1/* 2 * Copyright �� 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28#include <linux/iopoll.h> 29#include <linux/string_helpers.h> 30 31#include <drm/display/drm_scdc_helper.h> 32#include <drm/drm_privacy_screen_consumer.h> 33 34#include "i915_drv.h" 35#include "i915_reg.h" 36#include "icl_dsi.h" 37#include "intel_audio.h" 38#include "intel_audio_regs.h" 39#include "intel_backlight.h" 40#include "intel_combo_phy.h" 41#include "intel_combo_phy_regs.h" 42#include "intel_connector.h" 43#include "intel_crtc.h" 44#include "intel_cx0_phy.h" 45#include "intel_cx0_phy_regs.h" 46#include "intel_ddi.h" 47#include "intel_ddi_buf_trans.h" 48#include "intel_de.h" 49#include "intel_display_power.h" 50#include "intel_display_types.h" 51#include "intel_dkl_phy.h" 52#include "intel_dkl_phy_regs.h" 53#include "intel_dp.h" 54#include "intel_dp_aux.h" 55#include "intel_dp_link_training.h" 56#include "intel_dp_mst.h" 57#include "intel_dp_tunnel.h" 58#include "intel_dpio_phy.h" 59#include "intel_dsi.h" 60#include "intel_fdi.h" 61#include "intel_fifo_underrun.h" 62#include "intel_gmbus.h" 63#include "intel_hdcp.h" 64#include "intel_hdmi.h" 65#include "intel_hotplug.h" 66#include "intel_hti.h" 67#include "intel_lspcon.h" 68#include "intel_mg_phy_regs.h" 69#include "intel_modeset_lock.h" 70#include "intel_pps.h" 71#include "intel_psr.h" 72#include "intel_quirks.h" 73#include "intel_snps_phy.h" 74#include "intel_tc.h" 75#include "intel_vdsc.h" 76#include "intel_vdsc_regs.h" 77#include "skl_scaler.h" 78#include "skl_universal_plane.h" 79 80static const u8 index_to_dp_signal_levels[] = { 81 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 82 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 83 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 84 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 85 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 86 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 87 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 88 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 89 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 90 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 91}; 92 93static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 94 const struct intel_ddi_buf_trans *trans) 95{ 96 int level; 97 98 level = intel_bios_hdmi_level_shift(encoder->devdata); 99 if (level < 0) 100 level = trans->hdmi_default_entry; 101 102 return level; 103} 104 105static bool has_buf_trans_select(struct drm_i915_private *i915) 106{ 107 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 108} 109 110static bool has_iboost(struct drm_i915_private *i915) 111{ 112 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 113} 114 115/* 116 * Starting with Haswell, DDI port buffers must be programmed with correct 117 * values in advance. This function programs the correct values for 118 * DP/eDP/FDI use cases. 119 */ 120void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 121 const struct intel_crtc_state *crtc_state) 122{ 123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 124 u32 iboost_bit = 0; 125 int i, n_entries; 126 enum port port = encoder->port; 127 const struct intel_ddi_buf_trans *trans; 128 129 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 130 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 131 return; 132 133 /* If we're boosting the current, set bit 31 of trans1 */ 134 if (has_iboost(dev_priv) && 135 intel_bios_dp_boost_level(encoder->devdata)) 136 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 137 138 for (i = 0; i < n_entries; i++) { 139 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 140 trans->entries[i].hsw.trans1 | iboost_bit); 141 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 142 trans->entries[i].hsw.trans2); 143 } 144} 145 146/* 147 * Starting with Haswell, DDI port buffers must be programmed with correct 148 * values in advance. This function programs the correct values for 149 * HDMI/DVI use cases. 150 */ 151static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 152 const struct intel_crtc_state *crtc_state) 153{ 154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 155 int level = intel_ddi_level(encoder, crtc_state, 0); 156 u32 iboost_bit = 0; 157 int n_entries; 158 enum port port = encoder->port; 159 const struct intel_ddi_buf_trans *trans; 160 161 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 162 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 163 return; 164 165 /* If we're boosting the current, set bit 31 of trans1 */ 166 if (has_iboost(dev_priv) && 167 intel_bios_hdmi_boost_level(encoder->devdata)) 168 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 169 170 /* Entry 9 is for HDMI: */ 171 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 172 trans->entries[level].hsw.trans1 | iboost_bit); 173 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 174 trans->entries[level].hsw.trans2); 175} 176 177static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 178{ 179 int ret; 180 181 /* FIXME: find out why Bspec's 100us timeout is too short */ 182 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 183 XELPDP_PORT_BUF_PHY_IDLE), 10000); 184 if (ret) 185 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 186 port_name(port)); 187} 188 189void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 190 enum port port) 191{ 192 if (IS_BROXTON(dev_priv)) { 193 udelay(16); 194 return; 195 } 196 197 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 198 DDI_BUF_IS_IDLE), 8)) 199 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 200 port_name(port)); 201} 202 203static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 204 enum port port) 205{ 206 enum phy phy = intel_port_to_phy(dev_priv, port); 207 int timeout_us; 208 int ret; 209 210 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 211 if (DISPLAY_VER(dev_priv) < 10) { 212 usleep_range(518, 1000); 213 return; 214 } 215 216 if (DISPLAY_VER(dev_priv) >= 14) { 217 timeout_us = 10000; 218 } else if (IS_DG2(dev_priv)) { 219 timeout_us = 1200; 220 } else if (DISPLAY_VER(dev_priv) >= 12) { 221 if (intel_phy_is_tc(dev_priv, phy)) 222 timeout_us = 3000; 223 else 224 timeout_us = 1000; 225 } else { 226 timeout_us = 500; 227 } 228 229 if (DISPLAY_VER(dev_priv) >= 14) 230 ret = _wait_for(!(intel_de_read(dev_priv, 231 XELPDP_PORT_BUF_CTL1(dev_priv, port)) & 232 XELPDP_PORT_BUF_PHY_IDLE), 233 timeout_us, 10, 10); 234 else 235 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 236 timeout_us, 10, 10); 237 238 if (ret) 239 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 240 port_name(port)); 241} 242 243static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 244{ 245 switch (pll->info->id) { 246 case DPLL_ID_WRPLL1: 247 return PORT_CLK_SEL_WRPLL1; 248 case DPLL_ID_WRPLL2: 249 return PORT_CLK_SEL_WRPLL2; 250 case DPLL_ID_SPLL: 251 return PORT_CLK_SEL_SPLL; 252 case DPLL_ID_LCPLL_810: 253 return PORT_CLK_SEL_LCPLL_810; 254 case DPLL_ID_LCPLL_1350: 255 return PORT_CLK_SEL_LCPLL_1350; 256 case DPLL_ID_LCPLL_2700: 257 return PORT_CLK_SEL_LCPLL_2700; 258 default: 259 MISSING_CASE(pll->info->id); 260 return PORT_CLK_SEL_NONE; 261 } 262} 263 264static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 265 const struct intel_crtc_state *crtc_state) 266{ 267 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 268 int clock = crtc_state->port_clock; 269 const enum intel_dpll_id id = pll->info->id; 270 271 switch (id) { 272 default: 273 /* 274 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 275 * here, so do warn if this get passed in 276 */ 277 MISSING_CASE(id); 278 return DDI_CLK_SEL_NONE; 279 case DPLL_ID_ICL_TBTPLL: 280 switch (clock) { 281 case 162000: 282 return DDI_CLK_SEL_TBT_162; 283 case 270000: 284 return DDI_CLK_SEL_TBT_270; 285 case 540000: 286 return DDI_CLK_SEL_TBT_540; 287 case 810000: 288 return DDI_CLK_SEL_TBT_810; 289 default: 290 MISSING_CASE(clock); 291 return DDI_CLK_SEL_NONE; 292 } 293 case DPLL_ID_ICL_MGPLL1: 294 case DPLL_ID_ICL_MGPLL2: 295 case DPLL_ID_ICL_MGPLL3: 296 case DPLL_ID_ICL_MGPLL4: 297 case DPLL_ID_TGL_MGPLL5: 298 case DPLL_ID_TGL_MGPLL6: 299 return DDI_CLK_SEL_MG; 300 } 301} 302 303static u32 ddi_buf_phy_link_rate(int port_clock) 304{ 305 switch (port_clock) { 306 case 162000: 307 return DDI_BUF_PHY_LINK_RATE(0); 308 case 216000: 309 return DDI_BUF_PHY_LINK_RATE(4); 310 case 243000: 311 return DDI_BUF_PHY_LINK_RATE(5); 312 case 270000: 313 return DDI_BUF_PHY_LINK_RATE(1); 314 case 324000: 315 return DDI_BUF_PHY_LINK_RATE(6); 316 case 432000: 317 return DDI_BUF_PHY_LINK_RATE(7); 318 case 540000: 319 return DDI_BUF_PHY_LINK_RATE(2); 320 case 810000: 321 return DDI_BUF_PHY_LINK_RATE(3); 322 default: 323 MISSING_CASE(port_clock); 324 return DDI_BUF_PHY_LINK_RATE(0); 325 } 326} 327 328static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 329 const struct intel_crtc_state *crtc_state) 330{ 331 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 332 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 333 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 334 enum phy phy = intel_port_to_phy(i915, encoder->port); 335 336 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 337 intel_dp->DP = dig_port->saved_port_bits | 338 DDI_PORT_WIDTH(crtc_state->lane_count) | 339 DDI_BUF_TRANS_SELECT(0); 340 341 if (DISPLAY_VER(i915) >= 14) { 342 if (intel_dp_is_uhbr(crtc_state)) 343 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 344 else 345 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 346 } 347 348 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 349 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 350 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 351 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 352 } 353} 354 355static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 356 enum port port) 357{ 358 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 359 360 switch (val) { 361 case DDI_CLK_SEL_NONE: 362 return 0; 363 case DDI_CLK_SEL_TBT_162: 364 return 162000; 365 case DDI_CLK_SEL_TBT_270: 366 return 270000; 367 case DDI_CLK_SEL_TBT_540: 368 return 540000; 369 case DDI_CLK_SEL_TBT_810: 370 return 810000; 371 default: 372 MISSING_CASE(val); 373 return 0; 374 } 375} 376 377static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 378{ 379 /* CRT dotclock is determined via other means */ 380 if (pipe_config->has_pch_encoder) 381 return; 382 383 pipe_config->hw.adjusted_mode.crtc_clock = 384 intel_crtc_dotclock(pipe_config); 385} 386 387void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 388 const struct drm_connector_state *conn_state) 389{ 390 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 392 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 393 u32 temp; 394 395 if (!intel_crtc_has_dp_encoder(crtc_state)) 396 return; 397 398 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 399 400 temp = DP_MSA_MISC_SYNC_CLOCK; 401 402 switch (crtc_state->pipe_bpp) { 403 case 18: 404 temp |= DP_MSA_MISC_6_BPC; 405 break; 406 case 24: 407 temp |= DP_MSA_MISC_8_BPC; 408 break; 409 case 30: 410 temp |= DP_MSA_MISC_10_BPC; 411 break; 412 case 36: 413 temp |= DP_MSA_MISC_12_BPC; 414 break; 415 default: 416 MISSING_CASE(crtc_state->pipe_bpp); 417 break; 418 } 419 420 /* nonsense combination */ 421 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 422 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 423 424 if (crtc_state->limited_color_range) 425 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 426 427 /* 428 * As per DP 1.2 spec section 2.3.4.3 while sending 429 * YCBCR 444 signals we should program MSA MISC1/0 fields with 430 * colorspace information. 431 */ 432 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 433 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 434 435 /* 436 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 437 * of Color Encoding Format and Content Color Gamut] while sending 438 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 439 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 440 */ 441 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 442 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 443 444 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 445} 446 447static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 448{ 449 if (master_transcoder == TRANSCODER_EDP) 450 return 0; 451 else 452 return master_transcoder + 1; 453} 454 455static void 456intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 457 const struct intel_crtc_state *crtc_state) 458{ 459 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 460 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 461 u32 val = 0; 462 463 if (intel_dp_is_uhbr(crtc_state)) 464 val = TRANS_DP2_128B132B_CHANNEL_CODING; 465 466 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 467} 468 469/* 470 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 471 * 472 * Only intended to be used by intel_ddi_enable_transcoder_func() and 473 * intel_ddi_config_transcoder_func(). 474 */ 475static u32 476intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 477 const struct intel_crtc_state *crtc_state) 478{ 479 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 480 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 481 enum pipe pipe = crtc->pipe; 482 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 483 enum port port = encoder->port; 484 u32 temp; 485 486 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 487 temp = TRANS_DDI_FUNC_ENABLE; 488 if (DISPLAY_VER(dev_priv) >= 12) 489 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 490 else 491 temp |= TRANS_DDI_SELECT_PORT(port); 492 493 switch (crtc_state->pipe_bpp) { 494 default: 495 MISSING_CASE(crtc_state->pipe_bpp); 496 fallthrough; 497 case 18: 498 temp |= TRANS_DDI_BPC_6; 499 break; 500 case 24: 501 temp |= TRANS_DDI_BPC_8; 502 break; 503 case 30: 504 temp |= TRANS_DDI_BPC_10; 505 break; 506 case 36: 507 temp |= TRANS_DDI_BPC_12; 508 break; 509 } 510 511 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 512 temp |= TRANS_DDI_PVSYNC; 513 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 514 temp |= TRANS_DDI_PHSYNC; 515 516 if (cpu_transcoder == TRANSCODER_EDP) { 517 switch (pipe) { 518 default: 519 MISSING_CASE(pipe); 520 fallthrough; 521 case PIPE_A: 522 /* On Haswell, can only use the always-on power well for 523 * eDP when not using the panel fitter, and when not 524 * using motion blur mitigation (which we don't 525 * support). */ 526 if (crtc_state->pch_pfit.force_thru) 527 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 528 else 529 temp |= TRANS_DDI_EDP_INPUT_A_ON; 530 break; 531 case PIPE_B: 532 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 533 break; 534 case PIPE_C: 535 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 536 break; 537 } 538 } 539 540 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 541 if (crtc_state->has_hdmi_sink) 542 temp |= TRANS_DDI_MODE_SELECT_HDMI; 543 else 544 temp |= TRANS_DDI_MODE_SELECT_DVI; 545 546 if (crtc_state->hdmi_scrambling) 547 temp |= TRANS_DDI_HDMI_SCRAMBLING; 548 if (crtc_state->hdmi_high_tmds_clock_ratio) 549 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 550 if (DISPLAY_VER(dev_priv) >= 14) 551 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 552 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 553 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 554 temp |= (crtc_state->fdi_lanes - 1) << 1; 555 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 556 if (intel_dp_is_uhbr(crtc_state)) 557 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 558 else 559 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 560 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 561 562 if (DISPLAY_VER(dev_priv) >= 12) { 563 enum transcoder master; 564 565 master = crtc_state->mst_master_transcoder; 566 drm_WARN_ON(&dev_priv->drm, 567 master == INVALID_TRANSCODER); 568 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 569 } 570 } else { 571 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 572 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 573 } 574 575 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 576 crtc_state->master_transcoder != INVALID_TRANSCODER) { 577 u8 master_select = 578 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 579 580 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 581 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 582 } 583 584 return temp; 585} 586 587void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 588 const struct intel_crtc_state *crtc_state) 589{ 590 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 592 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 593 594 if (DISPLAY_VER(dev_priv) >= 11) { 595 enum transcoder master_transcoder = crtc_state->master_transcoder; 596 u32 ctl2 = 0; 597 598 if (master_transcoder != INVALID_TRANSCODER) { 599 u8 master_select = 600 bdw_trans_port_sync_master_select(master_transcoder); 601 602 ctl2 |= PORT_SYNC_MODE_ENABLE | 603 PORT_SYNC_MODE_MASTER_SELECT(master_select); 604 } 605 606 intel_de_write(dev_priv, 607 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 608 } 609 610 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 611 intel_ddi_transcoder_func_reg_val_get(encoder, 612 crtc_state)); 613} 614 615/* 616 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 617 * bit. 618 */ 619static void 620intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 621 const struct intel_crtc_state *crtc_state) 622{ 623 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 624 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 625 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 626 u32 ctl; 627 628 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 629 ctl &= ~TRANS_DDI_FUNC_ENABLE; 630 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 631} 632 633void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 634{ 635 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 637 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 638 u32 ctl; 639 640 if (DISPLAY_VER(dev_priv) >= 11) 641 intel_de_write(dev_priv, 642 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 643 644 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 645 646 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 647 648 ctl &= ~TRANS_DDI_FUNC_ENABLE; 649 650 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 651 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 652 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 653 654 if (DISPLAY_VER(dev_priv) >= 12) { 655 if (!intel_dp_mst_is_master_trans(crtc_state)) { 656 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 657 TRANS_DDI_MODE_SELECT_MASK); 658 } 659 } else { 660 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 661 } 662 663 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 664 665 if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) && 666 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 667 drm_dbg_kms(&dev_priv->drm, 668 "Quirk Increase DDI disabled time\n"); 669 /* Quirk time at 100ms for reliable operation */ 670 msleep(100); 671 } 672} 673 674int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 675 enum transcoder cpu_transcoder, 676 bool enable, u32 hdcp_mask) 677{ 678 struct drm_device *dev = intel_encoder->base.dev; 679 struct drm_i915_private *dev_priv = to_i915(dev); 680 intel_wakeref_t wakeref; 681 int ret = 0; 682 683 wakeref = intel_display_power_get_if_enabled(dev_priv, 684 intel_encoder->power_domain); 685 if (drm_WARN_ON(dev, !wakeref)) 686 return -ENXIO; 687 688 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 689 hdcp_mask, enable ? hdcp_mask : 0); 690 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 691 return ret; 692} 693 694bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 695{ 696 struct drm_device *dev = intel_connector->base.dev; 697 struct drm_i915_private *dev_priv = to_i915(dev); 698 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 699 int type = intel_connector->base.connector_type; 700 enum port port = encoder->port; 701 enum transcoder cpu_transcoder; 702 intel_wakeref_t wakeref; 703 enum pipe pipe = 0; 704 u32 tmp; 705 bool ret; 706 707 wakeref = intel_display_power_get_if_enabled(dev_priv, 708 encoder->power_domain); 709 if (!wakeref) 710 return false; 711 712 if (!encoder->get_hw_state(encoder, &pipe)) { 713 ret = false; 714 goto out; 715 } 716 717 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 718 cpu_transcoder = TRANSCODER_EDP; 719 else 720 cpu_transcoder = (enum transcoder) pipe; 721 722 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 723 724 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 725 case TRANS_DDI_MODE_SELECT_HDMI: 726 case TRANS_DDI_MODE_SELECT_DVI: 727 ret = type == DRM_MODE_CONNECTOR_HDMIA; 728 break; 729 730 case TRANS_DDI_MODE_SELECT_DP_SST: 731 ret = type == DRM_MODE_CONNECTOR_eDP || 732 type == DRM_MODE_CONNECTOR_DisplayPort; 733 break; 734 735 case TRANS_DDI_MODE_SELECT_DP_MST: 736 /* if the transcoder is in MST state then 737 * connector isn't connected */ 738 ret = false; 739 break; 740 741 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 742 if (HAS_DP20(dev_priv)) 743 /* 128b/132b */ 744 ret = false; 745 else 746 /* FDI */ 747 ret = type == DRM_MODE_CONNECTOR_VGA; 748 break; 749 750 default: 751 ret = false; 752 break; 753 } 754 755out: 756 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 757 758 return ret; 759} 760 761static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 762 u8 *pipe_mask, bool *is_dp_mst) 763{ 764 struct drm_device *dev = encoder->base.dev; 765 struct drm_i915_private *dev_priv = to_i915(dev); 766 enum port port = encoder->port; 767 intel_wakeref_t wakeref; 768 enum pipe p; 769 u32 tmp; 770 u8 mst_pipe_mask; 771 772 *pipe_mask = 0; 773 *is_dp_mst = false; 774 775 wakeref = intel_display_power_get_if_enabled(dev_priv, 776 encoder->power_domain); 777 if (!wakeref) 778 return; 779 780 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 781 if (!(tmp & DDI_BUF_CTL_ENABLE)) 782 goto out; 783 784 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 785 tmp = intel_de_read(dev_priv, 786 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 787 788 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 789 default: 790 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 791 fallthrough; 792 case TRANS_DDI_EDP_INPUT_A_ON: 793 case TRANS_DDI_EDP_INPUT_A_ONOFF: 794 *pipe_mask = BIT(PIPE_A); 795 break; 796 case TRANS_DDI_EDP_INPUT_B_ONOFF: 797 *pipe_mask = BIT(PIPE_B); 798 break; 799 case TRANS_DDI_EDP_INPUT_C_ONOFF: 800 *pipe_mask = BIT(PIPE_C); 801 break; 802 } 803 804 goto out; 805 } 806 807 mst_pipe_mask = 0; 808 for_each_pipe(dev_priv, p) { 809 enum transcoder cpu_transcoder = (enum transcoder)p; 810 unsigned int port_mask, ddi_select; 811 intel_wakeref_t trans_wakeref; 812 813 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 814 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 815 if (!trans_wakeref) 816 continue; 817 818 if (DISPLAY_VER(dev_priv) >= 12) { 819 port_mask = TGL_TRANS_DDI_PORT_MASK; 820 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 821 } else { 822 port_mask = TRANS_DDI_PORT_MASK; 823 ddi_select = TRANS_DDI_SELECT_PORT(port); 824 } 825 826 tmp = intel_de_read(dev_priv, 827 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 828 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 829 trans_wakeref); 830 831 if ((tmp & port_mask) != ddi_select) 832 continue; 833 834 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 835 (HAS_DP20(dev_priv) && 836 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 837 mst_pipe_mask |= BIT(p); 838 839 *pipe_mask |= BIT(p); 840 } 841 842 if (!*pipe_mask) 843 drm_dbg_kms(&dev_priv->drm, 844 "No pipe for [ENCODER:%d:%s] found\n", 845 encoder->base.base.id, encoder->base.name); 846 847 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 848 drm_dbg_kms(&dev_priv->drm, 849 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 850 encoder->base.base.id, encoder->base.name, 851 *pipe_mask); 852 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 853 } 854 855 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 856 drm_dbg_kms(&dev_priv->drm, 857 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 858 encoder->base.base.id, encoder->base.name, 859 *pipe_mask, mst_pipe_mask); 860 else 861 *is_dp_mst = mst_pipe_mask; 862 863out: 864 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 865 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 866 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 867 BXT_PHY_LANE_POWERDOWN_ACK | 868 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 869 drm_err(&dev_priv->drm, 870 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 871 encoder->base.base.id, encoder->base.name, tmp); 872 } 873 874 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 875} 876 877bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 878 enum pipe *pipe) 879{ 880 u8 pipe_mask; 881 bool is_mst; 882 883 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 884 885 if (is_mst || !pipe_mask) 886 return false; 887 888 *pipe = ffs(pipe_mask) - 1; 889 890 return true; 891} 892 893static enum intel_display_power_domain 894intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 895 const struct intel_crtc_state *crtc_state) 896{ 897 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 898 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 899 900 /* 901 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 902 * DC states enabled at the same time, while for driver initiated AUX 903 * transfers we need the same AUX IOs to be powered but with DC states 904 * disabled. Accordingly use the AUX_IO_<port> power domain here which 905 * leaves DC states enabled. 906 * 907 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 908 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 909 * well, so we can acquire a wider AUX_<port> power domain reference 910 * instead of a specific AUX_IO_<port> reference without powering up any 911 * extra wells. 912 */ 913 if (intel_encoder_can_psr(&dig_port->base)) 914 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 915 else if (DISPLAY_VER(i915) < 14 && 916 (intel_crtc_has_dp_encoder(crtc_state) || 917 intel_phy_is_tc(i915, phy))) 918 return intel_aux_power_domain(dig_port); 919 else 920 return POWER_DOMAIN_INVALID; 921} 922 923static void 924main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 925 const struct intel_crtc_state *crtc_state) 926{ 927 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 928 enum intel_display_power_domain domain = 929 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 930 931 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 932 933 if (domain == POWER_DOMAIN_INVALID) 934 return; 935 936 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 937} 938 939static void 940main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 941 const struct intel_crtc_state *crtc_state) 942{ 943 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 944 enum intel_display_power_domain domain = 945 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 946 intel_wakeref_t wf; 947 948 wf = fetch_and_zero(&dig_port->aux_wakeref); 949 if (!wf) 950 return; 951 952 intel_display_power_put(i915, domain, wf); 953} 954 955static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 956 struct intel_crtc_state *crtc_state) 957{ 958 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 959 struct intel_digital_port *dig_port; 960 961 /* 962 * TODO: Add support for MST encoders. Atm, the following should never 963 * happen since fake-MST encoders don't set their get_power_domains() 964 * hook. 965 */ 966 if (drm_WARN_ON(&dev_priv->drm, 967 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 968 return; 969 970 dig_port = enc_to_dig_port(encoder); 971 972 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 973 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 974 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 975 dig_port->ddi_io_power_domain); 976 } 977 978 main_link_aux_power_domain_get(dig_port, crtc_state); 979} 980 981void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 982 const struct intel_crtc_state *crtc_state) 983{ 984 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 985 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 986 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 987 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 988 u32 val; 989 990 if (cpu_transcoder == TRANSCODER_EDP) 991 return; 992 993 if (DISPLAY_VER(dev_priv) >= 13) 994 val = TGL_TRANS_CLK_SEL_PORT(phy); 995 else if (DISPLAY_VER(dev_priv) >= 12) 996 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 997 else 998 val = TRANS_CLK_SEL_PORT(encoder->port); 999 1000 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1001} 1002 1003void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1004{ 1005 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1006 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1007 u32 val; 1008 1009 if (cpu_transcoder == TRANSCODER_EDP) 1010 return; 1011 1012 if (DISPLAY_VER(dev_priv) >= 12) 1013 val = TGL_TRANS_CLK_SEL_DISABLED; 1014 else 1015 val = TRANS_CLK_SEL_DISABLED; 1016 1017 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1018} 1019 1020static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1021 enum port port, u8 iboost) 1022{ 1023 u32 tmp; 1024 1025 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1026 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1027 if (iboost) 1028 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1029 else 1030 tmp |= BALANCE_LEG_DISABLE(port); 1031 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1032} 1033 1034static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1035 const struct intel_crtc_state *crtc_state, 1036 int level) 1037{ 1038 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1039 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1040 u8 iboost; 1041 1042 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1043 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1044 else 1045 iboost = intel_bios_dp_boost_level(encoder->devdata); 1046 1047 if (iboost == 0) { 1048 const struct intel_ddi_buf_trans *trans; 1049 int n_entries; 1050 1051 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1052 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1053 return; 1054 1055 iboost = trans->entries[level].hsw.i_boost; 1056 } 1057 1058 /* Make sure that the requested I_boost is valid */ 1059 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1060 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1061 return; 1062 } 1063 1064 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1065 1066 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1067 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1068} 1069 1070static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1071 const struct intel_crtc_state *crtc_state) 1072{ 1073 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1074 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1075 int n_entries; 1076 1077 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1078 1079 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1080 n_entries = 1; 1081 if (drm_WARN_ON(&dev_priv->drm, 1082 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1083 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1084 1085 return index_to_dp_signal_levels[n_entries - 1] & 1086 DP_TRAIN_VOLTAGE_SWING_MASK; 1087} 1088 1089/* 1090 * We assume that the full set of pre-emphasis values can be 1091 * used on all DDI platforms. Should that change we need to 1092 * rethink this code. 1093 */ 1094static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1095{ 1096 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1097} 1098 1099static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1100 int lane) 1101{ 1102 if (crtc_state->port_clock > 600000) 1103 return 0; 1104 1105 if (crtc_state->lane_count == 4) 1106 return lane >= 1 ? LOADGEN_SELECT : 0; 1107 else 1108 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1109} 1110 1111static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1112 const struct intel_crtc_state *crtc_state) 1113{ 1114 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1115 const struct intel_ddi_buf_trans *trans; 1116 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1117 int n_entries, ln; 1118 u32 val; 1119 1120 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1121 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1122 return; 1123 1124 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1125 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1126 1127 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1128 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1129 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1130 intel_dp->hobl_active ? val : 0); 1131 } 1132 1133 /* Set PORT_TX_DW5 */ 1134 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1135 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1136 TAP2_DISABLE | TAP3_DISABLE); 1137 val |= SCALING_MODE_SEL(0x2); 1138 val |= RTERM_SELECT(0x6); 1139 val |= TAP3_DISABLE; 1140 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1141 1142 /* Program PORT_TX_DW2 */ 1143 for (ln = 0; ln < 4; ln++) { 1144 int level = intel_ddi_level(encoder, crtc_state, ln); 1145 1146 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1147 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1148 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1149 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1150 RCOMP_SCALAR(0x98)); 1151 } 1152 1153 /* Program PORT_TX_DW4 */ 1154 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1155 for (ln = 0; ln < 4; ln++) { 1156 int level = intel_ddi_level(encoder, crtc_state, ln); 1157 1158 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1159 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1160 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1161 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1162 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1163 } 1164 1165 /* Program PORT_TX_DW7 */ 1166 for (ln = 0; ln < 4; ln++) { 1167 int level = intel_ddi_level(encoder, crtc_state, ln); 1168 1169 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1170 N_SCALAR_MASK, 1171 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1172 } 1173} 1174 1175static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1176 const struct intel_crtc_state *crtc_state) 1177{ 1178 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1179 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1180 u32 val; 1181 int ln; 1182 1183 /* 1184 * 1. If port type is eDP or DP, 1185 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1186 * else clear to 0b. 1187 */ 1188 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1189 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1190 val &= ~COMMON_KEEPER_EN; 1191 else 1192 val |= COMMON_KEEPER_EN; 1193 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1194 1195 /* 2. Program loadgen select */ 1196 /* 1197 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1198 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1199 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1200 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1201 */ 1202 for (ln = 0; ln < 4; ln++) { 1203 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1204 LOADGEN_SELECT, 1205 icl_combo_phy_loadgen_select(crtc_state, ln)); 1206 } 1207 1208 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1209 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1210 0, SUS_CLOCK_CONFIG); 1211 1212 /* 4. Clear training enable to change swing values */ 1213 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1214 val &= ~TX_TRAINING_EN; 1215 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1216 1217 /* 5. Program swing and de-emphasis */ 1218 icl_ddi_combo_vswing_program(encoder, crtc_state); 1219 1220 /* 6. Set training enable to trigger update */ 1221 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1222 val |= TX_TRAINING_EN; 1223 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1224} 1225 1226static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1227 const struct intel_crtc_state *crtc_state) 1228{ 1229 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1230 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1231 const struct intel_ddi_buf_trans *trans; 1232 int n_entries, ln; 1233 1234 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1235 return; 1236 1237 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1238 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1239 return; 1240 1241 for (ln = 0; ln < 2; ln++) { 1242 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1243 CRI_USE_FS32, 0); 1244 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1245 CRI_USE_FS32, 0); 1246 } 1247 1248 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1249 for (ln = 0; ln < 2; ln++) { 1250 int level; 1251 1252 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1253 1254 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1255 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1256 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1257 1258 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1259 1260 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1261 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1262 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1263 } 1264 1265 /* Program MG_TX_DRVCTRL with values from vswing table */ 1266 for (ln = 0; ln < 2; ln++) { 1267 int level; 1268 1269 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1270 1271 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1272 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1273 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1274 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1275 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1276 CRI_TXDEEMPH_OVERRIDE_EN); 1277 1278 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1279 1280 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1281 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1282 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1283 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1284 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1285 CRI_TXDEEMPH_OVERRIDE_EN); 1286 1287 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1288 } 1289 1290 /* 1291 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1292 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1293 * values from table for which TX1 and TX2 enabled. 1294 */ 1295 for (ln = 0; ln < 2; ln++) { 1296 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1297 CFG_LOW_RATE_LKREN_EN, 1298 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1299 } 1300 1301 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1302 for (ln = 0; ln < 2; ln++) { 1303 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1304 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1305 CFG_AMI_CK_DIV_OVERRIDE_EN, 1306 crtc_state->port_clock > 500000 ? 1307 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1308 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1309 1310 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1311 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1312 CFG_AMI_CK_DIV_OVERRIDE_EN, 1313 crtc_state->port_clock > 500000 ? 1314 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1315 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1316 } 1317 1318 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1319 for (ln = 0; ln < 2; ln++) { 1320 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1321 0, CRI_CALCINIT); 1322 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1323 0, CRI_CALCINIT); 1324 } 1325} 1326 1327static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1328 const struct intel_crtc_state *crtc_state) 1329{ 1330 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1331 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1332 const struct intel_ddi_buf_trans *trans; 1333 int n_entries, ln; 1334 1335 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1336 return; 1337 1338 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1339 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1340 return; 1341 1342 for (ln = 0; ln < 2; ln++) { 1343 int level; 1344 1345 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1346 1347 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1348 1349 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1350 DKL_TX_PRESHOOT_COEFF_MASK | 1351 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1352 DKL_TX_VSWING_CONTROL_MASK, 1353 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1354 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1355 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1356 1357 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1358 1359 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1360 DKL_TX_PRESHOOT_COEFF_MASK | 1361 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1362 DKL_TX_VSWING_CONTROL_MASK, 1363 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1364 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1365 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1366 1367 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1368 DKL_TX_DP20BITMODE, 0); 1369 1370 if (IS_ALDERLAKE_P(dev_priv)) { 1371 u32 val; 1372 1373 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1374 if (ln == 0) { 1375 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1376 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1377 } else { 1378 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1379 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1380 } 1381 } else { 1382 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1383 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1384 } 1385 1386 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1387 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1388 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1389 val); 1390 } 1391 } 1392} 1393 1394static int translate_signal_level(struct intel_dp *intel_dp, 1395 u8 signal_levels) 1396{ 1397 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1398 int i; 1399 1400 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1401 if (index_to_dp_signal_levels[i] == signal_levels) 1402 return i; 1403 } 1404 1405 drm_WARN(&i915->drm, 1, 1406 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1407 signal_levels); 1408 1409 return 0; 1410} 1411 1412static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1413 const struct intel_crtc_state *crtc_state, 1414 int lane) 1415{ 1416 u8 train_set = intel_dp->train_set[lane]; 1417 1418 if (intel_dp_is_uhbr(crtc_state)) { 1419 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1420 } else { 1421 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1422 DP_TRAIN_PRE_EMPHASIS_MASK); 1423 1424 return translate_signal_level(intel_dp, signal_levels); 1425 } 1426} 1427 1428int intel_ddi_level(struct intel_encoder *encoder, 1429 const struct intel_crtc_state *crtc_state, 1430 int lane) 1431{ 1432 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1433 const struct intel_ddi_buf_trans *trans; 1434 int level, n_entries; 1435 1436 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1437 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1438 return 0; 1439 1440 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1441 level = intel_ddi_hdmi_level(encoder, trans); 1442 else 1443 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1444 lane); 1445 1446 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1447 level = n_entries - 1; 1448 1449 return level; 1450} 1451 1452static void 1453hsw_set_signal_levels(struct intel_encoder *encoder, 1454 const struct intel_crtc_state *crtc_state) 1455{ 1456 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1457 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1458 int level = intel_ddi_level(encoder, crtc_state, 0); 1459 enum port port = encoder->port; 1460 u32 signal_levels; 1461 1462 if (has_iboost(dev_priv)) 1463 skl_ddi_set_iboost(encoder, crtc_state, level); 1464 1465 /* HDMI ignores the rest */ 1466 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1467 return; 1468 1469 signal_levels = DDI_BUF_TRANS_SELECT(level); 1470 1471 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1472 signal_levels); 1473 1474 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1475 intel_dp->DP |= signal_levels; 1476 1477 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1478 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1479} 1480 1481static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1482 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1483{ 1484 mutex_lock(&i915->display.dpll.lock); 1485 1486 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1487 1488 /* 1489 * "This step and the step before must be 1490 * done with separate register writes." 1491 */ 1492 intel_de_rmw(i915, reg, clk_off, 0); 1493 1494 mutex_unlock(&i915->display.dpll.lock); 1495} 1496 1497static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1498 u32 clk_off) 1499{ 1500 mutex_lock(&i915->display.dpll.lock); 1501 1502 intel_de_rmw(i915, reg, 0, clk_off); 1503 1504 mutex_unlock(&i915->display.dpll.lock); 1505} 1506 1507static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1508 u32 clk_off) 1509{ 1510 return !(intel_de_read(i915, reg) & clk_off); 1511} 1512 1513static struct intel_shared_dpll * 1514_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1515 u32 clk_sel_mask, u32 clk_sel_shift) 1516{ 1517 enum intel_dpll_id id; 1518 1519 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1520 1521 return intel_get_shared_dpll_by_id(i915, id); 1522} 1523 1524static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1525 const struct intel_crtc_state *crtc_state) 1526{ 1527 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1528 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1529 enum phy phy = intel_port_to_phy(i915, encoder->port); 1530 1531 if (drm_WARN_ON(&i915->drm, !pll)) 1532 return; 1533 1534 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1535 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1536 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1537 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1538} 1539 1540static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1541{ 1542 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1543 enum phy phy = intel_port_to_phy(i915, encoder->port); 1544 1545 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1546 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1547} 1548 1549static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1550{ 1551 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1552 enum phy phy = intel_port_to_phy(i915, encoder->port); 1553 1554 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1555 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1556} 1557 1558static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1559{ 1560 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1561 enum phy phy = intel_port_to_phy(i915, encoder->port); 1562 1563 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1564 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1565 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1566} 1567 1568static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1569 const struct intel_crtc_state *crtc_state) 1570{ 1571 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1572 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1573 enum phy phy = intel_port_to_phy(i915, encoder->port); 1574 1575 if (drm_WARN_ON(&i915->drm, !pll)) 1576 return; 1577 1578 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1579 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1580 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1581 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1582} 1583 1584static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1585{ 1586 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1587 enum phy phy = intel_port_to_phy(i915, encoder->port); 1588 1589 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1590 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1591} 1592 1593static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1594{ 1595 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1596 enum phy phy = intel_port_to_phy(i915, encoder->port); 1597 1598 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1599 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1600} 1601 1602static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1603{ 1604 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1605 enum phy phy = intel_port_to_phy(i915, encoder->port); 1606 1607 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1608 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1609 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1610} 1611 1612static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1613 const struct intel_crtc_state *crtc_state) 1614{ 1615 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1616 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1617 enum phy phy = intel_port_to_phy(i915, encoder->port); 1618 1619 if (drm_WARN_ON(&i915->drm, !pll)) 1620 return; 1621 1622 /* 1623 * If we fail this, something went very wrong: first 2 PLLs should be 1624 * used by first 2 phys and last 2 PLLs by last phys 1625 */ 1626 if (drm_WARN_ON(&i915->drm, 1627 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1628 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1629 return; 1630 1631 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1632 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1633 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1634 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1635} 1636 1637static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1638{ 1639 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1640 enum phy phy = intel_port_to_phy(i915, encoder->port); 1641 1642 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1643 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1644} 1645 1646static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1647{ 1648 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1649 enum phy phy = intel_port_to_phy(i915, encoder->port); 1650 1651 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1652 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1653} 1654 1655static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1656{ 1657 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1658 enum phy phy = intel_port_to_phy(i915, encoder->port); 1659 enum intel_dpll_id id; 1660 u32 val; 1661 1662 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1663 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1664 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1665 id = val; 1666 1667 /* 1668 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1669 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1670 * bit for phy C and D. 1671 */ 1672 if (phy >= PHY_C) 1673 id += DPLL_ID_DG1_DPLL2; 1674 1675 return intel_get_shared_dpll_by_id(i915, id); 1676} 1677 1678static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1679 const struct intel_crtc_state *crtc_state) 1680{ 1681 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1682 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1683 enum phy phy = intel_port_to_phy(i915, encoder->port); 1684 1685 if (drm_WARN_ON(&i915->drm, !pll)) 1686 return; 1687 1688 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1689 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1690 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1691 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1692} 1693 1694static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1695{ 1696 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1697 enum phy phy = intel_port_to_phy(i915, encoder->port); 1698 1699 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1700 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1701} 1702 1703static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1704{ 1705 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1706 enum phy phy = intel_port_to_phy(i915, encoder->port); 1707 1708 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1709 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1710} 1711 1712struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1713{ 1714 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1715 enum phy phy = intel_port_to_phy(i915, encoder->port); 1716 1717 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1718 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1719 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1720} 1721 1722static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1723 const struct intel_crtc_state *crtc_state) 1724{ 1725 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1726 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1727 enum port port = encoder->port; 1728 1729 if (drm_WARN_ON(&i915->drm, !pll)) 1730 return; 1731 1732 /* 1733 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1734 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1735 */ 1736 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1737 1738 icl_ddi_combo_enable_clock(encoder, crtc_state); 1739} 1740 1741static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1742{ 1743 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1744 enum port port = encoder->port; 1745 1746 icl_ddi_combo_disable_clock(encoder); 1747 1748 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1749} 1750 1751static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1752{ 1753 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1754 enum port port = encoder->port; 1755 u32 tmp; 1756 1757 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1758 1759 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1760 return false; 1761 1762 return icl_ddi_combo_is_clock_enabled(encoder); 1763} 1764 1765static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1766 const struct intel_crtc_state *crtc_state) 1767{ 1768 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1769 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1770 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1771 enum port port = encoder->port; 1772 1773 if (drm_WARN_ON(&i915->drm, !pll)) 1774 return; 1775 1776 intel_de_write(i915, DDI_CLK_SEL(port), 1777 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1778 1779 mutex_lock(&i915->display.dpll.lock); 1780 1781 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1782 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1783 1784 mutex_unlock(&i915->display.dpll.lock); 1785} 1786 1787static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1788{ 1789 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1790 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1791 enum port port = encoder->port; 1792 1793 mutex_lock(&i915->display.dpll.lock); 1794 1795 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1796 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1797 1798 mutex_unlock(&i915->display.dpll.lock); 1799 1800 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1801} 1802 1803static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1804{ 1805 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1806 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1807 enum port port = encoder->port; 1808 u32 tmp; 1809 1810 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1811 1812 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1813 return false; 1814 1815 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1816 1817 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1818} 1819 1820static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1821{ 1822 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1823 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1824 enum port port = encoder->port; 1825 enum intel_dpll_id id; 1826 u32 tmp; 1827 1828 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1829 1830 switch (tmp & DDI_CLK_SEL_MASK) { 1831 case DDI_CLK_SEL_TBT_162: 1832 case DDI_CLK_SEL_TBT_270: 1833 case DDI_CLK_SEL_TBT_540: 1834 case DDI_CLK_SEL_TBT_810: 1835 id = DPLL_ID_ICL_TBTPLL; 1836 break; 1837 case DDI_CLK_SEL_MG: 1838 id = icl_tc_port_to_pll_id(tc_port); 1839 break; 1840 default: 1841 MISSING_CASE(tmp); 1842 fallthrough; 1843 case DDI_CLK_SEL_NONE: 1844 return NULL; 1845 } 1846 1847 return intel_get_shared_dpll_by_id(i915, id); 1848} 1849 1850static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1851{ 1852 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1853 enum intel_dpll_id id; 1854 1855 switch (encoder->port) { 1856 case PORT_A: 1857 id = DPLL_ID_SKL_DPLL0; 1858 break; 1859 case PORT_B: 1860 id = DPLL_ID_SKL_DPLL1; 1861 break; 1862 case PORT_C: 1863 id = DPLL_ID_SKL_DPLL2; 1864 break; 1865 default: 1866 MISSING_CASE(encoder->port); 1867 return NULL; 1868 } 1869 1870 return intel_get_shared_dpll_by_id(i915, id); 1871} 1872 1873static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1874 const struct intel_crtc_state *crtc_state) 1875{ 1876 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1877 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1878 enum port port = encoder->port; 1879 1880 if (drm_WARN_ON(&i915->drm, !pll)) 1881 return; 1882 1883 mutex_lock(&i915->display.dpll.lock); 1884 1885 intel_de_rmw(i915, DPLL_CTRL2, 1886 DPLL_CTRL2_DDI_CLK_OFF(port) | 1887 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1888 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1889 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1890 1891 mutex_unlock(&i915->display.dpll.lock); 1892} 1893 1894static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1895{ 1896 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1897 enum port port = encoder->port; 1898 1899 mutex_lock(&i915->display.dpll.lock); 1900 1901 intel_de_rmw(i915, DPLL_CTRL2, 1902 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1903 1904 mutex_unlock(&i915->display.dpll.lock); 1905} 1906 1907static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1908{ 1909 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1910 enum port port = encoder->port; 1911 1912 /* 1913 * FIXME Not sure if the override affects both 1914 * the PLL selection and the CLK_OFF bit. 1915 */ 1916 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1917} 1918 1919static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1920{ 1921 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1922 enum port port = encoder->port; 1923 enum intel_dpll_id id; 1924 u32 tmp; 1925 1926 tmp = intel_de_read(i915, DPLL_CTRL2); 1927 1928 /* 1929 * FIXME Not sure if the override affects both 1930 * the PLL selection and the CLK_OFF bit. 1931 */ 1932 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1933 return NULL; 1934 1935 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1936 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1937 1938 return intel_get_shared_dpll_by_id(i915, id); 1939} 1940 1941void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1942 const struct intel_crtc_state *crtc_state) 1943{ 1944 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1945 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1946 enum port port = encoder->port; 1947 1948 if (drm_WARN_ON(&i915->drm, !pll)) 1949 return; 1950 1951 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1952} 1953 1954void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1955{ 1956 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1957 enum port port = encoder->port; 1958 1959 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1960} 1961 1962bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1963{ 1964 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1965 enum port port = encoder->port; 1966 1967 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1968} 1969 1970static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1971{ 1972 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1973 enum port port = encoder->port; 1974 enum intel_dpll_id id; 1975 u32 tmp; 1976 1977 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1978 1979 switch (tmp & PORT_CLK_SEL_MASK) { 1980 case PORT_CLK_SEL_WRPLL1: 1981 id = DPLL_ID_WRPLL1; 1982 break; 1983 case PORT_CLK_SEL_WRPLL2: 1984 id = DPLL_ID_WRPLL2; 1985 break; 1986 case PORT_CLK_SEL_SPLL: 1987 id = DPLL_ID_SPLL; 1988 break; 1989 case PORT_CLK_SEL_LCPLL_810: 1990 id = DPLL_ID_LCPLL_810; 1991 break; 1992 case PORT_CLK_SEL_LCPLL_1350: 1993 id = DPLL_ID_LCPLL_1350; 1994 break; 1995 case PORT_CLK_SEL_LCPLL_2700: 1996 id = DPLL_ID_LCPLL_2700; 1997 break; 1998 default: 1999 MISSING_CASE(tmp); 2000 fallthrough; 2001 case PORT_CLK_SEL_NONE: 2002 return NULL; 2003 } 2004 2005 return intel_get_shared_dpll_by_id(i915, id); 2006} 2007 2008void intel_ddi_enable_clock(struct intel_encoder *encoder, 2009 const struct intel_crtc_state *crtc_state) 2010{ 2011 if (encoder->enable_clock) 2012 encoder->enable_clock(encoder, crtc_state); 2013} 2014 2015void intel_ddi_disable_clock(struct intel_encoder *encoder) 2016{ 2017 if (encoder->disable_clock) 2018 encoder->disable_clock(encoder); 2019} 2020 2021void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2022{ 2023 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2024 u32 port_mask; 2025 bool ddi_clk_needed; 2026 2027 /* 2028 * In case of DP MST, we sanitize the primary encoder only, not the 2029 * virtual ones. 2030 */ 2031 if (encoder->type == INTEL_OUTPUT_DP_MST) 2032 return; 2033 2034 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2035 u8 pipe_mask; 2036 bool is_mst; 2037 2038 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2039 /* 2040 * In the unlikely case that BIOS enables DP in MST mode, just 2041 * warn since our MST HW readout is incomplete. 2042 */ 2043 if (drm_WARN_ON(&i915->drm, is_mst)) 2044 return; 2045 } 2046 2047 port_mask = BIT(encoder->port); 2048 ddi_clk_needed = encoder->base.crtc; 2049 2050 if (encoder->type == INTEL_OUTPUT_DSI) { 2051 struct intel_encoder *other_encoder; 2052 2053 port_mask = intel_dsi_encoder_ports(encoder); 2054 /* 2055 * Sanity check that we haven't incorrectly registered another 2056 * encoder using any of the ports of this DSI encoder. 2057 */ 2058 for_each_intel_encoder(&i915->drm, other_encoder) { 2059 if (other_encoder == encoder) 2060 continue; 2061 2062 if (drm_WARN_ON(&i915->drm, 2063 port_mask & BIT(other_encoder->port))) 2064 return; 2065 } 2066 /* 2067 * For DSI we keep the ddi clocks gated 2068 * except during enable/disable sequence. 2069 */ 2070 ddi_clk_needed = false; 2071 } 2072 2073 if (ddi_clk_needed || !encoder->is_clock_enabled || 2074 !encoder->is_clock_enabled(encoder)) 2075 return; 2076 2077 drm_notice(&i915->drm, 2078 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2079 encoder->base.base.id, encoder->base.name); 2080 2081 encoder->disable_clock(encoder); 2082} 2083 2084static void 2085icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2086 const struct intel_crtc_state *crtc_state) 2087{ 2088 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2089 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2090 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2091 u32 ln0, ln1, pin_assignment; 2092 u8 width; 2093 2094 if (!intel_phy_is_tc(dev_priv, phy) || 2095 intel_tc_port_in_tbt_alt_mode(dig_port)) 2096 return; 2097 2098 if (DISPLAY_VER(dev_priv) >= 12) { 2099 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2100 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2101 } else { 2102 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2103 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2104 } 2105 2106 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2107 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2108 2109 /* DPPATC */ 2110 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2111 width = crtc_state->lane_count; 2112 2113 switch (pin_assignment) { 2114 case 0x0: 2115 drm_WARN_ON(&dev_priv->drm, 2116 !intel_tc_port_in_legacy_mode(dig_port)); 2117 if (width == 1) { 2118 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2119 } else { 2120 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2121 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2122 } 2123 break; 2124 case 0x1: 2125 if (width == 4) { 2126 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2127 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2128 } 2129 break; 2130 case 0x2: 2131 if (width == 2) { 2132 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2133 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2134 } 2135 break; 2136 case 0x3: 2137 case 0x5: 2138 if (width == 1) { 2139 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2140 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2141 } else { 2142 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2143 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2144 } 2145 break; 2146 case 0x4: 2147 case 0x6: 2148 if (width == 1) { 2149 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2150 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2151 } else { 2152 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2153 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2154 } 2155 break; 2156 default: 2157 MISSING_CASE(pin_assignment); 2158 } 2159 2160 if (DISPLAY_VER(dev_priv) >= 12) { 2161 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2162 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2163 } else { 2164 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2165 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2166 } 2167} 2168 2169static enum transcoder 2170tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2171{ 2172 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2173 return crtc_state->mst_master_transcoder; 2174 else 2175 return crtc_state->cpu_transcoder; 2176} 2177 2178i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2179 const struct intel_crtc_state *crtc_state) 2180{ 2181 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2182 2183 if (DISPLAY_VER(dev_priv) >= 12) 2184 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2185 else 2186 return DP_TP_CTL(encoder->port); 2187} 2188 2189i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2190 const struct intel_crtc_state *crtc_state) 2191{ 2192 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2193 2194 if (DISPLAY_VER(dev_priv) >= 12) 2195 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2196 else 2197 return DP_TP_STATUS(encoder->port); 2198} 2199 2200static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2201 const struct intel_crtc_state *crtc_state, 2202 bool enable) 2203{ 2204 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2205 2206 if (!crtc_state->vrr.enable) 2207 return; 2208 2209 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2210 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2211 drm_dbg_kms(&i915->drm, 2212 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2213 str_enable_disable(enable)); 2214} 2215 2216static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2217 const struct intel_crtc_state *crtc_state, 2218 bool enable) 2219{ 2220 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2221 2222 if (!crtc_state->fec_enable) 2223 return; 2224 2225 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2226 enable ? DP_FEC_READY : 0) <= 0) 2227 drm_dbg_kms(&i915->drm, "Failed to set FEC_READY to %s in the sink\n", 2228 enable ? "enabled" : "disabled"); 2229 2230 if (enable && 2231 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2232 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2233 drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n"); 2234} 2235 2236static int read_fec_detected_status(struct drm_dp_aux *aux) 2237{ 2238 int ret; 2239 u8 status; 2240 2241 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2242 if (ret < 0) 2243 return ret; 2244 2245 return status; 2246} 2247 2248static void wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2249{ 2250 struct drm_i915_private *i915 = to_i915(aux->drm_dev); 2251 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2252 int status; 2253 int err; 2254 2255 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2256 status & mask || status < 0, 2257 10000, 200000); 2258 2259 if (!err && status >= 0) 2260 return; 2261 2262 if (err == -ETIMEDOUT) 2263 drm_dbg_kms(&i915->drm, "Timeout waiting for FEC %s to get detected\n", 2264 str_enabled_disabled(enabled)); 2265 else 2266 drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status); 2267} 2268 2269void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2270 const struct intel_crtc_state *crtc_state, 2271 bool enabled) 2272{ 2273 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2274 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2275 int ret; 2276 2277 if (!crtc_state->fec_enable) 2278 return; 2279 2280 if (enabled) 2281 ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 2282 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2283 else 2284 ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder, crtc_state), 2285 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2286 2287 if (ret) 2288 drm_err(&i915->drm, 2289 "Timeout waiting for FEC live state to get %s\n", 2290 str_enabled_disabled(enabled)); 2291 2292 /* 2293 * At least the Synoptics MST hub doesn't set the detected flag for 2294 * FEC decoding disabling so skip waiting for that. 2295 */ 2296 if (enabled) 2297 wait_for_fec_detected(&intel_dp->aux, enabled); 2298} 2299 2300static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2301 const struct intel_crtc_state *crtc_state) 2302{ 2303 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2304 2305 if (!crtc_state->fec_enable) 2306 return; 2307 2308 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2309 0, DP_TP_CTL_FEC_ENABLE); 2310} 2311 2312static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2313 const struct intel_crtc_state *crtc_state) 2314{ 2315 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2316 2317 if (!crtc_state->fec_enable) 2318 return; 2319 2320 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2321 DP_TP_CTL_FEC_ENABLE, 0); 2322 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2323} 2324 2325static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2326 const struct intel_crtc_state *crtc_state) 2327{ 2328 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2329 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2330 enum phy phy = intel_port_to_phy(i915, encoder->port); 2331 2332 if (intel_phy_is_combo(i915, phy)) { 2333 bool lane_reversal = 2334 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2335 2336 intel_combo_phy_power_up_lanes(i915, phy, false, 2337 crtc_state->lane_count, 2338 lane_reversal); 2339 } 2340} 2341 2342/* Splitter enable for eDP MSO is limited to certain pipes. */ 2343static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2344{ 2345 if (IS_ALDERLAKE_P(i915)) 2346 return BIT(PIPE_A) | BIT(PIPE_B); 2347 else 2348 return BIT(PIPE_A); 2349} 2350 2351static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2352 struct intel_crtc_state *pipe_config) 2353{ 2354 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2355 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2356 enum pipe pipe = crtc->pipe; 2357 u32 dss1; 2358 2359 if (!HAS_MSO(i915)) 2360 return; 2361 2362 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2363 2364 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2365 if (!pipe_config->splitter.enable) 2366 return; 2367 2368 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2369 pipe_config->splitter.enable = false; 2370 return; 2371 } 2372 2373 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2374 default: 2375 drm_WARN(&i915->drm, true, 2376 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2377 fallthrough; 2378 case SPLITTER_CONFIGURATION_2_SEGMENT: 2379 pipe_config->splitter.link_count = 2; 2380 break; 2381 case SPLITTER_CONFIGURATION_4_SEGMENT: 2382 pipe_config->splitter.link_count = 4; 2383 break; 2384 } 2385 2386 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2387} 2388 2389static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2390{ 2391 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2392 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2393 enum pipe pipe = crtc->pipe; 2394 u32 dss1 = 0; 2395 2396 if (!HAS_MSO(i915)) 2397 return; 2398 2399 if (crtc_state->splitter.enable) { 2400 dss1 |= SPLITTER_ENABLE; 2401 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2402 if (crtc_state->splitter.link_count == 2) 2403 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2404 else 2405 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2406 } 2407 2408 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2409 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2410 OVERLAP_PIXELS_MASK, dss1); 2411} 2412 2413static u8 mtl_get_port_width(u8 lane_count) 2414{ 2415 switch (lane_count) { 2416 case 1: 2417 return 0; 2418 case 2: 2419 return 1; 2420 case 3: 2421 return 4; 2422 case 4: 2423 return 3; 2424 default: 2425 MISSING_CASE(lane_count); 2426 return 4; 2427 } 2428} 2429 2430static void 2431mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2432{ 2433 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2434 enum port port = encoder->port; 2435 i915_reg_t reg; 2436 u32 set_bits, wait_bits; 2437 2438 if (DISPLAY_VER(dev_priv) >= 20) { 2439 reg = DDI_BUF_CTL(port); 2440 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2441 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2442 } else { 2443 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2444 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2445 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2446 } 2447 2448 intel_de_rmw(dev_priv, reg, 0, set_bits); 2449 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2450 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2451 port_name(port)); 2452 } 2453} 2454 2455static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2456 const struct intel_crtc_state *crtc_state) 2457{ 2458 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2459 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2460 enum port port = encoder->port; 2461 u32 val; 2462 2463 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)); 2464 val &= ~XELPDP_PORT_WIDTH_MASK; 2465 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2466 2467 val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK; 2468 if (intel_dp_is_uhbr(crtc_state)) 2469 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2470 else 2471 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2472 2473 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 2474 val |= XELPDP_PORT_REVERSAL; 2475 2476 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val); 2477} 2478 2479static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2480{ 2481 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2482 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2483 u32 val; 2484 2485 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2486 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2487 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2488 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2489} 2490 2491static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2492 struct intel_encoder *encoder, 2493 const struct intel_crtc_state *crtc_state, 2494 const struct drm_connector_state *conn_state) 2495{ 2496 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2497 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2498 2499 intel_dp_set_link_params(intel_dp, 2500 crtc_state->port_clock, 2501 crtc_state->lane_count); 2502 2503 /* 2504 * We only configure what the register value will be here. Actual 2505 * enabling happens during link training farther down. 2506 */ 2507 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2508 2509 /* 2510 * 1. Enable Power Wells 2511 * 2512 * This was handled at the beginning of intel_atomic_commit_tail(), 2513 * before we called down into this function. 2514 */ 2515 2516 /* 2. PMdemand was already set */ 2517 2518 /* 3. Select Thunderbolt */ 2519 mtl_port_buf_ctl_io_selection(encoder); 2520 2521 /* 4. Enable Panel Power if PPS is required */ 2522 intel_pps_on(intel_dp); 2523 2524 /* 5. Enable the port PLL */ 2525 intel_ddi_enable_clock(encoder, crtc_state); 2526 2527 /* 2528 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2529 * Transcoder. 2530 */ 2531 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2532 2533 /* 2534 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2535 */ 2536 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2537 2538 /* 2539 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2540 * Transport Select 2541 */ 2542 intel_ddi_config_transcoder_func(encoder, crtc_state); 2543 2544 /* 2545 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2546 */ 2547 intel_ddi_mso_configure(crtc_state); 2548 2549 if (!is_mst) 2550 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2551 2552 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2553 if (!is_mst) 2554 intel_dp_sink_enable_decompression(state, 2555 to_intel_connector(conn_state->connector), 2556 crtc_state); 2557 2558 /* 2559 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2560 * in the FEC_CONFIGURATION register to 1 before initiating link 2561 * training 2562 */ 2563 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2564 2565 intel_dp_check_frl_training(intel_dp); 2566 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2567 2568 /* 2569 * 6. The rest of the below are substeps under the bspec's "Enable and 2570 * Train Display Port" step. Note that steps that are specific to 2571 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2572 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2573 * us when active_mst_links==0, so any steps designated for "single 2574 * stream or multi-stream master transcoder" can just be performed 2575 * unconditionally here. 2576 * 2577 * mtl_ddi_prepare_link_retrain() that is called by 2578 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2579 * 6.i and 6.j 2580 * 2581 * 6.k Follow DisplayPort specification training sequence (see notes for 2582 * failure handling) 2583 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2584 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2585 * (timeout after 800 us) 2586 */ 2587 intel_dp_start_link_train(intel_dp, crtc_state); 2588 2589 /* 6.n Set DP_TP_CTL link training to Normal */ 2590 if (!is_trans_port_sync_mode(crtc_state)) 2591 intel_dp_stop_link_train(intel_dp, crtc_state); 2592 2593 /* 6.o Configure and enable FEC if needed */ 2594 intel_ddi_enable_fec(encoder, crtc_state); 2595 2596 if (!is_mst) 2597 intel_dsc_dp_pps_write(encoder, crtc_state); 2598} 2599 2600static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2601 struct intel_encoder *encoder, 2602 const struct intel_crtc_state *crtc_state, 2603 const struct drm_connector_state *conn_state) 2604{ 2605 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2606 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2607 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2608 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2609 2610 intel_dp_set_link_params(intel_dp, 2611 crtc_state->port_clock, 2612 crtc_state->lane_count); 2613 2614 /* 2615 * We only configure what the register value will be here. Actual 2616 * enabling happens during link training farther down. 2617 */ 2618 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2619 2620 /* 2621 * 1. Enable Power Wells 2622 * 2623 * This was handled at the beginning of intel_atomic_commit_tail(), 2624 * before we called down into this function. 2625 */ 2626 2627 /* 2. Enable Panel Power if PPS is required */ 2628 intel_pps_on(intel_dp); 2629 2630 /* 2631 * 3. For non-TBT Type-C ports, set FIA lane count 2632 * (DFLEXDPSP.DPX4TXLATC) 2633 * 2634 * This was done before tgl_ddi_pre_enable_dp by 2635 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2636 */ 2637 2638 /* 2639 * 4. Enable the port PLL. 2640 * 2641 * The PLL enabling itself was already done before this function by 2642 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2643 * configure the PLL to port mapping here. 2644 */ 2645 intel_ddi_enable_clock(encoder, crtc_state); 2646 2647 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2648 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2649 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2650 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2651 dig_port->ddi_io_power_domain); 2652 } 2653 2654 /* 6. Program DP_MODE */ 2655 icl_program_mg_dp_mode(dig_port, crtc_state); 2656 2657 /* 2658 * 7. The rest of the below are substeps under the bspec's "Enable and 2659 * Train Display Port" step. Note that steps that are specific to 2660 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2661 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2662 * us when active_mst_links==0, so any steps designated for "single 2663 * stream or multi-stream master transcoder" can just be performed 2664 * unconditionally here. 2665 */ 2666 2667 /* 2668 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2669 * Transcoder. 2670 */ 2671 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2672 2673 if (HAS_DP20(dev_priv)) 2674 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2675 2676 /* 2677 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2678 * Transport Select 2679 */ 2680 intel_ddi_config_transcoder_func(encoder, crtc_state); 2681 2682 /* 2683 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2684 * selected 2685 * 2686 * This will be handled by the intel_dp_start_link_train() farther 2687 * down this function. 2688 */ 2689 2690 /* 7.e Configure voltage swing and related IO settings */ 2691 encoder->set_signal_levels(encoder, crtc_state); 2692 2693 /* 2694 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2695 * the used lanes of the DDI. 2696 */ 2697 intel_ddi_power_up_lanes(encoder, crtc_state); 2698 2699 /* 2700 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2701 */ 2702 intel_ddi_mso_configure(crtc_state); 2703 2704 if (!is_mst) 2705 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2706 2707 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2708 if (!is_mst) 2709 intel_dp_sink_enable_decompression(state, 2710 to_intel_connector(conn_state->connector), 2711 crtc_state); 2712 /* 2713 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2714 * in the FEC_CONFIGURATION register to 1 before initiating link 2715 * training 2716 */ 2717 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2718 2719 intel_dp_check_frl_training(intel_dp); 2720 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2721 2722 /* 2723 * 7.i Follow DisplayPort specification training sequence (see notes for 2724 * failure handling) 2725 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2726 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2727 * (timeout after 800 us) 2728 */ 2729 intel_dp_start_link_train(intel_dp, crtc_state); 2730 2731 /* 7.k Set DP_TP_CTL link training to Normal */ 2732 if (!is_trans_port_sync_mode(crtc_state)) 2733 intel_dp_stop_link_train(intel_dp, crtc_state); 2734 2735 /* 7.l Configure and enable FEC if needed */ 2736 intel_ddi_enable_fec(encoder, crtc_state); 2737 2738 if (!is_mst) 2739 intel_dsc_dp_pps_write(encoder, crtc_state); 2740} 2741 2742static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2743 struct intel_encoder *encoder, 2744 const struct intel_crtc_state *crtc_state, 2745 const struct drm_connector_state *conn_state) 2746{ 2747 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2749 enum port port = encoder->port; 2750 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2751 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2752 2753 if (DISPLAY_VER(dev_priv) < 11) 2754 drm_WARN_ON(&dev_priv->drm, 2755 is_mst && (port == PORT_A || port == PORT_E)); 2756 else 2757 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2758 2759 intel_dp_set_link_params(intel_dp, 2760 crtc_state->port_clock, 2761 crtc_state->lane_count); 2762 2763 /* 2764 * We only configure what the register value will be here. Actual 2765 * enabling happens during link training farther down. 2766 */ 2767 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2768 2769 intel_pps_on(intel_dp); 2770 2771 intel_ddi_enable_clock(encoder, crtc_state); 2772 2773 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2774 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2775 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2776 dig_port->ddi_io_power_domain); 2777 } 2778 2779 icl_program_mg_dp_mode(dig_port, crtc_state); 2780 2781 if (has_buf_trans_select(dev_priv)) 2782 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2783 2784 encoder->set_signal_levels(encoder, crtc_state); 2785 2786 intel_ddi_power_up_lanes(encoder, crtc_state); 2787 2788 if (!is_mst) 2789 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2790 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2791 if (!is_mst) 2792 intel_dp_sink_enable_decompression(state, 2793 to_intel_connector(conn_state->connector), 2794 crtc_state); 2795 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2796 intel_dp_start_link_train(intel_dp, crtc_state); 2797 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2798 !is_trans_port_sync_mode(crtc_state)) 2799 intel_dp_stop_link_train(intel_dp, crtc_state); 2800 2801 intel_ddi_enable_fec(encoder, crtc_state); 2802 2803 if (!is_mst) { 2804 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2805 intel_dsc_dp_pps_write(encoder, crtc_state); 2806 } 2807} 2808 2809static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2810 struct intel_encoder *encoder, 2811 const struct intel_crtc_state *crtc_state, 2812 const struct drm_connector_state *conn_state) 2813{ 2814 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2815 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2816 2817 if (HAS_DP20(dev_priv)) { 2818 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2819 crtc_state); 2820 if (crtc_state->has_panel_replay) 2821 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, 2822 DP_PANEL_REPLAY_ENABLE); 2823 } 2824 2825 if (DISPLAY_VER(dev_priv) >= 14) 2826 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2827 else if (DISPLAY_VER(dev_priv) >= 12) 2828 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2829 else 2830 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2831 2832 /* MST will call a setting of MSA after an allocating of Virtual Channel 2833 * from MST encoder pre_enable callback. 2834 */ 2835 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2836 intel_ddi_set_dp_msa(crtc_state, conn_state); 2837} 2838 2839static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2840 struct intel_encoder *encoder, 2841 const struct intel_crtc_state *crtc_state, 2842 const struct drm_connector_state *conn_state) 2843{ 2844 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2845 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2846 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2847 2848 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2849 intel_ddi_enable_clock(encoder, crtc_state); 2850 2851 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2852 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2853 dig_port->ddi_io_power_domain); 2854 2855 icl_program_mg_dp_mode(dig_port, crtc_state); 2856 2857 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2858 2859 dig_port->set_infoframes(encoder, 2860 crtc_state->has_infoframe, 2861 crtc_state, conn_state); 2862} 2863 2864static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2865 struct intel_encoder *encoder, 2866 const struct intel_crtc_state *crtc_state, 2867 const struct drm_connector_state *conn_state) 2868{ 2869 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2870 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2871 enum pipe pipe = crtc->pipe; 2872 2873 /* 2874 * When called from DP MST code: 2875 * - conn_state will be NULL 2876 * - encoder will be the main encoder (ie. mst->primary) 2877 * - the main connector associated with this port 2878 * won't be active or linked to a crtc 2879 * - crtc_state will be the state of the first stream to 2880 * be activated on this port, and it may not be the same 2881 * stream that will be deactivated last, but each stream 2882 * should have a state that is identical when it comes to 2883 * the DP link parameteres 2884 */ 2885 2886 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2887 2888 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2889 2890 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2891 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2892 conn_state); 2893 } else { 2894 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2895 2896 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2897 conn_state); 2898 2899 /* FIXME precompute everything properly */ 2900 /* FIXME how do we turn infoframes off again? */ 2901 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 2902 dig_port->set_infoframes(encoder, 2903 crtc_state->has_infoframe, 2904 crtc_state, conn_state); 2905 } 2906} 2907 2908static void 2909mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 2910{ 2911 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2912 enum port port = encoder->port; 2913 i915_reg_t reg; 2914 u32 clr_bits, wait_bits; 2915 2916 if (DISPLAY_VER(dev_priv) >= 20) { 2917 reg = DDI_BUF_CTL(port); 2918 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2919 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2920 } else { 2921 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2922 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2923 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2924 } 2925 2926 intel_de_rmw(dev_priv, reg, clr_bits, 0); 2927 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 2928 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 2929 port_name(port)); 2930} 2931 2932static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 2933 const struct intel_crtc_state *crtc_state) 2934{ 2935 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2936 enum port port = encoder->port; 2937 u32 val; 2938 2939 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 2940 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2941 if (val & DDI_BUF_CTL_ENABLE) { 2942 val &= ~DDI_BUF_CTL_ENABLE; 2943 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2944 2945 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 2946 mtl_wait_ddi_buf_idle(dev_priv, port); 2947 } 2948 2949 /* 3.d Disable D2D Link */ 2950 mtl_ddi_disable_d2d_link(encoder); 2951 2952 /* 3.e Disable DP_TP_CTL */ 2953 if (intel_crtc_has_dp_encoder(crtc_state)) { 2954 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2955 DP_TP_CTL_ENABLE, 0); 2956 } 2957} 2958 2959static void disable_ddi_buf(struct intel_encoder *encoder, 2960 const struct intel_crtc_state *crtc_state) 2961{ 2962 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2963 enum port port = encoder->port; 2964 bool wait = false; 2965 u32 val; 2966 2967 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2968 if (val & DDI_BUF_CTL_ENABLE) { 2969 val &= ~DDI_BUF_CTL_ENABLE; 2970 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2971 wait = true; 2972 } 2973 2974 if (intel_crtc_has_dp_encoder(crtc_state)) 2975 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2976 DP_TP_CTL_ENABLE, 0); 2977 2978 intel_ddi_disable_fec(encoder, crtc_state); 2979 2980 if (wait) 2981 intel_wait_ddi_buf_idle(dev_priv, port); 2982} 2983 2984static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2985 const struct intel_crtc_state *crtc_state) 2986{ 2987 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2988 2989 if (DISPLAY_VER(dev_priv) >= 14) { 2990 mtl_disable_ddi_buf(encoder, crtc_state); 2991 2992 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 2993 intel_ddi_disable_fec(encoder, crtc_state); 2994 } else { 2995 disable_ddi_buf(encoder, crtc_state); 2996 } 2997 2998 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2999} 3000 3001static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3002 struct intel_encoder *encoder, 3003 const struct intel_crtc_state *old_crtc_state, 3004 const struct drm_connector_state *old_conn_state) 3005{ 3006 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3007 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3008 struct intel_dp *intel_dp = &dig_port->dp; 3009 intel_wakeref_t wakeref; 3010 bool is_mst = intel_crtc_has_type(old_crtc_state, 3011 INTEL_OUTPUT_DP_MST); 3012 3013 if (!is_mst) 3014 intel_dp_set_infoframes(encoder, false, 3015 old_crtc_state, old_conn_state); 3016 3017 /* 3018 * Power down sink before disabling the port, otherwise we end 3019 * up getting interrupts from the sink on detecting link loss. 3020 */ 3021 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3022 3023 if (DISPLAY_VER(dev_priv) >= 12) { 3024 if (is_mst) { 3025 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3026 3027 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 3028 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3029 0); 3030 } 3031 } else { 3032 if (!is_mst) 3033 intel_ddi_disable_transcoder_clock(old_crtc_state); 3034 } 3035 3036 intel_disable_ddi_buf(encoder, old_crtc_state); 3037 3038 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3039 3040 /* 3041 * From TGL spec: "If single stream or multi-stream master transcoder: 3042 * Configure Transcoder Clock select to direct no clock to the 3043 * transcoder" 3044 */ 3045 if (DISPLAY_VER(dev_priv) >= 12) 3046 intel_ddi_disable_transcoder_clock(old_crtc_state); 3047 3048 intel_pps_vdd_on(intel_dp); 3049 intel_pps_off(intel_dp); 3050 3051 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3052 3053 if (wakeref) 3054 intel_display_power_put(dev_priv, 3055 dig_port->ddi_io_power_domain, 3056 wakeref); 3057 3058 intel_ddi_disable_clock(encoder); 3059 3060 /* De-select Thunderbolt */ 3061 if (DISPLAY_VER(dev_priv) >= 14) 3062 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3063 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3064} 3065 3066static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3067 struct intel_encoder *encoder, 3068 const struct intel_crtc_state *old_crtc_state, 3069 const struct drm_connector_state *old_conn_state) 3070{ 3071 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3072 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3073 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3074 intel_wakeref_t wakeref; 3075 3076 dig_port->set_infoframes(encoder, false, 3077 old_crtc_state, old_conn_state); 3078 3079 if (DISPLAY_VER(dev_priv) < 12) 3080 intel_ddi_disable_transcoder_clock(old_crtc_state); 3081 3082 intel_disable_ddi_buf(encoder, old_crtc_state); 3083 3084 if (DISPLAY_VER(dev_priv) >= 12) 3085 intel_ddi_disable_transcoder_clock(old_crtc_state); 3086 3087 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3088 if (wakeref) 3089 intel_display_power_put(dev_priv, 3090 dig_port->ddi_io_power_domain, 3091 wakeref); 3092 3093 intel_ddi_disable_clock(encoder); 3094 3095 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3096} 3097 3098static void intel_ddi_post_disable(struct intel_atomic_state *state, 3099 struct intel_encoder *encoder, 3100 const struct intel_crtc_state *old_crtc_state, 3101 const struct drm_connector_state *old_conn_state) 3102{ 3103 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3104 struct intel_crtc *slave_crtc; 3105 3106 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 3107 intel_crtc_vblank_off(old_crtc_state); 3108 3109 intel_disable_transcoder(old_crtc_state); 3110 3111 intel_ddi_disable_transcoder_func(old_crtc_state); 3112 3113 intel_dsc_disable(old_crtc_state); 3114 3115 if (DISPLAY_VER(dev_priv) >= 9) 3116 skl_scaler_disable(old_crtc_state); 3117 else 3118 ilk_pfit_disable(old_crtc_state); 3119 } 3120 3121 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 3122 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) { 3123 const struct intel_crtc_state *old_slave_crtc_state = 3124 intel_atomic_get_old_crtc_state(state, slave_crtc); 3125 3126 intel_crtc_vblank_off(old_slave_crtc_state); 3127 3128 intel_dsc_disable(old_slave_crtc_state); 3129 skl_scaler_disable(old_slave_crtc_state); 3130 } 3131 3132 /* 3133 * When called from DP MST code: 3134 * - old_conn_state will be NULL 3135 * - encoder will be the main encoder (ie. mst->primary) 3136 * - the main connector associated with this port 3137 * won't be active or linked to a crtc 3138 * - old_crtc_state will be the state of the last stream to 3139 * be deactivated on this port, and it may not be the same 3140 * stream that was activated last, but each stream 3141 * should have a state that is identical when it comes to 3142 * the DP link parameteres 3143 */ 3144 3145 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3146 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3147 old_conn_state); 3148 else 3149 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3150 old_conn_state); 3151} 3152 3153static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3154 struct intel_encoder *encoder, 3155 const struct intel_crtc_state *old_crtc_state, 3156 const struct drm_connector_state *old_conn_state) 3157{ 3158 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3159 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3160 enum phy phy = intel_port_to_phy(i915, encoder->port); 3161 bool is_tc_port = intel_phy_is_tc(i915, phy); 3162 3163 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3164 3165 if (is_tc_port) 3166 intel_tc_port_put_link(dig_port); 3167} 3168 3169static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3170 struct intel_encoder *encoder, 3171 const struct intel_crtc_state *crtc_state) 3172{ 3173 const struct drm_connector_state *conn_state; 3174 struct drm_connector *conn; 3175 int i; 3176 3177 if (!crtc_state->sync_mode_slaves_mask) 3178 return; 3179 3180 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3181 struct intel_encoder *slave_encoder = 3182 to_intel_encoder(conn_state->best_encoder); 3183 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3184 const struct intel_crtc_state *slave_crtc_state; 3185 3186 if (!slave_crtc) 3187 continue; 3188 3189 slave_crtc_state = 3190 intel_atomic_get_new_crtc_state(state, slave_crtc); 3191 3192 if (slave_crtc_state->master_transcoder != 3193 crtc_state->cpu_transcoder) 3194 continue; 3195 3196 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3197 slave_crtc_state); 3198 } 3199 3200 usleep_range(200, 400); 3201 3202 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3203 crtc_state); 3204} 3205 3206static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3207 struct intel_encoder *encoder, 3208 const struct intel_crtc_state *crtc_state, 3209 const struct drm_connector_state *conn_state) 3210{ 3211 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3212 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3213 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3214 enum port port = encoder->port; 3215 3216 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3217 intel_dp_stop_link_train(intel_dp, crtc_state); 3218 3219 drm_connector_update_privacy_screen(conn_state); 3220 intel_edp_backlight_on(crtc_state, conn_state); 3221 3222 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3223 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3224 3225 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3226} 3227 3228/* FIXME bad home for this function */ 3229i915_reg_t hsw_chicken_trans_reg(struct drm_i915_private *i915, 3230 enum transcoder cpu_transcoder) 3231{ 3232 return DISPLAY_VER(i915) >= 14 ? 3233 MTL_CHICKEN_TRANS(cpu_transcoder) : 3234 CHICKEN_TRANS(cpu_transcoder); 3235} 3236 3237static i915_reg_t 3238gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3239 enum port port) 3240{ 3241 static const enum transcoder trans[] = { 3242 [PORT_A] = TRANSCODER_EDP, 3243 [PORT_B] = TRANSCODER_A, 3244 [PORT_C] = TRANSCODER_B, 3245 [PORT_D] = TRANSCODER_C, 3246 [PORT_E] = TRANSCODER_A, 3247 }; 3248 3249 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3250 3251 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3252 port = PORT_A; 3253 3254 return CHICKEN_TRANS(trans[port]); 3255} 3256 3257static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3258 struct intel_encoder *encoder, 3259 const struct intel_crtc_state *crtc_state, 3260 const struct drm_connector_state *conn_state) 3261{ 3262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3263 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3264 struct drm_connector *connector = conn_state->connector; 3265 enum port port = encoder->port; 3266 enum phy phy = intel_port_to_phy(dev_priv, port); 3267 u32 buf_ctl; 3268 3269 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3270 crtc_state->hdmi_high_tmds_clock_ratio, 3271 crtc_state->hdmi_scrambling)) 3272 drm_dbg_kms(&dev_priv->drm, 3273 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3274 connector->base.id, connector->name); 3275 3276 if (has_buf_trans_select(dev_priv)) 3277 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3278 3279 /* e. Enable D2D Link for C10/C20 Phy */ 3280 if (DISPLAY_VER(dev_priv) >= 14) 3281 mtl_ddi_enable_d2d(encoder); 3282 3283 encoder->set_signal_levels(encoder, crtc_state); 3284 3285 /* Display WA #1143: skl,kbl,cfl */ 3286 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3287 /* 3288 * For some reason these chicken bits have been 3289 * stuffed into a transcoder register, event though 3290 * the bits affect a specific DDI port rather than 3291 * a specific transcoder. 3292 */ 3293 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3294 u32 val; 3295 3296 val = intel_de_read(dev_priv, reg); 3297 3298 if (port == PORT_E) 3299 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3300 DDIE_TRAINING_OVERRIDE_VALUE; 3301 else 3302 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3303 DDI_TRAINING_OVERRIDE_VALUE; 3304 3305 intel_de_write(dev_priv, reg, val); 3306 intel_de_posting_read(dev_priv, reg); 3307 3308 udelay(1); 3309 3310 if (port == PORT_E) 3311 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3312 DDIE_TRAINING_OVERRIDE_VALUE); 3313 else 3314 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3315 DDI_TRAINING_OVERRIDE_VALUE); 3316 3317 intel_de_write(dev_priv, reg, val); 3318 } 3319 3320 intel_ddi_power_up_lanes(encoder, crtc_state); 3321 3322 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3323 * are ignored so nothing special needs to be done besides 3324 * enabling the port. 3325 * 3326 * On ADL_P the PHY link rate and lane count must be programmed but 3327 * these are both 0 for HDMI. 3328 * 3329 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3330 * is filled with lane count, already set in the crtc_state. 3331 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3332 */ 3333 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 3334 if (DISPLAY_VER(dev_priv) >= 14) { 3335 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3336 u32 port_buf = 0; 3337 3338 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3339 3340 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 3341 port_buf |= XELPDP_PORT_REVERSAL; 3342 3343 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3344 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3345 3346 buf_ctl |= DDI_PORT_WIDTH(lane_count); 3347 3348 if (DISPLAY_VER(dev_priv) >= 20) 3349 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3350 } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) { 3351 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3352 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3353 } 3354 3355 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3356 3357 intel_wait_ddi_buf_active(dev_priv, port); 3358} 3359 3360static void intel_enable_ddi(struct intel_atomic_state *state, 3361 struct intel_encoder *encoder, 3362 const struct intel_crtc_state *crtc_state, 3363 const struct drm_connector_state *conn_state) 3364{ 3365 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3366 3367 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 3368 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3369 3370 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3371 intel_audio_sdp_split_update(crtc_state); 3372 3373 intel_enable_transcoder(crtc_state); 3374 3375 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3376 3377 intel_crtc_vblank_on(crtc_state); 3378 3379 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3380 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3381 else 3382 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3383 3384 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3385 3386} 3387 3388static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3389 struct intel_encoder *encoder, 3390 const struct intel_crtc_state *old_crtc_state, 3391 const struct drm_connector_state *old_conn_state) 3392{ 3393 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3394 struct intel_connector *connector = 3395 to_intel_connector(old_conn_state->connector); 3396 3397 intel_dp->link_trained = false; 3398 3399 intel_psr_disable(intel_dp, old_crtc_state); 3400 intel_edp_backlight_off(old_conn_state); 3401 /* Disable the decompression in DP Sink */ 3402 intel_dp_sink_disable_decompression(state, 3403 connector, old_crtc_state); 3404 /* Disable Ignore_MSA bit in DP Sink */ 3405 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3406 false); 3407} 3408 3409static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3410 struct intel_encoder *encoder, 3411 const struct intel_crtc_state *old_crtc_state, 3412 const struct drm_connector_state *old_conn_state) 3413{ 3414 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3415 struct drm_connector *connector = old_conn_state->connector; 3416 3417 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3418 false, false)) 3419 drm_dbg_kms(&i915->drm, 3420 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3421 connector->base.id, connector->name); 3422} 3423 3424static void intel_disable_ddi(struct intel_atomic_state *state, 3425 struct intel_encoder *encoder, 3426 const struct intel_crtc_state *old_crtc_state, 3427 const struct drm_connector_state *old_conn_state) 3428{ 3429 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3430 3431 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3432 3433 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3434 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3435 old_conn_state); 3436 else 3437 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3438 old_conn_state); 3439} 3440 3441static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3442 struct intel_encoder *encoder, 3443 const struct intel_crtc_state *crtc_state, 3444 const struct drm_connector_state *conn_state) 3445{ 3446 intel_ddi_set_dp_msa(crtc_state, conn_state); 3447 3448 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3449 3450 intel_backlight_update(state, encoder, crtc_state, conn_state); 3451 drm_connector_update_privacy_screen(conn_state); 3452} 3453 3454void intel_ddi_update_pipe(struct intel_atomic_state *state, 3455 struct intel_encoder *encoder, 3456 const struct intel_crtc_state *crtc_state, 3457 const struct drm_connector_state *conn_state) 3458{ 3459 3460 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3461 !intel_encoder_is_mst(encoder)) 3462 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3463 conn_state); 3464 3465 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3466} 3467 3468void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3469 struct intel_encoder *encoder, 3470 struct intel_crtc *crtc) 3471{ 3472 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3473 struct intel_crtc_state *crtc_state = 3474 intel_atomic_get_new_crtc_state(state, crtc); 3475 struct intel_crtc *slave_crtc; 3476 enum phy phy = intel_port_to_phy(i915, encoder->port); 3477 3478 /* FIXME: Add MTL pll_mgr */ 3479 if (DISPLAY_VER(i915) >= 14 || !intel_phy_is_tc(i915, phy)) 3480 return; 3481 3482 intel_update_active_dpll(state, crtc, encoder); 3483 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 3484 intel_crtc_bigjoiner_slave_pipes(crtc_state)) 3485 intel_update_active_dpll(state, slave_crtc, encoder); 3486} 3487 3488static void 3489intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3490 struct intel_encoder *encoder, 3491 const struct intel_crtc_state *crtc_state, 3492 const struct drm_connector_state *conn_state) 3493{ 3494 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3495 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3496 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3497 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3498 3499 if (is_tc_port) { 3500 struct intel_crtc *master_crtc = 3501 to_intel_crtc(crtc_state->uapi.crtc); 3502 3503 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3504 intel_ddi_update_active_dpll(state, encoder, master_crtc); 3505 } 3506 3507 main_link_aux_power_domain_get(dig_port, crtc_state); 3508 3509 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3510 /* 3511 * Program the lane count for static/dynamic connections on 3512 * Type-C ports. Skip this step for TBT. 3513 */ 3514 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3515 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3516 bxt_ddi_phy_set_lane_optim_mask(encoder, 3517 crtc_state->lane_lat_optim_mask); 3518} 3519 3520static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3521{ 3522 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3523 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 3524 int ln; 3525 3526 for (ln = 0; ln < 2; ln++) 3527 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3528} 3529 3530static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3531 const struct intel_crtc_state *crtc_state) 3532{ 3533 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3534 struct intel_encoder *encoder = &dig_port->base; 3535 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3536 enum port port = encoder->port; 3537 u32 dp_tp_ctl; 3538 3539 /* 3540 * TODO: To train with only a different voltage swing entry is not 3541 * necessary disable and enable port 3542 */ 3543 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3544 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3545 mtl_disable_ddi_buf(encoder, crtc_state); 3546 3547 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3548 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3549 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3550 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3551 } else { 3552 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3553 if (crtc_state->enhanced_framing) 3554 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3555 } 3556 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3557 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3558 3559 /* 6.f Enable D2D Link */ 3560 mtl_ddi_enable_d2d(encoder); 3561 3562 /* 6.g Configure voltage swing and related IO settings */ 3563 encoder->set_signal_levels(encoder, crtc_state); 3564 3565 /* 6.h Configure PORT_BUF_CTL1 */ 3566 mtl_port_buf_ctl_program(encoder, crtc_state); 3567 3568 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3569 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3570 if (DISPLAY_VER(dev_priv) >= 20) 3571 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3572 3573 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3574 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3575 3576 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3577 intel_wait_ddi_buf_active(dev_priv, port); 3578} 3579 3580static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3581 const struct intel_crtc_state *crtc_state) 3582{ 3583 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3584 struct intel_encoder *encoder = &dig_port->base; 3585 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3586 enum port port = encoder->port; 3587 u32 dp_tp_ctl, ddi_buf_ctl; 3588 bool wait = false; 3589 3590 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3591 3592 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3593 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3594 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3595 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3596 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3597 wait = true; 3598 } 3599 3600 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3601 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3602 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3603 3604 if (wait) 3605 intel_wait_ddi_buf_idle(dev_priv, port); 3606 } 3607 3608 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3609 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3610 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3611 } else { 3612 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3613 if (crtc_state->enhanced_framing) 3614 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3615 } 3616 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3617 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3618 3619 if (IS_ALDERLAKE_P(dev_priv) && 3620 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3621 adlp_tbt_to_dp_alt_switch_wa(encoder); 3622 3623 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3624 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3625 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3626 3627 intel_wait_ddi_buf_active(dev_priv, port); 3628} 3629 3630static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3631 const struct intel_crtc_state *crtc_state, 3632 u8 dp_train_pat) 3633{ 3634 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3635 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3636 u32 temp; 3637 3638 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3639 3640 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3641 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3642 case DP_TRAINING_PATTERN_DISABLE: 3643 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3644 break; 3645 case DP_TRAINING_PATTERN_1: 3646 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3647 break; 3648 case DP_TRAINING_PATTERN_2: 3649 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3650 break; 3651 case DP_TRAINING_PATTERN_3: 3652 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3653 break; 3654 case DP_TRAINING_PATTERN_4: 3655 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3656 break; 3657 } 3658 3659 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3660} 3661 3662static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3663 const struct intel_crtc_state *crtc_state) 3664{ 3665 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3666 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3667 enum port port = encoder->port; 3668 3669 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3670 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3671 3672 /* 3673 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3674 * reason we need to set idle transmission mode is to work around a HW 3675 * issue where we enable the pipe while not in idle link-training mode. 3676 * In this case there is requirement to wait for a minimum number of 3677 * idle patterns to be sent. 3678 */ 3679 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3680 return; 3681 3682 if (intel_de_wait_for_set(dev_priv, 3683 dp_tp_status_reg(encoder, crtc_state), 3684 DP_TP_STATUS_IDLE_DONE, 1)) 3685 drm_err(&dev_priv->drm, 3686 "Timed out waiting for DP idle patterns\n"); 3687} 3688 3689static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3690 enum transcoder cpu_transcoder) 3691{ 3692 if (cpu_transcoder == TRANSCODER_EDP) 3693 return false; 3694 3695 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3696 return false; 3697 3698 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3699 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3700} 3701 3702static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3703{ 3704 if (crtc_state->port_clock > 594000) 3705 return 2; 3706 else 3707 return 0; 3708} 3709 3710static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3711{ 3712 if (crtc_state->port_clock > 594000) 3713 return 3; 3714 else 3715 return 0; 3716} 3717 3718static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3719{ 3720 if (crtc_state->port_clock > 594000) 3721 return 1; 3722 else 3723 return 0; 3724} 3725 3726void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3727{ 3728 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3729 3730 if (DISPLAY_VER(dev_priv) >= 14) 3731 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3732 else if (DISPLAY_VER(dev_priv) >= 12) 3733 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3734 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3735 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3736 else if (DISPLAY_VER(dev_priv) >= 11) 3737 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3738} 3739 3740static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3741 enum transcoder cpu_transcoder) 3742{ 3743 u32 master_select; 3744 3745 if (DISPLAY_VER(dev_priv) >= 11) { 3746 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3747 3748 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3749 return INVALID_TRANSCODER; 3750 3751 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3752 } else { 3753 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3754 3755 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3756 return INVALID_TRANSCODER; 3757 3758 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3759 } 3760 3761 if (master_select == 0) 3762 return TRANSCODER_EDP; 3763 else 3764 return master_select - 1; 3765} 3766 3767static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3768{ 3769 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3770 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3771 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3772 enum transcoder cpu_transcoder; 3773 3774 crtc_state->master_transcoder = 3775 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3776 3777 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3778 enum intel_display_power_domain power_domain; 3779 intel_wakeref_t trans_wakeref; 3780 3781 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3782 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3783 power_domain); 3784 3785 if (!trans_wakeref) 3786 continue; 3787 3788 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3789 crtc_state->cpu_transcoder) 3790 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3791 3792 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3793 } 3794 3795 drm_WARN_ON(&dev_priv->drm, 3796 crtc_state->master_transcoder != INVALID_TRANSCODER && 3797 crtc_state->sync_mode_slaves_mask); 3798} 3799 3800static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3801 struct intel_crtc_state *pipe_config) 3802{ 3803 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3804 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3805 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3806 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3807 u32 temp, flags = 0; 3808 3809 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3810 if (temp & TRANS_DDI_PHSYNC) 3811 flags |= DRM_MODE_FLAG_PHSYNC; 3812 else 3813 flags |= DRM_MODE_FLAG_NHSYNC; 3814 if (temp & TRANS_DDI_PVSYNC) 3815 flags |= DRM_MODE_FLAG_PVSYNC; 3816 else 3817 flags |= DRM_MODE_FLAG_NVSYNC; 3818 3819 pipe_config->hw.adjusted_mode.flags |= flags; 3820 3821 switch (temp & TRANS_DDI_BPC_MASK) { 3822 case TRANS_DDI_BPC_6: 3823 pipe_config->pipe_bpp = 18; 3824 break; 3825 case TRANS_DDI_BPC_8: 3826 pipe_config->pipe_bpp = 24; 3827 break; 3828 case TRANS_DDI_BPC_10: 3829 pipe_config->pipe_bpp = 30; 3830 break; 3831 case TRANS_DDI_BPC_12: 3832 pipe_config->pipe_bpp = 36; 3833 break; 3834 default: 3835 break; 3836 } 3837 3838 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3839 case TRANS_DDI_MODE_SELECT_HDMI: 3840 pipe_config->has_hdmi_sink = true; 3841 3842 pipe_config->infoframes.enable |= 3843 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3844 3845 if (pipe_config->infoframes.enable) 3846 pipe_config->has_infoframe = true; 3847 3848 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3849 pipe_config->hdmi_scrambling = true; 3850 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3851 pipe_config->hdmi_high_tmds_clock_ratio = true; 3852 fallthrough; 3853 case TRANS_DDI_MODE_SELECT_DVI: 3854 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3855 if (DISPLAY_VER(dev_priv) >= 14) 3856 pipe_config->lane_count = 3857 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3858 else 3859 pipe_config->lane_count = 4; 3860 break; 3861 case TRANS_DDI_MODE_SELECT_DP_SST: 3862 if (encoder->type == INTEL_OUTPUT_EDP) 3863 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3864 else 3865 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3866 pipe_config->lane_count = 3867 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3868 3869 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3870 &pipe_config->dp_m_n); 3871 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3872 &pipe_config->dp_m2_n2); 3873 3874 pipe_config->enhanced_framing = 3875 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3876 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3877 3878 if (DISPLAY_VER(dev_priv) >= 11) 3879 pipe_config->fec_enable = 3880 intel_de_read(dev_priv, 3881 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3882 3883 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3884 pipe_config->infoframes.enable |= 3885 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3886 else 3887 pipe_config->infoframes.enable |= 3888 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3889 break; 3890 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3891 if (!HAS_DP20(dev_priv)) { 3892 /* FDI */ 3893 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3894 pipe_config->enhanced_framing = 3895 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3896 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3897 break; 3898 } 3899 fallthrough; /* 128b/132b */ 3900 case TRANS_DDI_MODE_SELECT_DP_MST: 3901 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3902 pipe_config->lane_count = 3903 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3904 3905 if (DISPLAY_VER(dev_priv) >= 12) 3906 pipe_config->mst_master_transcoder = 3907 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3908 3909 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3910 &pipe_config->dp_m_n); 3911 3912 if (DISPLAY_VER(dev_priv) >= 11) 3913 pipe_config->fec_enable = 3914 intel_de_read(dev_priv, 3915 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3916 3917 pipe_config->infoframes.enable |= 3918 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3919 break; 3920 default: 3921 break; 3922 } 3923} 3924 3925static void intel_ddi_get_config(struct intel_encoder *encoder, 3926 struct intel_crtc_state *pipe_config) 3927{ 3928 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3929 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3930 3931 /* XXX: DSI transcoder paranoia */ 3932 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3933 return; 3934 3935 intel_ddi_read_func_ctl(encoder, pipe_config); 3936 3937 intel_ddi_mso_get_config(encoder, pipe_config); 3938 3939 pipe_config->has_audio = 3940 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3941 3942 if (encoder->type == INTEL_OUTPUT_EDP) 3943 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3944 3945 ddi_dotclock_get(pipe_config); 3946 3947 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3948 pipe_config->lane_lat_optim_mask = 3949 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3950 3951 intel_ddi_compute_min_voltage_level(pipe_config); 3952 3953 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3954 3955 intel_read_infoframe(encoder, pipe_config, 3956 HDMI_INFOFRAME_TYPE_AVI, 3957 &pipe_config->infoframes.avi); 3958 intel_read_infoframe(encoder, pipe_config, 3959 HDMI_INFOFRAME_TYPE_SPD, 3960 &pipe_config->infoframes.spd); 3961 intel_read_infoframe(encoder, pipe_config, 3962 HDMI_INFOFRAME_TYPE_VENDOR, 3963 &pipe_config->infoframes.hdmi); 3964 intel_read_infoframe(encoder, pipe_config, 3965 HDMI_INFOFRAME_TYPE_DRM, 3966 &pipe_config->infoframes.drm); 3967 3968 if (DISPLAY_VER(dev_priv) >= 8) 3969 bdw_get_trans_port_sync_config(pipe_config); 3970 3971 intel_psr_get_config(encoder, pipe_config); 3972 3973 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3974 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3975 3976 intel_audio_codec_get_config(encoder, pipe_config); 3977} 3978 3979void intel_ddi_get_clock(struct intel_encoder *encoder, 3980 struct intel_crtc_state *crtc_state, 3981 struct intel_shared_dpll *pll) 3982{ 3983 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3984 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3985 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3986 bool pll_active; 3987 3988 if (drm_WARN_ON(&i915->drm, !pll)) 3989 return; 3990 3991 port_dpll->pll = pll; 3992 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3993 drm_WARN_ON(&i915->drm, !pll_active); 3994 3995 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3996 3997 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3998 &crtc_state->dpll_hw_state); 3999} 4000 4001static void mtl_ddi_get_config(struct intel_encoder *encoder, 4002 struct intel_crtc_state *crtc_state) 4003{ 4004 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4005 4006 if (intel_tc_port_in_tbt_alt_mode(dig_port)) { 4007 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4008 } else { 4009 intel_cx0pll_readout_hw_state(encoder, &crtc_state->cx0pll_state); 4010 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->cx0pll_state); 4011 } 4012 4013 intel_ddi_get_config(encoder, crtc_state); 4014} 4015 4016static void dg2_ddi_get_config(struct intel_encoder *encoder, 4017 struct intel_crtc_state *crtc_state) 4018{ 4019 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 4020 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 4021 4022 intel_ddi_get_config(encoder, crtc_state); 4023} 4024 4025static void adls_ddi_get_config(struct intel_encoder *encoder, 4026 struct intel_crtc_state *crtc_state) 4027{ 4028 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4029 intel_ddi_get_config(encoder, crtc_state); 4030} 4031 4032static void rkl_ddi_get_config(struct intel_encoder *encoder, 4033 struct intel_crtc_state *crtc_state) 4034{ 4035 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4036 intel_ddi_get_config(encoder, crtc_state); 4037} 4038 4039static void dg1_ddi_get_config(struct intel_encoder *encoder, 4040 struct intel_crtc_state *crtc_state) 4041{ 4042 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4043 intel_ddi_get_config(encoder, crtc_state); 4044} 4045 4046static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4047 struct intel_crtc_state *crtc_state) 4048{ 4049 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4050 intel_ddi_get_config(encoder, crtc_state); 4051} 4052 4053static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4054{ 4055 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4056} 4057 4058static enum icl_port_dpll_id 4059icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4060 const struct intel_crtc_state *crtc_state) 4061{ 4062 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4063 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4064 4065 if (drm_WARN_ON(&i915->drm, !pll)) 4066 return ICL_PORT_DPLL_DEFAULT; 4067 4068 if (icl_ddi_tc_pll_is_tbt(pll)) 4069 return ICL_PORT_DPLL_DEFAULT; 4070 else 4071 return ICL_PORT_DPLL_MG_PHY; 4072} 4073 4074enum icl_port_dpll_id 4075intel_ddi_port_pll_type(struct intel_encoder *encoder, 4076 const struct intel_crtc_state *crtc_state) 4077{ 4078 if (!encoder->port_pll_type) 4079 return ICL_PORT_DPLL_DEFAULT; 4080 4081 return encoder->port_pll_type(encoder, crtc_state); 4082} 4083 4084static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4085 struct intel_crtc_state *crtc_state, 4086 struct intel_shared_dpll *pll) 4087{ 4088 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4089 enum icl_port_dpll_id port_dpll_id; 4090 struct icl_port_dpll *port_dpll; 4091 bool pll_active; 4092 4093 if (drm_WARN_ON(&i915->drm, !pll)) 4094 return; 4095 4096 if (icl_ddi_tc_pll_is_tbt(pll)) 4097 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4098 else 4099 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4100 4101 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4102 4103 port_dpll->pll = pll; 4104 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4105 drm_WARN_ON(&i915->drm, !pll_active); 4106 4107 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4108 4109 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4110 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4111 else 4112 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4113 &crtc_state->dpll_hw_state); 4114} 4115 4116static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4117 struct intel_crtc_state *crtc_state) 4118{ 4119 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4120 intel_ddi_get_config(encoder, crtc_state); 4121} 4122 4123static void bxt_ddi_get_config(struct intel_encoder *encoder, 4124 struct intel_crtc_state *crtc_state) 4125{ 4126 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4127 intel_ddi_get_config(encoder, crtc_state); 4128} 4129 4130static void skl_ddi_get_config(struct intel_encoder *encoder, 4131 struct intel_crtc_state *crtc_state) 4132{ 4133 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4134 intel_ddi_get_config(encoder, crtc_state); 4135} 4136 4137void hsw_ddi_get_config(struct intel_encoder *encoder, 4138 struct intel_crtc_state *crtc_state) 4139{ 4140 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4141 intel_ddi_get_config(encoder, crtc_state); 4142} 4143 4144static void intel_ddi_sync_state(struct intel_encoder *encoder, 4145 const struct intel_crtc_state *crtc_state) 4146{ 4147 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4148 enum phy phy = intel_port_to_phy(i915, encoder->port); 4149 4150 if (intel_phy_is_tc(i915, phy)) 4151 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4152 crtc_state); 4153 4154 if (intel_encoder_is_dp(encoder)) 4155 intel_dp_sync_state(encoder, crtc_state); 4156} 4157 4158static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4159 struct intel_crtc_state *crtc_state) 4160{ 4161 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4162 enum phy phy = intel_port_to_phy(i915, encoder->port); 4163 bool fastset = true; 4164 4165 if (intel_phy_is_tc(i915, phy)) { 4166 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4167 encoder->base.base.id, encoder->base.name); 4168 crtc_state->uapi.mode_changed = true; 4169 fastset = false; 4170 } 4171 4172 if (intel_crtc_has_dp_encoder(crtc_state) && 4173 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4174 fastset = false; 4175 4176 return fastset; 4177} 4178 4179static enum intel_output_type 4180intel_ddi_compute_output_type(struct intel_encoder *encoder, 4181 struct intel_crtc_state *crtc_state, 4182 struct drm_connector_state *conn_state) 4183{ 4184 switch (conn_state->connector->connector_type) { 4185 case DRM_MODE_CONNECTOR_HDMIA: 4186 return INTEL_OUTPUT_HDMI; 4187 case DRM_MODE_CONNECTOR_eDP: 4188 return INTEL_OUTPUT_EDP; 4189 case DRM_MODE_CONNECTOR_DisplayPort: 4190 return INTEL_OUTPUT_DP; 4191 default: 4192 MISSING_CASE(conn_state->connector->connector_type); 4193 return INTEL_OUTPUT_UNUSED; 4194 } 4195} 4196 4197static int intel_ddi_compute_config(struct intel_encoder *encoder, 4198 struct intel_crtc_state *pipe_config, 4199 struct drm_connector_state *conn_state) 4200{ 4201 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4202 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4203 enum port port = encoder->port; 4204 int ret; 4205 4206 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4207 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4208 4209 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4210 pipe_config->has_hdmi_sink = 4211 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4212 4213 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4214 } else { 4215 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4216 } 4217 4218 if (ret) 4219 return ret; 4220 4221 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4222 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4223 pipe_config->pch_pfit.force_thru = 4224 pipe_config->pch_pfit.enabled || 4225 pipe_config->crc_enabled; 4226 4227 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4228 pipe_config->lane_lat_optim_mask = 4229 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4230 4231 intel_ddi_compute_min_voltage_level(pipe_config); 4232 4233 return 0; 4234} 4235 4236static bool mode_equal(const struct drm_display_mode *mode1, 4237 const struct drm_display_mode *mode2) 4238{ 4239 return drm_mode_match(mode1, mode2, 4240 DRM_MODE_MATCH_TIMINGS | 4241 DRM_MODE_MATCH_FLAGS | 4242 DRM_MODE_MATCH_3D_FLAGS) && 4243 mode1->clock == mode2->clock; /* we want an exact match */ 4244} 4245 4246static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4247 const struct intel_link_m_n *m_n_2) 4248{ 4249 return m_n_1->tu == m_n_2->tu && 4250 m_n_1->data_m == m_n_2->data_m && 4251 m_n_1->data_n == m_n_2->data_n && 4252 m_n_1->link_m == m_n_2->link_m && 4253 m_n_1->link_n == m_n_2->link_n; 4254} 4255 4256static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4257 const struct intel_crtc_state *crtc_state2) 4258{ 4259 /* 4260 * FIXME the modeset sequence is currently wrong and 4261 * can't deal with bigjoiner + port sync at the same time. 4262 */ 4263 return crtc_state1->hw.active && crtc_state2->hw.active && 4264 !crtc_state1->bigjoiner_pipes && !crtc_state2->bigjoiner_pipes && 4265 crtc_state1->output_types == crtc_state2->output_types && 4266 crtc_state1->output_format == crtc_state2->output_format && 4267 crtc_state1->lane_count == crtc_state2->lane_count && 4268 crtc_state1->port_clock == crtc_state2->port_clock && 4269 mode_equal(&crtc_state1->hw.adjusted_mode, 4270 &crtc_state2->hw.adjusted_mode) && 4271 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4272} 4273 4274static u8 4275intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4276 int tile_group_id) 4277{ 4278 struct drm_connector *connector; 4279 const struct drm_connector_state *conn_state; 4280 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4281 struct intel_atomic_state *state = 4282 to_intel_atomic_state(ref_crtc_state->uapi.state); 4283 u8 transcoders = 0; 4284 int i; 4285 4286 /* 4287 * We don't enable port sync on BDW due to missing w/as and 4288 * due to not having adjusted the modeset sequence appropriately. 4289 */ 4290 if (DISPLAY_VER(dev_priv) < 9) 4291 return 0; 4292 4293 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4294 return 0; 4295 4296 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4297 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4298 const struct intel_crtc_state *crtc_state; 4299 4300 if (!crtc) 4301 continue; 4302 4303 if (!connector->has_tile || 4304 connector->tile_group->id != 4305 tile_group_id) 4306 continue; 4307 crtc_state = intel_atomic_get_new_crtc_state(state, 4308 crtc); 4309 if (!crtcs_port_sync_compatible(ref_crtc_state, 4310 crtc_state)) 4311 continue; 4312 transcoders |= BIT(crtc_state->cpu_transcoder); 4313 } 4314 4315 return transcoders; 4316} 4317 4318static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4319 struct intel_crtc_state *crtc_state, 4320 struct drm_connector_state *conn_state) 4321{ 4322 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4323 struct drm_connector *connector = conn_state->connector; 4324 u8 port_sync_transcoders = 0; 4325 4326 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4327 encoder->base.base.id, encoder->base.name, 4328 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4329 4330 if (connector->has_tile) 4331 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4332 connector->tile_group->id); 4333 4334 /* 4335 * EDP Transcoders cannot be ensalved 4336 * make them a master always when present 4337 */ 4338 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4339 crtc_state->master_transcoder = TRANSCODER_EDP; 4340 else 4341 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4342 4343 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4344 crtc_state->master_transcoder = INVALID_TRANSCODER; 4345 crtc_state->sync_mode_slaves_mask = 4346 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4347 } 4348 4349 return 0; 4350} 4351 4352static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4353{ 4354 struct drm_i915_private *i915 = to_i915(encoder->dev); 4355 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4356 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 4357 4358 intel_dp_encoder_flush_work(encoder); 4359 if (intel_phy_is_tc(i915, phy)) 4360 intel_tc_port_cleanup(dig_port); 4361 intel_display_power_flush_work(i915); 4362 4363 drm_encoder_cleanup(encoder); 4364 kfree(dig_port->hdcp_port_data.streams); 4365 kfree(dig_port); 4366} 4367 4368static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4369{ 4370 struct drm_i915_private *i915 = to_i915(encoder->dev); 4371 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4372 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4373 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 4374 4375 intel_dp->reset_link_params = true; 4376 4377 intel_pps_encoder_reset(intel_dp); 4378 4379 if (intel_phy_is_tc(i915, phy)) 4380 intel_tc_port_init_mode(dig_port); 4381} 4382 4383static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4384{ 4385 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4386 4387 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4388 4389 return 0; 4390} 4391 4392static const struct drm_encoder_funcs intel_ddi_funcs = { 4393 .reset = intel_ddi_encoder_reset, 4394 .destroy = intel_ddi_encoder_destroy, 4395 .late_register = intel_ddi_encoder_late_register, 4396}; 4397 4398static struct intel_connector * 4399intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4400{ 4401 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4402 struct intel_connector *connector; 4403 enum port port = dig_port->base.port; 4404 4405 connector = intel_connector_alloc(); 4406 if (!connector) 4407 return NULL; 4408 4409 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4410 if (DISPLAY_VER(i915) >= 14) 4411 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4412 else 4413 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4414 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4415 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4416 4417 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4418 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4419 4420 if (!intel_dp_init_connector(dig_port, connector)) { 4421 kfree(connector); 4422 return NULL; 4423 } 4424 4425 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4426 struct drm_device *dev = dig_port->base.base.dev; 4427 struct drm_privacy_screen *privacy_screen; 4428 4429 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4430 if (!IS_ERR(privacy_screen)) { 4431 drm_connector_attach_privacy_screen_provider(&connector->base, 4432 privacy_screen); 4433 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4434 drm_warn(dev, "Error getting privacy-screen\n"); 4435 } 4436 } 4437 4438 return connector; 4439} 4440 4441static int modeset_pipe(struct drm_crtc *crtc, 4442 struct drm_modeset_acquire_ctx *ctx) 4443{ 4444 struct drm_atomic_state *state; 4445 struct drm_crtc_state *crtc_state; 4446 int ret; 4447 4448 state = drm_atomic_state_alloc(crtc->dev); 4449 if (!state) 4450 return -ENOMEM; 4451 4452 state->acquire_ctx = ctx; 4453 to_intel_atomic_state(state)->internal = true; 4454 4455 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4456 if (IS_ERR(crtc_state)) { 4457 ret = PTR_ERR(crtc_state); 4458 goto out; 4459 } 4460 4461 crtc_state->connectors_changed = true; 4462 4463 ret = drm_atomic_commit(state); 4464out: 4465 drm_atomic_state_put(state); 4466 4467 return ret; 4468} 4469 4470static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4471 struct drm_modeset_acquire_ctx *ctx) 4472{ 4473 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4474 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4475 struct intel_connector *connector = hdmi->attached_connector; 4476 struct i2c_adapter *ddc = connector->base.ddc; 4477 struct drm_connector_state *conn_state; 4478 struct intel_crtc_state *crtc_state; 4479 struct intel_crtc *crtc; 4480 u8 config; 4481 int ret; 4482 4483 if (connector->base.status != connector_status_connected) 4484 return 0; 4485 4486 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4487 ctx); 4488 if (ret) 4489 return ret; 4490 4491 conn_state = connector->base.state; 4492 4493 crtc = to_intel_crtc(conn_state->crtc); 4494 if (!crtc) 4495 return 0; 4496 4497 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4498 if (ret) 4499 return ret; 4500 4501 crtc_state = to_intel_crtc_state(crtc->base.state); 4502 4503 drm_WARN_ON(&dev_priv->drm, 4504 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4505 4506 if (!crtc_state->hw.active) 4507 return 0; 4508 4509 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4510 !crtc_state->hdmi_scrambling) 4511 return 0; 4512 4513 if (conn_state->commit && 4514 !try_wait_for_completion(&conn_state->commit->hw_done)) 4515 return 0; 4516 4517 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4518 if (ret < 0) { 4519 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4520 connector->base.base.id, connector->base.name, ret); 4521 return 0; 4522 } 4523 4524 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4525 crtc_state->hdmi_high_tmds_clock_ratio && 4526 !!(config & SCDC_SCRAMBLING_ENABLE) == 4527 crtc_state->hdmi_scrambling) 4528 return 0; 4529 4530 /* 4531 * HDMI 2.0 says that one should not send scrambled data 4532 * prior to configuring the sink scrambling, and that 4533 * TMDS clock/data transmission should be suspended when 4534 * changing the TMDS clock rate in the sink. So let's 4535 * just do a full modeset here, even though some sinks 4536 * would be perfectly happy if were to just reconfigure 4537 * the SCDC settings on the fly. 4538 */ 4539 return modeset_pipe(&crtc->base, ctx); 4540} 4541 4542static enum intel_hotplug_state 4543intel_ddi_hotplug(struct intel_encoder *encoder, 4544 struct intel_connector *connector) 4545{ 4546 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4547 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4548 struct intel_dp *intel_dp = &dig_port->dp; 4549 enum phy phy = intel_port_to_phy(i915, encoder->port); 4550 bool is_tc = intel_phy_is_tc(i915, phy); 4551 struct drm_modeset_acquire_ctx ctx; 4552 enum intel_hotplug_state state; 4553 int ret; 4554 4555 if (intel_dp->compliance.test_active && 4556 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4557 intel_dp_phy_test(encoder); 4558 /* just do the PHY test and nothing else */ 4559 return INTEL_HOTPLUG_UNCHANGED; 4560 } 4561 4562 state = intel_encoder_hotplug(encoder, connector); 4563 4564 if (!intel_tc_port_link_reset(dig_port)) { 4565 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) { 4566 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4567 ret = intel_hdmi_reset_link(encoder, &ctx); 4568 else 4569 ret = intel_dp_retrain_link(encoder, &ctx); 4570 } 4571 4572 drm_WARN_ON(encoder->base.dev, ret); 4573 } 4574 4575 /* 4576 * Unpowered type-c dongles can take some time to boot and be 4577 * responsible, so here giving some time to those dongles to power up 4578 * and then retrying the probe. 4579 * 4580 * On many platforms the HDMI live state signal is known to be 4581 * unreliable, so we can't use it to detect if a sink is connected or 4582 * not. Instead we detect if it's connected based on whether we can 4583 * read the EDID or not. That in turn has a problem during disconnect, 4584 * since the HPD interrupt may be raised before the DDC lines get 4585 * disconnected (due to how the required length of DDC vs. HPD 4586 * connector pins are specified) and so we'll still be able to get a 4587 * valid EDID. To solve this schedule another detection cycle if this 4588 * time around we didn't detect any change in the sink's connection 4589 * status. 4590 * 4591 * Type-c connectors which get their HPD signal deasserted then 4592 * reasserted, without unplugging/replugging the sink from the 4593 * connector, introduce a delay until the AUX channel communication 4594 * becomes functional. Retry the detection for 5 seconds on type-c 4595 * connectors to account for this delay. 4596 */ 4597 if (state == INTEL_HOTPLUG_UNCHANGED && 4598 connector->hotplug_retries < (is_tc ? 5 : 1) && 4599 !dig_port->dp.is_mst) 4600 state = INTEL_HOTPLUG_RETRY; 4601 4602 return state; 4603} 4604 4605static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4606{ 4607 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4608 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4609 4610 return intel_de_read(dev_priv, SDEISR) & bit; 4611} 4612 4613static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4614{ 4615 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4616 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4617 4618 return intel_de_read(dev_priv, DEISR) & bit; 4619} 4620 4621static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4622{ 4623 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4624 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4625 4626 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4627} 4628 4629static struct intel_connector * 4630intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4631{ 4632 struct intel_connector *connector; 4633 enum port port = dig_port->base.port; 4634 4635 connector = intel_connector_alloc(); 4636 if (!connector) 4637 return NULL; 4638 4639 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4640 intel_hdmi_init_connector(dig_port, connector); 4641 4642 return connector; 4643} 4644 4645static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4646{ 4647 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4648 4649 if (dig_port->base.port != PORT_A) 4650 return false; 4651 4652 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4653 return false; 4654 4655 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4656 * supported configuration 4657 */ 4658 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4659 return true; 4660 4661 return false; 4662} 4663 4664static int 4665intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4666{ 4667 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4668 enum port port = dig_port->base.port; 4669 int max_lanes = 4; 4670 4671 if (DISPLAY_VER(dev_priv) >= 11) 4672 return max_lanes; 4673 4674 if (port == PORT_A || port == PORT_E) { 4675 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4676 max_lanes = port == PORT_A ? 4 : 0; 4677 else 4678 /* Both A and E share 2 lanes */ 4679 max_lanes = 2; 4680 } 4681 4682 /* 4683 * Some BIOS might fail to set this bit on port A if eDP 4684 * wasn't lit up at boot. Force this bit set when needed 4685 * so we use the proper lane count for our calculations. 4686 */ 4687 if (intel_ddi_a_force_4_lanes(dig_port)) { 4688 drm_dbg_kms(&dev_priv->drm, 4689 "Forcing DDI_A_4_LANES for port A\n"); 4690 dig_port->saved_port_bits |= DDI_A_4_LANES; 4691 max_lanes = 4; 4692 } 4693 4694 return max_lanes; 4695} 4696 4697static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4698 enum port port) 4699{ 4700 if (port >= PORT_D_XELPD) 4701 return HPD_PORT_D + port - PORT_D_XELPD; 4702 else if (port >= PORT_TC1) 4703 return HPD_PORT_TC1 + port - PORT_TC1; 4704 else 4705 return HPD_PORT_A + port - PORT_A; 4706} 4707 4708static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4709 enum port port) 4710{ 4711 if (port >= PORT_TC1) 4712 return HPD_PORT_C + port - PORT_TC1; 4713 else 4714 return HPD_PORT_A + port - PORT_A; 4715} 4716 4717static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4718 enum port port) 4719{ 4720 if (port >= PORT_TC1) 4721 return HPD_PORT_TC1 + port - PORT_TC1; 4722 else 4723 return HPD_PORT_A + port - PORT_A; 4724} 4725 4726static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4727 enum port port) 4728{ 4729 if (HAS_PCH_TGP(dev_priv)) 4730 return tgl_hpd_pin(dev_priv, port); 4731 4732 if (port >= PORT_TC1) 4733 return HPD_PORT_C + port - PORT_TC1; 4734 else 4735 return HPD_PORT_A + port - PORT_A; 4736} 4737 4738static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4739 enum port port) 4740{ 4741 if (port >= PORT_C) 4742 return HPD_PORT_TC1 + port - PORT_C; 4743 else 4744 return HPD_PORT_A + port - PORT_A; 4745} 4746 4747static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4748 enum port port) 4749{ 4750 if (port == PORT_D) 4751 return HPD_PORT_A; 4752 4753 if (HAS_PCH_TGP(dev_priv)) 4754 return icl_hpd_pin(dev_priv, port); 4755 4756 return HPD_PORT_A + port - PORT_A; 4757} 4758 4759static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4760{ 4761 if (HAS_PCH_TGP(dev_priv)) 4762 return icl_hpd_pin(dev_priv, port); 4763 4764 return HPD_PORT_A + port - PORT_A; 4765} 4766 4767static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4768{ 4769 if (DISPLAY_VER(i915) >= 12) 4770 return port >= PORT_TC1; 4771 else if (DISPLAY_VER(i915) >= 11) 4772 return port >= PORT_C; 4773 else 4774 return false; 4775} 4776 4777static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4778{ 4779 intel_dp_encoder_suspend(encoder); 4780} 4781 4782static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4783{ 4784 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4785 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4786 4787 intel_tc_port_suspend(dig_port); 4788} 4789 4790static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4791{ 4792 intel_dp_encoder_shutdown(encoder); 4793 intel_hdmi_encoder_shutdown(encoder); 4794} 4795 4796static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4797{ 4798 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4799 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4800 4801 intel_tc_port_cleanup(dig_port); 4802} 4803 4804#define port_tc_name(port) ((port) - PORT_TC1 + '1') 4805#define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4806 4807static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 4808{ 4809 /* straps not used on skl+ */ 4810 if (DISPLAY_VER(i915) >= 9) 4811 return true; 4812 4813 switch (port) { 4814 case PORT_A: 4815 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 4816 case PORT_B: 4817 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 4818 case PORT_C: 4819 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 4820 case PORT_D: 4821 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 4822 case PORT_E: 4823 return true; /* no strap for DDI-E */ 4824 default: 4825 MISSING_CASE(port); 4826 return false; 4827 } 4828} 4829 4830static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 4831{ 4832 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4833 enum phy phy = intel_port_to_phy(i915, encoder->port); 4834 4835 return init_dp || intel_phy_is_tc(i915, phy); 4836} 4837 4838static bool assert_has_icl_dsi(struct drm_i915_private *i915) 4839{ 4840 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 4841 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 4842 "Platform does not support DSI\n"); 4843} 4844 4845static bool port_in_use(struct drm_i915_private *i915, enum port port) 4846{ 4847 struct intel_encoder *encoder; 4848 4849 for_each_intel_encoder(&i915->drm, encoder) { 4850 /* FIXME what about second port for dual link DSI? */ 4851 if (encoder->port == port) 4852 return true; 4853 } 4854 4855 return false; 4856} 4857 4858void intel_ddi_init(struct drm_i915_private *dev_priv, 4859 const struct intel_bios_encoder_data *devdata) 4860{ 4861 struct intel_digital_port *dig_port; 4862 struct intel_encoder *encoder; 4863 bool init_hdmi, init_dp; 4864 enum port port; 4865 enum phy phy; 4866 4867 port = intel_bios_encoder_port(devdata); 4868 if (port == PORT_NONE) 4869 return; 4870 4871 if (!port_strap_detected(dev_priv, port)) { 4872 drm_dbg_kms(&dev_priv->drm, 4873 "Port %c strap not detected\n", port_name(port)); 4874 return; 4875 } 4876 4877 if (!assert_port_valid(dev_priv, port)) 4878 return; 4879 4880 if (port_in_use(dev_priv, port)) { 4881 drm_dbg_kms(&dev_priv->drm, 4882 "Port %c already claimed\n", port_name(port)); 4883 return; 4884 } 4885 4886 if (intel_bios_encoder_supports_dsi(devdata)) { 4887 /* BXT/GLK handled elsewhere, for now at least */ 4888 if (!assert_has_icl_dsi(dev_priv)) 4889 return; 4890 4891 icl_dsi_init(dev_priv, devdata); 4892 return; 4893 } 4894 4895 phy = intel_port_to_phy(dev_priv, port); 4896 4897 /* 4898 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4899 * have taken over some of the PHYs and made them unavailable to the 4900 * driver. In that case we should skip initializing the corresponding 4901 * outputs. 4902 */ 4903 if (intel_hti_uses_phy(dev_priv, phy)) { 4904 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4905 port_name(port), phy_name(phy)); 4906 return; 4907 } 4908 4909 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4910 intel_bios_encoder_supports_hdmi(devdata); 4911 init_dp = intel_bios_encoder_supports_dp(devdata); 4912 4913 if (intel_bios_encoder_is_lspcon(devdata)) { 4914 /* 4915 * Lspcon device needs to be driven with DP connector 4916 * with special detection sequence. So make sure DP 4917 * is initialized before lspcon. 4918 */ 4919 init_dp = true; 4920 init_hdmi = false; 4921 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4922 port_name(port)); 4923 } 4924 4925 if (!init_dp && !init_hdmi) { 4926 drm_dbg_kms(&dev_priv->drm, 4927 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4928 port_name(port)); 4929 return; 4930 } 4931 4932 if (intel_phy_is_snps(dev_priv, phy) && 4933 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4934 drm_dbg_kms(&dev_priv->drm, 4935 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4936 phy_name(phy)); 4937 } 4938 4939 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4940 if (!dig_port) 4941 return; 4942 4943 dig_port->aux_ch = AUX_CH_NONE; 4944 4945 encoder = &dig_port->base; 4946 encoder->devdata = devdata; 4947 4948 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4949 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4950 DRM_MODE_ENCODER_TMDS, 4951 "DDI %c/PHY %c", 4952 port_name(port - PORT_D_XELPD + PORT_D), 4953 phy_name(phy)); 4954 } else if (DISPLAY_VER(dev_priv) >= 12) { 4955 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4956 4957 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4958 DRM_MODE_ENCODER_TMDS, 4959 "DDI %s%c/PHY %s%c", 4960 port >= PORT_TC1 ? "TC" : "", 4961 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4962 tc_port != TC_PORT_NONE ? "TC" : "", 4963 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4964 } else if (DISPLAY_VER(dev_priv) >= 11) { 4965 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4966 4967 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4968 DRM_MODE_ENCODER_TMDS, 4969 "DDI %c%s/PHY %s%c", 4970 port_name(port), 4971 port >= PORT_C ? " (TC)" : "", 4972 tc_port != TC_PORT_NONE ? "TC" : "", 4973 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4974 } else { 4975 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4976 DRM_MODE_ENCODER_TMDS, 4977 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4978 } 4979 4980 mutex_init(&dig_port->hdcp_mutex); 4981 dig_port->num_hdcp_streams = 0; 4982 4983 encoder->hotplug = intel_ddi_hotplug; 4984 encoder->compute_output_type = intel_ddi_compute_output_type; 4985 encoder->compute_config = intel_ddi_compute_config; 4986 encoder->compute_config_late = intel_ddi_compute_config_late; 4987 encoder->enable = intel_enable_ddi; 4988 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4989 encoder->pre_enable = intel_ddi_pre_enable; 4990 encoder->disable = intel_disable_ddi; 4991 encoder->post_pll_disable = intel_ddi_post_pll_disable; 4992 encoder->post_disable = intel_ddi_post_disable; 4993 encoder->update_pipe = intel_ddi_update_pipe; 4994 encoder->audio_enable = intel_audio_codec_enable; 4995 encoder->audio_disable = intel_audio_codec_disable; 4996 encoder->get_hw_state = intel_ddi_get_hw_state; 4997 encoder->sync_state = intel_ddi_sync_state; 4998 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4999 encoder->suspend = intel_ddi_encoder_suspend; 5000 encoder->shutdown = intel_ddi_encoder_shutdown; 5001 encoder->get_power_domains = intel_ddi_get_power_domains; 5002 5003 encoder->type = INTEL_OUTPUT_DDI; 5004 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 5005 encoder->port = port; 5006 encoder->cloneable = 0; 5007 encoder->pipe_mask = ~0; 5008 5009 if (DISPLAY_VER(dev_priv) >= 14) { 5010 encoder->enable_clock = intel_mtl_pll_enable; 5011 encoder->disable_clock = intel_mtl_pll_disable; 5012 encoder->port_pll_type = intel_mtl_port_pll_type; 5013 encoder->get_config = mtl_ddi_get_config; 5014 } else if (IS_DG2(dev_priv)) { 5015 encoder->enable_clock = intel_mpllb_enable; 5016 encoder->disable_clock = intel_mpllb_disable; 5017 encoder->get_config = dg2_ddi_get_config; 5018 } else if (IS_ALDERLAKE_S(dev_priv)) { 5019 encoder->enable_clock = adls_ddi_enable_clock; 5020 encoder->disable_clock = adls_ddi_disable_clock; 5021 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5022 encoder->get_config = adls_ddi_get_config; 5023 } else if (IS_ROCKETLAKE(dev_priv)) { 5024 encoder->enable_clock = rkl_ddi_enable_clock; 5025 encoder->disable_clock = rkl_ddi_disable_clock; 5026 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5027 encoder->get_config = rkl_ddi_get_config; 5028 } else if (IS_DG1(dev_priv)) { 5029 encoder->enable_clock = dg1_ddi_enable_clock; 5030 encoder->disable_clock = dg1_ddi_disable_clock; 5031 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5032 encoder->get_config = dg1_ddi_get_config; 5033 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5034 if (intel_ddi_is_tc(dev_priv, port)) { 5035 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5036 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5037 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5038 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5039 encoder->get_config = icl_ddi_combo_get_config; 5040 } else { 5041 encoder->enable_clock = icl_ddi_combo_enable_clock; 5042 encoder->disable_clock = icl_ddi_combo_disable_clock; 5043 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5044 encoder->get_config = icl_ddi_combo_get_config; 5045 } 5046 } else if (DISPLAY_VER(dev_priv) >= 11) { 5047 if (intel_ddi_is_tc(dev_priv, port)) { 5048 encoder->enable_clock = icl_ddi_tc_enable_clock; 5049 encoder->disable_clock = icl_ddi_tc_disable_clock; 5050 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5051 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5052 encoder->get_config = icl_ddi_tc_get_config; 5053 } else { 5054 encoder->enable_clock = icl_ddi_combo_enable_clock; 5055 encoder->disable_clock = icl_ddi_combo_disable_clock; 5056 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5057 encoder->get_config = icl_ddi_combo_get_config; 5058 } 5059 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5060 /* BXT/GLK have fixed PLL->port mapping */ 5061 encoder->get_config = bxt_ddi_get_config; 5062 } else if (DISPLAY_VER(dev_priv) == 9) { 5063 encoder->enable_clock = skl_ddi_enable_clock; 5064 encoder->disable_clock = skl_ddi_disable_clock; 5065 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5066 encoder->get_config = skl_ddi_get_config; 5067 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5068 encoder->enable_clock = hsw_ddi_enable_clock; 5069 encoder->disable_clock = hsw_ddi_disable_clock; 5070 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5071 encoder->get_config = hsw_ddi_get_config; 5072 } 5073 5074 if (DISPLAY_VER(dev_priv) >= 14) { 5075 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5076 } else if (IS_DG2(dev_priv)) { 5077 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5078 } else if (DISPLAY_VER(dev_priv) >= 12) { 5079 if (intel_phy_is_combo(dev_priv, phy)) 5080 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5081 else 5082 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5083 } else if (DISPLAY_VER(dev_priv) >= 11) { 5084 if (intel_phy_is_combo(dev_priv, phy)) 5085 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5086 else 5087 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5088 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5089 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 5090 } else { 5091 encoder->set_signal_levels = hsw_set_signal_levels; 5092 } 5093 5094 intel_ddi_buf_trans_init(encoder); 5095 5096 if (DISPLAY_VER(dev_priv) >= 13) 5097 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5098 else if (IS_DG1(dev_priv)) 5099 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5100 else if (IS_ROCKETLAKE(dev_priv)) 5101 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5102 else if (DISPLAY_VER(dev_priv) >= 12) 5103 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5104 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5105 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5106 else if (DISPLAY_VER(dev_priv) == 11) 5107 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5108 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5109 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5110 else 5111 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5112 5113 if (DISPLAY_VER(dev_priv) >= 11) 5114 dig_port->saved_port_bits = 5115 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5116 & DDI_BUF_PORT_REVERSAL; 5117 else 5118 dig_port->saved_port_bits = 5119 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5120 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5121 5122 if (intel_bios_encoder_lane_reversal(devdata)) 5123 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 5124 5125 dig_port->dp.output_reg = INVALID_MMIO_REG; 5126 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5127 5128 if (need_aux_ch(encoder, init_dp)) { 5129 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5130 if (dig_port->aux_ch == AUX_CH_NONE) 5131 goto err; 5132 } 5133 5134 if (intel_phy_is_tc(dev_priv, phy)) { 5135 bool is_legacy = 5136 !intel_bios_encoder_supports_typec_usb(devdata) && 5137 !intel_bios_encoder_supports_tbt(devdata); 5138 5139 if (!is_legacy && init_hdmi) { 5140 is_legacy = !init_dp; 5141 5142 drm_dbg_kms(&dev_priv->drm, 5143 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5144 port_name(port), 5145 str_yes_no(init_dp), 5146 is_legacy ? "legacy" : "non-legacy"); 5147 } 5148 5149 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5150 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5151 5152 dig_port->lock = intel_tc_port_lock; 5153 dig_port->unlock = intel_tc_port_unlock; 5154 5155 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5156 goto err; 5157 } 5158 5159 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5160 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5161 5162 if (DISPLAY_VER(dev_priv) >= 11) { 5163 if (intel_phy_is_tc(dev_priv, phy)) 5164 dig_port->connected = intel_tc_port_connected; 5165 else 5166 dig_port->connected = lpt_digital_port_connected; 5167 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5168 dig_port->connected = bdw_digital_port_connected; 5169 } else if (DISPLAY_VER(dev_priv) == 9) { 5170 dig_port->connected = lpt_digital_port_connected; 5171 } else if (IS_BROADWELL(dev_priv)) { 5172 if (port == PORT_A) 5173 dig_port->connected = bdw_digital_port_connected; 5174 else 5175 dig_port->connected = lpt_digital_port_connected; 5176 } else if (IS_HASWELL(dev_priv)) { 5177 if (port == PORT_A) 5178 dig_port->connected = hsw_digital_port_connected; 5179 else 5180 dig_port->connected = lpt_digital_port_connected; 5181 } 5182 5183 intel_infoframe_init(dig_port); 5184 5185 if (init_dp) { 5186 if (!intel_ddi_init_dp_connector(dig_port)) 5187 goto err; 5188 5189 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5190 5191 if (dig_port->dp.mso_link_count) 5192 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5193 } 5194 5195 /* 5196 * In theory we don't need the encoder->type check, 5197 * but leave it just in case we have some really bad VBTs... 5198 */ 5199 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5200 if (!intel_ddi_init_hdmi_connector(dig_port)) 5201 goto err; 5202 } 5203 5204 return; 5205 5206err: 5207 drm_encoder_cleanup(&encoder->base); 5208 kfree(dig_port); 5209} 5210