i915/display/intel_pps.c

98 		     intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
112 	DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
122 	pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
275 	return intel_de_read(dev_priv, PP_STATUS(pps_idx)) & PP_ON;
280 	return intel_de_read(dev_priv, PP_CONTROL(pps_idx)) & EDP_FORCE_VDD;
295 		u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
370 		return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
537 	return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
550 	return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
570 			    intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
571 			    intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
605 		    intel_de_read(dev_priv, pp_stat_reg),
606 		    intel_de_read(dev_priv, pp_ctrl_reg));
613 			intel_de_read(dev_priv, pp_stat_reg),
614 			intel_de_read(dev_priv, pp_ctrl_reg));
700 	control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
755 		    intel_de_read(dev_priv, pp_stat_reg),
756 		    intel_de_read(dev_priv, pp_ctrl_reg));
827 		    intel_de_read(dev_priv, pp_stat_reg),
828 		    intel_de_read(dev_priv, pp_ctrl_reg));
1281 	pp_on = intel_de_read(dev_priv, regs.pp_on);
1282 	pp_off = intel_de_read(dev_priv, regs.pp_off);
1293 		pp_div = intel_de_read(dev_priv, regs.pp_div);
1551 		    intel_de_read(dev_priv, regs.pp_on),
1552 		    intel_de_read(dev_priv, regs.pp_off),
1554 		    intel_de_read(dev_priv, regs.pp_div) :
1555 		    (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
1718 		port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1745 		port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1752 	val = intel_de_read(dev_priv, pp_reg);