i915/display/intel_display.c

327 		u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
397 			 intel_de_read(dev_priv, dpll_reg) & port_mask,
451 	val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
497 	val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
732 	tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
1859 		    intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
2194 		    intel_de_read(dev_priv, PFIT_CONTROL));
2583 		bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2796 		return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2798 		return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2810 	tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
2815 		tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
2820 	tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
2824 	tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
2830 		tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
2834 	tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
2847 			intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
2874 	tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
2970 	tmp = intel_de_read(dev_priv, PFIT_CONTROL);
2985 		intel_de_read(dev_priv, PFIT_PGM_RATIOS);
2994 	tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3030 	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3266 	tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3311 	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3312 	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3313 	m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3314 	m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3315 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3356 	ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3367 	pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3368 	size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3403 	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3488 		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3509 			u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3525 			u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3603 			tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3710 		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3716 	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3752 		tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
3756 		tmp = intel_de_read(display, MIPI_CTRL(display, port));
3821 		u32 tmp = intel_de_read(dev_priv,
3837 	tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
3856 			intel_de_read(dev_priv,
3863 		tmp = intel_de_read(dev_priv, hsw_chicken_trans_reg(dev_priv, pipe_config->cpu_transcoder));
7632 	if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7635 	if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7650 	    intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7654 	if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7703 		if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
7708 			if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
7712 		if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
7715 		if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
7718 		if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
7721 		if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
7746 		if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
7748 		if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7753 		if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
7755 		if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7764 			if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
7766 			if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
7782 		if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7797 		if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7802 		if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
7813 		if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
8224 		    intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
8226 		    intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
8228 		    intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
8230 		    intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8232 		    intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);