1// SPDX-License-Identifier: MIT
2/*
3 * Copyright �� 2018 Intel Corporation
4 */
5
6#include "i915_reg.h"
7#include "intel_combo_phy.h"
8#include "intel_combo_phy_regs.h"
9#include "intel_de.h"
10#include "intel_display_types.h"
11
12#define for_each_combo_phy(__dev_priv, __phy) \
13	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
14		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
15
16#define for_each_combo_phy_reverse(__dev_priv, __phy) \
17	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
18		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
19
20enum {
21	PROCMON_0_85V_DOT_0,
22	PROCMON_0_95V_DOT_0,
23	PROCMON_0_95V_DOT_1,
24	PROCMON_1_05V_DOT_0,
25	PROCMON_1_05V_DOT_1,
26};
27
28static const struct icl_procmon {
29	const char *name;
30	u32 dw1, dw9, dw10;
31} icl_procmon_values[] = {
32	[PROCMON_0_85V_DOT_0] = {
33		.name = "0.85V dot0 (low-voltage)",
34		.dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96,
35	},
36	[PROCMON_0_95V_DOT_0] = {
37		.name = "0.95V dot0",
38		.dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB,
39	},
40	[PROCMON_0_95V_DOT_1] = {
41		.name = "0.95V dot1",
42		.dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5,
43	},
44	[PROCMON_1_05V_DOT_0] = {
45		.name = "1.05V dot0",
46		.dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1,
47	},
48	[PROCMON_1_05V_DOT_1] = {
49		.name = "1.05V dot1",
50		.dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1,
51	},
52};
53
54static const struct icl_procmon *
55icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
56{
57	u32 val;
58
59	val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
60	switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
61	default:
62		MISSING_CASE(val);
63		fallthrough;
64	case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
65		return &icl_procmon_values[PROCMON_0_85V_DOT_0];
66	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
67		return &icl_procmon_values[PROCMON_0_95V_DOT_0];
68	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
69		return &icl_procmon_values[PROCMON_0_95V_DOT_1];
70	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
71		return &icl_procmon_values[PROCMON_1_05V_DOT_0];
72	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
73		return &icl_procmon_values[PROCMON_1_05V_DOT_1];
74	}
75}
76
77static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
78				       enum phy phy)
79{
80	const struct icl_procmon *procmon;
81
82	procmon = icl_get_procmon_ref_values(dev_priv, phy);
83
84	intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy),
85		     (0xff << 16) | 0xff, procmon->dw1);
86
87	intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);
88	intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);
89}
90
91static bool check_phy_reg(struct drm_i915_private *dev_priv,
92			  enum phy phy, i915_reg_t reg, u32 mask,
93			  u32 expected_val)
94{
95	u32 val = intel_de_read(dev_priv, reg);
96
97	if ((val & mask) != expected_val) {
98		drm_dbg(&dev_priv->drm,
99			"Combo PHY %c reg %08x state mismatch: "
100			"current %08x mask %08x expected %08x\n",
101			phy_name(phy),
102			reg.reg, val, mask, expected_val);
103		return false;
104	}
105
106	return true;
107}
108
109static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
110					  enum phy phy)
111{
112	const struct icl_procmon *procmon;
113	bool ret;
114
115	procmon = icl_get_procmon_ref_values(dev_priv, phy);
116
117	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
118			    (0xff << 16) | 0xff, procmon->dw1);
119	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
120			     -1U, procmon->dw9);
121	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
122			     -1U, procmon->dw10);
123
124	return ret;
125}
126
127static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
128{
129	/*
130	 * Some platforms only expect PHY_MISC to be programmed for PHY-A and
131	 * PHY-B and may not even have instances of the register for the
132	 * other combo PHY's.
133	 *
134	 * ADL-S technically has three instances of PHY_MISC, but only requires
135	 * that we program it for PHY A.
136	 */
137
138	if (IS_ALDERLAKE_S(i915))
139		return phy == PHY_A;
140	else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) ||
141		 IS_ROCKETLAKE(i915) ||
142		 IS_DG1(i915))
143		return phy < PHY_C;
144
145	return true;
146}
147
148static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
149				  enum phy phy)
150{
151	/* The PHY C added by EHL has no PHY_MISC register */
152	if (!has_phy_misc(dev_priv, phy))
153		return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
154	else
155		return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) &
156			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
157			(intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
158}
159
160static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)
161{
162	bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A);
163	bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D);
164	bool dsi_present = intel_bios_is_dsi_present(i915, NULL);
165
166	/*
167	 * VBT's 'dvo port' field for child devices references the DDI, not
168	 * the PHY.  So if combo PHY A is wired up to drive an external
169	 * display, we should see a child device present on PORT_D and
170	 * nothing on PORT_A and no DSI.
171	 */
172	if (ddi_d_present && !ddi_a_present && !dsi_present)
173		return true;
174
175	/*
176	 * If we encounter a VBT that claims to have an external display on
177	 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message
178	 * in the log and let the internal display win.
179	 */
180	if (ddi_d_present)
181		drm_err(&i915->drm,
182			"VBT claims to have both internal and external displays on PHY A.  Configuring for internal.\n");
183
184	return false;
185}
186
187static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
188{
189	/*
190	 * Certain PHYs are connected to compensation resistors and act
191	 * as masters to other PHYs.
192	 *
193	 * ICL,TGL:
194	 *   A(master) -> B(slave), C(slave)
195	 * RKL,DG1:
196	 *   A(master) -> B(slave)
197	 *   C(master) -> D(slave)
198	 * ADL-S:
199	 *   A(master) -> B(slave), C(slave)
200	 *   D(master) -> E(slave)
201	 *
202	 * We must set the IREFGEN bit for any PHY acting as a master
203	 * to another PHY.
204	 */
205	if (phy == PHY_A)
206		return true;
207	else if (IS_ALDERLAKE_S(dev_priv))
208		return phy == PHY_D;
209	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
210		return phy == PHY_C;
211
212	return false;
213}
214
215static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
216				       enum phy phy)
217{
218	bool ret = true;
219	u32 expected_val = 0;
220
221	if (!icl_combo_phy_enabled(dev_priv, phy))
222		return false;
223
224	if (DISPLAY_VER(dev_priv) >= 12) {
225		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy),
226				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
227				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
228				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
229				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
230
231		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
232				     DCC_MODE_SELECT_MASK, RUN_DCC_ONCE);
233	}
234
235	ret &= icl_verify_procmon_ref_values(dev_priv, phy);
236
237	if (phy_is_master(dev_priv, phy)) {
238		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
239				     IREFGEN, IREFGEN);
240
241		if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
242			if (ehl_vbt_ddi_d_present(dev_priv))
243				expected_val = ICL_PHY_MISC_MUX_DDID;
244
245			ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy),
246					     ICL_PHY_MISC_MUX_DDID,
247					     expected_val);
248		}
249	}
250
251	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
252			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
253
254	return ret;
255}
256
257void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
258				    enum phy phy, bool is_dsi,
259				    int lane_count, bool lane_reversal)
260{
261	u8 lane_mask;
262
263	if (is_dsi) {
264		drm_WARN_ON(&dev_priv->drm, lane_reversal);
265
266		switch (lane_count) {
267		case 1:
268			lane_mask = PWR_DOWN_LN_3_1_0;
269			break;
270		case 2:
271			lane_mask = PWR_DOWN_LN_3_1;
272			break;
273		case 3:
274			lane_mask = PWR_DOWN_LN_3;
275			break;
276		default:
277			MISSING_CASE(lane_count);
278			fallthrough;
279		case 4:
280			lane_mask = PWR_UP_ALL_LANES;
281			break;
282		}
283	} else {
284		switch (lane_count) {
285		case 1:
286			lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 :
287						    PWR_DOWN_LN_3_2_1;
288			break;
289		case 2:
290			lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 :
291						    PWR_DOWN_LN_3_2;
292			break;
293		default:
294			MISSING_CASE(lane_count);
295			fallthrough;
296		case 4:
297			lane_mask = PWR_UP_ALL_LANES;
298			break;
299		}
300	}
301
302	intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy),
303		     PWR_DOWN_LN_MASK, lane_mask);
304}
305
306static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
307{
308	enum phy phy;
309
310	for_each_combo_phy(dev_priv, phy) {
311		const struct icl_procmon *procmon;
312		u32 val;
313
314		if (icl_combo_phy_verify_state(dev_priv, phy))
315			continue;
316
317		procmon = icl_get_procmon_ref_values(dev_priv, phy);
318
319		drm_dbg(&dev_priv->drm,
320			"Initializing combo PHY %c (Voltage/Process Info : %s)\n",
321			phy_name(phy), procmon->name);
322
323		if (!has_phy_misc(dev_priv, phy))
324			goto skip_phy_misc;
325
326		/*
327		 * EHL's combo PHY A can be hooked up to either an external
328		 * display (via DDI-D) or an internal display (via DDI-A or
329		 * the DSI DPHY).  This is a motherboard design decision that
330		 * can't be changed on the fly, so initialize the PHY's mux
331		 * based on whether our VBT indicates the presence of any
332		 * "internal" child devices.
333		 */
334		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
335		if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
336		    phy == PHY_A) {
337			val &= ~ICL_PHY_MISC_MUX_DDID;
338
339			if (ehl_vbt_ddi_d_present(dev_priv))
340				val |= ICL_PHY_MISC_MUX_DDID;
341		}
342
343		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
344		intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
345
346skip_phy_misc:
347		if (DISPLAY_VER(dev_priv) >= 12) {
348			val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy));
349			val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
350			val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
351			val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
352			intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
353
354			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
355			val &= ~DCC_MODE_SELECT_MASK;
356			val |= RUN_DCC_ONCE;
357			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
358		}
359
360		icl_set_procmon_ref_values(dev_priv, phy);
361
362		if (phy_is_master(dev_priv, phy))
363			intel_de_rmw(dev_priv, ICL_PORT_COMP_DW8(phy),
364				     0, IREFGEN);
365
366		intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT);
367		intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),
368			     0, CL_POWER_DOWN_ENABLE);
369	}
370}
371
372static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
373{
374	enum phy phy;
375
376	for_each_combo_phy_reverse(dev_priv, phy) {
377		if (phy == PHY_A &&
378		    !icl_combo_phy_verify_state(dev_priv, phy)) {
379			if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) {
380				/*
381				 * A known problem with old ifwi:
382				 * https://gitlab.freedesktop.org/drm/intel/-/issues/2411
383				 * Suppress the warning for CI. Remove ASAP!
384				 */
385				drm_dbg_kms(&dev_priv->drm,
386					    "Combo PHY %c HW state changed unexpectedly\n",
387					    phy_name(phy));
388			} else {
389				drm_warn(&dev_priv->drm,
390					 "Combo PHY %c HW state changed unexpectedly\n",
391					 phy_name(phy));
392			}
393		}
394
395		if (!has_phy_misc(dev_priv, phy))
396			goto skip_phy_misc;
397
398		intel_de_rmw(dev_priv, ICL_PHY_MISC(phy), 0,
399			     ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN);
400
401skip_phy_misc:
402		intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);
403	}
404}
405
406void intel_combo_phy_init(struct drm_i915_private *i915)
407{
408	icl_combo_phys_init(i915);
409}
410
411void intel_combo_phy_uninit(struct drm_i915_private *i915)
412{
413	icl_combo_phys_uninit(i915);
414}
415