1/* 2 * Copyright �� 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28#include <drm/display/drm_dsc_helper.h> 29#include <drm/drm_atomic_helper.h> 30#include <drm/drm_mipi_dsi.h> 31 32#include "i915_reg.h" 33#include "icl_dsi.h" 34#include "icl_dsi_regs.h" 35#include "intel_atomic.h" 36#include "intel_backlight.h" 37#include "intel_backlight_regs.h" 38#include "intel_combo_phy.h" 39#include "intel_combo_phy_regs.h" 40#include "intel_connector.h" 41#include "intel_crtc.h" 42#include "intel_ddi.h" 43#include "intel_de.h" 44#include "intel_dsi.h" 45#include "intel_dsi_vbt.h" 46#include "intel_panel.h" 47#include "intel_vdsc.h" 48#include "intel_vdsc_regs.h" 49#include "skl_scaler.h" 50#include "skl_universal_plane.h" 51 52static int header_credits_available(struct drm_i915_private *dev_priv, 53 enum transcoder dsi_trans) 54{ 55 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 56 >> FREE_HEADER_CREDIT_SHIFT; 57} 58 59static int payload_credits_available(struct drm_i915_private *dev_priv, 60 enum transcoder dsi_trans) 61{ 62 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 63 >> FREE_PLOAD_CREDIT_SHIFT; 64} 65 66static bool wait_for_header_credits(struct drm_i915_private *dev_priv, 67 enum transcoder dsi_trans, int hdr_credit) 68{ 69 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 70 hdr_credit, 100)) { 71 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 72 return false; 73 } 74 75 return true; 76} 77 78static bool wait_for_payload_credits(struct drm_i915_private *dev_priv, 79 enum transcoder dsi_trans, int payld_credit) 80{ 81 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 82 payld_credit, 100)) { 83 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 84 return false; 85 } 86 87 return true; 88} 89 90static enum transcoder dsi_port_to_transcoder(enum port port) 91{ 92 if (port == PORT_A) 93 return TRANSCODER_DSI_0; 94 else 95 return TRANSCODER_DSI_1; 96} 97 98static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 99{ 100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 101 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 102 struct mipi_dsi_device *dsi; 103 enum port port; 104 enum transcoder dsi_trans; 105 int ret; 106 107 /* wait for header/payload credits to be released */ 108 for_each_dsi_port(port, intel_dsi->ports) { 109 dsi_trans = dsi_port_to_transcoder(port); 110 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 111 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT); 112 } 113 114 /* send nop DCS command */ 115 for_each_dsi_port(port, intel_dsi->ports) { 116 dsi = intel_dsi->dsi_hosts[port]->device; 117 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 118 dsi->channel = 0; 119 ret = mipi_dsi_dcs_nop(dsi); 120 if (ret < 0) 121 drm_err(&dev_priv->drm, 122 "error sending DCS NOP command\n"); 123 } 124 125 /* wait for header credits to be released */ 126 for_each_dsi_port(port, intel_dsi->ports) { 127 dsi_trans = dsi_port_to_transcoder(port); 128 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); 129 } 130 131 /* wait for LP TX in progress bit to be cleared */ 132 for_each_dsi_port(port, intel_dsi->ports) { 133 dsi_trans = dsi_port_to_transcoder(port); 134 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 135 LPTX_IN_PROGRESS), 20)) 136 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 137 } 138} 139 140static int dsi_send_pkt_payld(struct intel_dsi_host *host, 141 const struct mipi_dsi_packet *packet) 142{ 143 struct intel_dsi *intel_dsi = host->intel_dsi; 144 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 145 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 146 const u8 *data = packet->payload; 147 u32 len = packet->payload_length; 148 int i, j; 149 150 /* payload queue can accept *256 bytes*, check limit */ 151 if (len > MAX_PLOAD_CREDIT * 4) { 152 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); 153 return -EINVAL; 154 } 155 156 for (i = 0; i < len; i += 4) { 157 u32 tmp = 0; 158 159 if (!wait_for_payload_credits(i915, dsi_trans, 1)) 160 return -EBUSY; 161 162 for (j = 0; j < min_t(u32, len - i, 4); j++) 163 tmp |= *data++ << 8 * j; 164 165 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp); 166 } 167 168 return 0; 169} 170 171static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 172 const struct mipi_dsi_packet *packet, 173 bool enable_lpdt) 174{ 175 struct intel_dsi *intel_dsi = host->intel_dsi; 176 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 177 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 178 u32 tmp; 179 180 if (!wait_for_header_credits(dev_priv, dsi_trans, 1)) 181 return -EBUSY; 182 183 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 184 185 if (packet->payload) 186 tmp |= PAYLOAD_PRESENT; 187 else 188 tmp &= ~PAYLOAD_PRESENT; 189 190 tmp &= ~VBLANK_FENCE; 191 192 if (enable_lpdt) 193 tmp |= LP_DATA_TRANSFER; 194 else 195 tmp &= ~LP_DATA_TRANSFER; 196 197 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 198 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 199 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 200 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 201 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 202 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 203 204 return 0; 205} 206 207void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 208{ 209 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 210 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 211 u32 mode_flags; 212 enum port port; 213 214 mode_flags = crtc_state->mode_flags; 215 216 /* 217 * case 1 also covers dual link 218 * In case of dual link, frame update should be set on 219 * DSI_0 220 */ 221 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 222 port = PORT_A; 223 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 224 port = PORT_B; 225 else 226 return; 227 228 intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0, DSI_FRAME_UPDATE_REQUEST); 229} 230 231static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 232{ 233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 234 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 235 enum phy phy; 236 u32 tmp, mask, val; 237 int lane; 238 239 for_each_dsi_phy(phy, intel_dsi->phys) { 240 /* 241 * Program voltage swing and pre-emphasis level values as per 242 * table in BSPEC under DDI buffer programing 243 */ 244 mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK; 245 val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE | 246 RTERM_SELECT(0x6); 247 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 248 tmp &= ~mask; 249 tmp |= val; 250 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 251 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val); 252 253 mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 254 RCOMP_SCALAR_MASK; 255 val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) | 256 RCOMP_SCALAR(0x98); 257 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 258 tmp &= ~mask; 259 tmp |= val; 260 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 261 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val); 262 263 mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 264 CURSOR_COEFF_MASK; 265 val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) | 266 CURSOR_COEFF(0x3f); 267 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val); 268 269 /* Bspec: must not use GRP register for write */ 270 for (lane = 0; lane <= 3; lane++) 271 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), 272 mask, val); 273 } 274} 275 276static void configure_dual_link_mode(struct intel_encoder *encoder, 277 const struct intel_crtc_state *pipe_config) 278{ 279 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 280 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 281 i915_reg_t dss_ctl1_reg, dss_ctl2_reg; 282 u32 dss_ctl1; 283 284 /* FIXME: Move all DSS handling to intel_vdsc.c */ 285 if (DISPLAY_VER(dev_priv) >= 12) { 286 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 287 288 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); 289 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); 290 } else { 291 dss_ctl1_reg = DSS_CTL1; 292 dss_ctl2_reg = DSS_CTL2; 293 } 294 295 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg); 296 dss_ctl1 |= SPLITTER_ENABLE; 297 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 298 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 299 300 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 301 const struct drm_display_mode *adjusted_mode = 302 &pipe_config->hw.adjusted_mode; 303 u16 hactive = adjusted_mode->crtc_hdisplay; 304 u16 dl_buffer_depth; 305 306 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 307 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 308 309 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 310 drm_err(&dev_priv->drm, 311 "DL buffer depth exceed max value\n"); 312 313 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 314 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 315 intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, 316 RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth)); 317 } else { 318 /* Interleave */ 319 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 320 } 321 322 intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1); 323} 324 325/* aka DSI 8X clock */ 326static int afe_clk(struct intel_encoder *encoder, 327 const struct intel_crtc_state *crtc_state) 328{ 329 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 330 int bpp; 331 332 if (crtc_state->dsc.compression_enable) 333 bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); 334 else 335 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 336 337 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 338} 339 340static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 341 const struct intel_crtc_state *crtc_state) 342{ 343 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 344 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 345 enum port port; 346 int afe_clk_khz; 347 int theo_word_clk, act_word_clk; 348 u32 esc_clk_div_m, esc_clk_div_m_phy; 349 350 afe_clk_khz = afe_clk(encoder, crtc_state); 351 352 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 353 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 354 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 355 esc_clk_div_m = act_word_clk * 8; 356 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 357 } else { 358 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 359 } 360 361 for_each_dsi_port(port, intel_dsi->ports) { 362 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 363 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 364 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 365 } 366 367 for_each_dsi_port(port, intel_dsi->ports) { 368 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 369 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 370 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 371 } 372 373 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 374 for_each_dsi_port(port, intel_dsi->ports) { 375 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), 376 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 377 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); 378 } 379 } 380} 381 382static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 383 struct intel_dsi *intel_dsi) 384{ 385 enum port port; 386 387 for_each_dsi_port(port, intel_dsi->ports) { 388 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 389 intel_dsi->io_wakeref[port] = 390 intel_display_power_get(dev_priv, 391 port == PORT_A ? 392 POWER_DOMAIN_PORT_DDI_IO_A : 393 POWER_DOMAIN_PORT_DDI_IO_B); 394 } 395} 396 397static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 398{ 399 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 400 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 401 enum port port; 402 403 for_each_dsi_port(port, intel_dsi->ports) 404 intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port), 405 0, COMBO_PHY_MODE_DSI); 406 407 get_dsi_io_power_domains(dev_priv, intel_dsi); 408} 409 410static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 411{ 412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 413 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 414 enum phy phy; 415 416 for_each_dsi_phy(phy, intel_dsi->phys) 417 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 418 intel_dsi->lane_count, false); 419} 420 421static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 422{ 423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 424 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 425 enum phy phy; 426 u32 tmp; 427 int lane; 428 429 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 430 for_each_dsi_phy(phy, intel_dsi->phys) { 431 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), LOADGEN_SELECT, 0); 432 for (lane = 0; lane <= 3; lane++) 433 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), 434 LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0); 435 } 436 437 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 438 for_each_dsi_phy(phy, intel_dsi->phys) { 439 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), 440 FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5)); 441 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); 442 tmp &= ~FRC_LATENCY_OPTIM_MASK; 443 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 444 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 445 446 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 447 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) || 448 (DISPLAY_VER(dev_priv) >= 12)) { 449 intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 450 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0)); 451 452 tmp = intel_de_read(dev_priv, 453 ICL_PORT_PCS_DW1_LN(0, phy)); 454 tmp &= ~LATENCY_OPTIM_MASK; 455 tmp |= LATENCY_OPTIM_VAL(0x1); 456 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 457 tmp); 458 } 459 } 460 461} 462 463static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 464{ 465 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 466 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 467 u32 tmp; 468 enum phy phy; 469 470 /* clear common keeper enable bit */ 471 for_each_dsi_phy(phy, intel_dsi->phys) { 472 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 473 tmp &= ~COMMON_KEEPER_EN; 474 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 475 intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0); 476 } 477 478 /* 479 * Set SUS Clock Config bitfield to 11b 480 * Note: loadgen select program is done 481 * as part of lane phy sequence configuration 482 */ 483 for_each_dsi_phy(phy, intel_dsi->phys) 484 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 0, SUS_CLOCK_CONFIG); 485 486 /* Clear training enable to change swing values */ 487 for_each_dsi_phy(phy, intel_dsi->phys) { 488 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 489 tmp &= ~TX_TRAINING_EN; 490 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 491 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0); 492 } 493 494 /* Program swing and de-emphasis */ 495 dsi_program_swing_and_deemphasis(encoder); 496 497 /* Set training enable to trigger update */ 498 for_each_dsi_phy(phy, intel_dsi->phys) { 499 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 500 tmp |= TX_TRAINING_EN; 501 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 502 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN); 503 } 504} 505 506static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 507{ 508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 509 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 510 enum port port; 511 512 for_each_dsi_port(port, intel_dsi->ports) { 513 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE); 514 515 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 516 DDI_BUF_IS_IDLE), 517 500)) 518 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 519 port_name(port)); 520 } 521} 522 523static void 524gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 525 const struct intel_crtc_state *crtc_state) 526{ 527 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 528 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 529 enum port port; 530 enum phy phy; 531 532 /* Program DPHY clock lanes timings */ 533 for_each_dsi_port(port, intel_dsi->ports) 534 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 535 intel_dsi->dphy_reg); 536 537 /* Program DPHY data lanes timings */ 538 for_each_dsi_port(port, intel_dsi->ports) 539 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 540 intel_dsi->dphy_data_lane_reg); 541 542 /* 543 * If DSI link operating at or below an 800 MHz, 544 * TA_SURE should be override and programmed to 545 * a value '0' inside TA_PARAM_REGISTERS otherwise 546 * leave all fields at HW default values. 547 */ 548 if (DISPLAY_VER(dev_priv) == 11) { 549 if (afe_clk(encoder, crtc_state) <= 800000) { 550 for_each_dsi_port(port, intel_dsi->ports) 551 intel_de_rmw(dev_priv, DPHY_TA_TIMING_PARAM(port), 552 TA_SURE_MASK, 553 TA_SURE_OVERRIDE | TA_SURE(0)); 554 } 555 } 556 557 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 558 for_each_dsi_phy(phy, intel_dsi->phys) 559 intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy), 560 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP); 561 } 562} 563 564static void 565gen11_dsi_setup_timings(struct intel_encoder *encoder, 566 const struct intel_crtc_state *crtc_state) 567{ 568 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 569 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 570 enum port port; 571 572 /* Program T-INIT master registers */ 573 for_each_dsi_port(port, intel_dsi->ports) 574 intel_de_rmw(dev_priv, ICL_DSI_T_INIT_MASTER(port), 575 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count); 576 577 /* shadow register inside display core */ 578 for_each_dsi_port(port, intel_dsi->ports) 579 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 580 intel_dsi->dphy_reg); 581 582 /* shadow register inside display core */ 583 for_each_dsi_port(port, intel_dsi->ports) 584 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 585 intel_dsi->dphy_data_lane_reg); 586 587 /* shadow register inside display core */ 588 if (DISPLAY_VER(dev_priv) == 11) { 589 if (afe_clk(encoder, crtc_state) <= 800000) { 590 for_each_dsi_port(port, intel_dsi->ports) { 591 intel_de_rmw(dev_priv, DSI_TA_TIMING_PARAM(port), 592 TA_SURE_MASK, 593 TA_SURE_OVERRIDE | TA_SURE(0)); 594 } 595 } 596 } 597} 598 599static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 600{ 601 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 602 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 603 u32 tmp; 604 enum phy phy; 605 606 mutex_lock(&dev_priv->display.dpll.lock); 607 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 608 for_each_dsi_phy(phy, intel_dsi->phys) 609 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 610 611 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 612 mutex_unlock(&dev_priv->display.dpll.lock); 613} 614 615static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 616{ 617 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 618 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 619 u32 tmp; 620 enum phy phy; 621 622 mutex_lock(&dev_priv->display.dpll.lock); 623 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 624 for_each_dsi_phy(phy, intel_dsi->phys) 625 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 626 627 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 628 mutex_unlock(&dev_priv->display.dpll.lock); 629} 630 631static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 632{ 633 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 634 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 635 bool clock_enabled = false; 636 enum phy phy; 637 u32 tmp; 638 639 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 640 641 for_each_dsi_phy(phy, intel_dsi->phys) { 642 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 643 clock_enabled = true; 644 } 645 646 return clock_enabled; 647} 648 649static void gen11_dsi_map_pll(struct intel_encoder *encoder, 650 const struct intel_crtc_state *crtc_state) 651{ 652 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 653 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 654 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 655 enum phy phy; 656 u32 val; 657 658 mutex_lock(&dev_priv->display.dpll.lock); 659 660 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 661 for_each_dsi_phy(phy, intel_dsi->phys) { 662 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 663 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 664 } 665 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 666 667 for_each_dsi_phy(phy, intel_dsi->phys) { 668 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 669 } 670 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 671 672 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 673 674 mutex_unlock(&dev_priv->display.dpll.lock); 675} 676 677static void 678gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 679 const struct intel_crtc_state *pipe_config) 680{ 681 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 682 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 683 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 684 enum pipe pipe = crtc->pipe; 685 u32 tmp; 686 enum port port; 687 enum transcoder dsi_trans; 688 689 for_each_dsi_port(port, intel_dsi->ports) { 690 dsi_trans = dsi_port_to_transcoder(port); 691 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 692 693 if (intel_dsi->eotp_pkt) 694 tmp &= ~EOTP_DISABLED; 695 else 696 tmp |= EOTP_DISABLED; 697 698 /* enable link calibration if freq > 1.5Gbps */ 699 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 700 tmp &= ~LINK_CALIBRATION_MASK; 701 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 702 } 703 704 /* configure continuous clock */ 705 tmp &= ~CONTINUOUS_CLK_MASK; 706 if (intel_dsi->clock_stop) 707 tmp |= CLK_ENTER_LP_AFTER_DATA; 708 else 709 tmp |= CLK_HS_CONTINUOUS; 710 711 /* configure buffer threshold limit to minimum */ 712 tmp &= ~PIX_BUF_THRESHOLD_MASK; 713 tmp |= PIX_BUF_THRESHOLD_1_4; 714 715 /* set virtual channel to '0' */ 716 tmp &= ~PIX_VIRT_CHAN_MASK; 717 tmp |= PIX_VIRT_CHAN(0); 718 719 /* program BGR transmission */ 720 if (intel_dsi->bgr_enabled) 721 tmp |= BGR_TRANSMISSION; 722 723 /* select pixel format */ 724 tmp &= ~PIX_FMT_MASK; 725 if (pipe_config->dsc.compression_enable) { 726 tmp |= PIX_FMT_COMPRESSED; 727 } else { 728 switch (intel_dsi->pixel_format) { 729 default: 730 MISSING_CASE(intel_dsi->pixel_format); 731 fallthrough; 732 case MIPI_DSI_FMT_RGB565: 733 tmp |= PIX_FMT_RGB565; 734 break; 735 case MIPI_DSI_FMT_RGB666_PACKED: 736 tmp |= PIX_FMT_RGB666_PACKED; 737 break; 738 case MIPI_DSI_FMT_RGB666: 739 tmp |= PIX_FMT_RGB666_LOOSE; 740 break; 741 case MIPI_DSI_FMT_RGB888: 742 tmp |= PIX_FMT_RGB888; 743 break; 744 } 745 } 746 747 if (DISPLAY_VER(dev_priv) >= 12) { 748 if (is_vid_mode(intel_dsi)) 749 tmp |= BLANKING_PACKET_ENABLE; 750 } 751 752 /* program DSI operation mode */ 753 if (is_vid_mode(intel_dsi)) { 754 tmp &= ~OP_MODE_MASK; 755 switch (intel_dsi->video_mode) { 756 default: 757 MISSING_CASE(intel_dsi->video_mode); 758 fallthrough; 759 case NON_BURST_SYNC_EVENTS: 760 tmp |= VIDEO_MODE_SYNC_EVENT; 761 break; 762 case NON_BURST_SYNC_PULSE: 763 tmp |= VIDEO_MODE_SYNC_PULSE; 764 break; 765 } 766 } else { 767 /* 768 * FIXME: Retrieve this info from VBT. 769 * As per the spec when dsi transcoder is operating 770 * in TE GATE mode, TE comes from GPIO 771 * which is UTIL PIN for DSI 0. 772 * Also this GPIO would not be used for other 773 * purposes is an assumption. 774 */ 775 tmp &= ~OP_MODE_MASK; 776 tmp |= CMD_MODE_TE_GATE; 777 tmp |= TE_SOURCE_GPIO; 778 } 779 780 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 781 } 782 783 /* enable port sync mode if dual link */ 784 if (intel_dsi->dual_link) { 785 for_each_dsi_port(port, intel_dsi->ports) { 786 dsi_trans = dsi_port_to_transcoder(port); 787 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans), 788 0, PORT_SYNC_MODE_ENABLE); 789 } 790 791 /* configure stream splitting */ 792 configure_dual_link_mode(encoder, pipe_config); 793 } 794 795 for_each_dsi_port(port, intel_dsi->ports) { 796 dsi_trans = dsi_port_to_transcoder(port); 797 798 /* select data lane width */ 799 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 800 tmp &= ~DDI_PORT_WIDTH_MASK; 801 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 802 803 /* select input pipe */ 804 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 805 switch (pipe) { 806 default: 807 MISSING_CASE(pipe); 808 fallthrough; 809 case PIPE_A: 810 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 811 break; 812 case PIPE_B: 813 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 814 break; 815 case PIPE_C: 816 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 817 break; 818 case PIPE_D: 819 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 820 break; 821 } 822 823 /* enable DDI buffer */ 824 tmp |= TRANS_DDI_FUNC_ENABLE; 825 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 826 } 827 828 /* wait for link ready */ 829 for_each_dsi_port(port, intel_dsi->ports) { 830 dsi_trans = dsi_port_to_transcoder(port); 831 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 832 LINK_READY), 2500)) 833 drm_err(&dev_priv->drm, "DSI link not ready\n"); 834 } 835} 836 837static void 838gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 839 const struct intel_crtc_state *crtc_state) 840{ 841 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 842 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 843 const struct drm_display_mode *adjusted_mode = 844 &crtc_state->hw.adjusted_mode; 845 enum port port; 846 enum transcoder dsi_trans; 847 /* horizontal timings */ 848 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 849 u16 hback_porch; 850 /* vertical timings */ 851 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 852 int mul = 1, div = 1; 853 854 /* 855 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 856 * for slower link speed if DSC is enabled. 857 * 858 * The compression frequency ratio is the ratio between compressed and 859 * non-compressed link speeds, and simplifies down to the ratio between 860 * compressed and non-compressed bpp. 861 */ 862 if (crtc_state->dsc.compression_enable) { 863 mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); 864 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 865 } 866 867 hactive = adjusted_mode->crtc_hdisplay; 868 869 if (is_vid_mode(intel_dsi)) 870 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 871 else 872 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 873 874 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 875 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 876 hsync_size = hsync_end - hsync_start; 877 hback_porch = (adjusted_mode->crtc_htotal - 878 adjusted_mode->crtc_hsync_end); 879 vactive = adjusted_mode->crtc_vdisplay; 880 881 if (is_vid_mode(intel_dsi)) { 882 vtotal = adjusted_mode->crtc_vtotal; 883 } else { 884 int bpp, line_time_us, byte_clk_period_ns; 885 886 if (crtc_state->dsc.compression_enable) 887 bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); 888 else 889 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 890 891 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 892 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 893 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 894 } 895 vsync_start = adjusted_mode->crtc_vsync_start; 896 vsync_end = adjusted_mode->crtc_vsync_end; 897 vsync_shift = hsync_start - htotal / 2; 898 899 if (intel_dsi->dual_link) { 900 hactive /= 2; 901 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 902 hactive += intel_dsi->pixel_overlap; 903 htotal /= 2; 904 } 905 906 /* minimum hactive as per bspec: 256 pixels */ 907 if (adjusted_mode->crtc_hdisplay < 256) 908 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 909 910 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 911 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 912 drm_err(&dev_priv->drm, 913 "hactive pixels are not multiple of 4\n"); 914 915 /* program TRANS_HTOTAL register */ 916 for_each_dsi_port(port, intel_dsi->ports) { 917 dsi_trans = dsi_port_to_transcoder(port); 918 intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans), 919 HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); 920 } 921 922 /* TRANS_HSYNC register to be programmed only for video mode */ 923 if (is_vid_mode(intel_dsi)) { 924 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { 925 /* BSPEC: hsync size should be atleast 16 pixels */ 926 if (hsync_size < 16) 927 drm_err(&dev_priv->drm, 928 "hsync size < 16 pixels\n"); 929 } 930 931 if (hback_porch < 16) 932 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 933 934 if (intel_dsi->dual_link) { 935 hsync_start /= 2; 936 hsync_end /= 2; 937 } 938 939 for_each_dsi_port(port, intel_dsi->ports) { 940 dsi_trans = dsi_port_to_transcoder(port); 941 intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans), 942 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); 943 } 944 } 945 946 /* program TRANS_VTOTAL register */ 947 for_each_dsi_port(port, intel_dsi->ports) { 948 dsi_trans = dsi_port_to_transcoder(port); 949 /* 950 * FIXME: Programing this by assuming progressive mode, since 951 * non-interlaced info from VBT is not saved inside 952 * struct drm_display_mode. 953 * For interlace mode: program required pixel minus 2 954 */ 955 intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans), 956 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); 957 } 958 959 if (vsync_end < vsync_start || vsync_end > vtotal) 960 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 961 962 if (vsync_start < vactive) 963 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 964 965 /* program TRANS_VSYNC register for video mode only */ 966 if (is_vid_mode(intel_dsi)) { 967 for_each_dsi_port(port, intel_dsi->ports) { 968 dsi_trans = dsi_port_to_transcoder(port); 969 intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans), 970 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); 971 } 972 } 973 974 /* 975 * FIXME: It has to be programmed only for video modes and interlaced 976 * modes. Put the check condition here once interlaced 977 * info available as described above. 978 * program TRANS_VSYNCSHIFT register 979 */ 980 if (is_vid_mode(intel_dsi)) { 981 for_each_dsi_port(port, intel_dsi->ports) { 982 dsi_trans = dsi_port_to_transcoder(port); 983 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(dsi_trans), 984 vsync_shift); 985 } 986 } 987 988 /* 989 * program TRANS_VBLANK register, should be same as vtotal programmed 990 * 991 * FIXME get rid of these local hacks and do it right, 992 * this will not handle eg. delayed vblank correctly. 993 */ 994 if (DISPLAY_VER(dev_priv) >= 12) { 995 for_each_dsi_port(port, intel_dsi->ports) { 996 dsi_trans = dsi_port_to_transcoder(port); 997 intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans), 998 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); 999 } 1000 } 1001} 1002 1003static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1004{ 1005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1006 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1007 enum port port; 1008 enum transcoder dsi_trans; 1009 1010 for_each_dsi_port(port, intel_dsi->ports) { 1011 dsi_trans = dsi_port_to_transcoder(port); 1012 intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), 0, TRANSCONF_ENABLE); 1013 1014 /* wait for transcoder to be enabled */ 1015 if (intel_de_wait_for_set(dev_priv, TRANSCONF(dsi_trans), 1016 TRANSCONF_STATE_ENABLE, 10)) 1017 drm_err(&dev_priv->drm, 1018 "DSI transcoder not enabled\n"); 1019 } 1020} 1021 1022static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1023 const struct intel_crtc_state *crtc_state) 1024{ 1025 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1026 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1027 enum port port; 1028 enum transcoder dsi_trans; 1029 u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1030 1031 /* 1032 * escape clock count calculation: 1033 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1034 * UI (nsec) = (10^6)/Bitrate 1035 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1036 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1037 */ 1038 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1039 mul = 8 * 1000000; 1040 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1041 divisor); 1042 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1043 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1044 1045 for_each_dsi_port(port, intel_dsi->ports) { 1046 dsi_trans = dsi_port_to_transcoder(port); 1047 1048 /* program hst_tx_timeout */ 1049 intel_de_rmw(dev_priv, DSI_HSTX_TO(dsi_trans), 1050 HSTX_TIMEOUT_VALUE_MASK, 1051 HSTX_TIMEOUT_VALUE(hs_tx_timeout)); 1052 1053 /* FIXME: DSI_CALIB_TO */ 1054 1055 /* program lp_rx_host timeout */ 1056 intel_de_rmw(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), 1057 LPRX_TIMEOUT_VALUE_MASK, 1058 LPRX_TIMEOUT_VALUE(lp_rx_timeout)); 1059 1060 /* FIXME: DSI_PWAIT_TO */ 1061 1062 /* program turn around timeout */ 1063 intel_de_rmw(dev_priv, DSI_TA_TO(dsi_trans), 1064 TA_TIMEOUT_VALUE_MASK, 1065 TA_TIMEOUT_VALUE(ta_timeout)); 1066 } 1067} 1068 1069static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1070 bool enable) 1071{ 1072 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1073 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1074 u32 tmp; 1075 1076 /* 1077 * used as TE i/p for DSI0, 1078 * for dual link/DSI1 TE is from slave DSI1 1079 * through GPIO. 1080 */ 1081 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1082 return; 1083 1084 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); 1085 1086 if (enable) { 1087 tmp |= UTIL_PIN_DIRECTION_INPUT; 1088 tmp |= UTIL_PIN_ENABLE; 1089 } else { 1090 tmp &= ~UTIL_PIN_ENABLE; 1091 } 1092 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); 1093} 1094 1095static void 1096gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1097 const struct intel_crtc_state *crtc_state) 1098{ 1099 /* step 4a: power up all lanes of the DDI used by DSI */ 1100 gen11_dsi_power_up_lanes(encoder); 1101 1102 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1103 gen11_dsi_config_phy_lanes_sequence(encoder); 1104 1105 /* step 4c: configure voltage swing and skew */ 1106 gen11_dsi_voltage_swing_program_seq(encoder); 1107 1108 /* setup D-PHY timings */ 1109 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1110 1111 /* enable DDI buffer */ 1112 gen11_dsi_enable_ddi_buffer(encoder); 1113 1114 gen11_dsi_gate_clocks(encoder); 1115 1116 gen11_dsi_setup_timings(encoder, crtc_state); 1117 1118 /* Since transcoder is configured to take events from GPIO */ 1119 gen11_dsi_config_util_pin(encoder, true); 1120 1121 /* step 4h: setup DSI protocol timeouts */ 1122 gen11_dsi_setup_timeouts(encoder, crtc_state); 1123 1124 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1125 gen11_dsi_configure_transcoder(encoder, crtc_state); 1126} 1127 1128static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1129{ 1130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1131 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1132 struct mipi_dsi_device *dsi; 1133 enum port port; 1134 enum transcoder dsi_trans; 1135 u32 tmp; 1136 int ret; 1137 1138 /* set maximum return packet size */ 1139 for_each_dsi_port(port, intel_dsi->ports) { 1140 dsi_trans = dsi_port_to_transcoder(port); 1141 1142 /* 1143 * FIXME: This uses the number of DW's currently in the payload 1144 * receive queue. This is probably not what we want here. 1145 */ 1146 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1147 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1148 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1149 tmp = tmp * 4; 1150 dsi = intel_dsi->dsi_hosts[port]->device; 1151 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1152 if (ret < 0) 1153 drm_err(&dev_priv->drm, 1154 "error setting max return pkt size%d\n", tmp); 1155 } 1156 1157 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1158 1159 /* ensure all panel commands dispatched before enabling transcoder */ 1160 wait_for_cmds_dispatched_to_panel(encoder); 1161} 1162 1163static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1164 struct intel_encoder *encoder, 1165 const struct intel_crtc_state *crtc_state, 1166 const struct drm_connector_state *conn_state) 1167{ 1168 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1169 1170 intel_dsi_wait_panel_power_cycle(intel_dsi); 1171 1172 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1173 msleep(intel_dsi->panel_on_delay); 1174 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1175 1176 /* step2: enable IO power */ 1177 gen11_dsi_enable_io_power(encoder); 1178 1179 /* step3: enable DSI PLL */ 1180 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1181} 1182 1183static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1184 struct intel_encoder *encoder, 1185 const struct intel_crtc_state *pipe_config, 1186 const struct drm_connector_state *conn_state) 1187{ 1188 /* step3b */ 1189 gen11_dsi_map_pll(encoder, pipe_config); 1190 1191 /* step4: enable DSI port and DPHY */ 1192 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1193 1194 /* step5: program and powerup panel */ 1195 gen11_dsi_powerup_panel(encoder); 1196 1197 intel_dsc_dsi_pps_write(encoder, pipe_config); 1198 1199 /* step6c: configure transcoder timings */ 1200 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1201} 1202 1203/* 1204 * Wa_1409054076:icl,jsl,ehl 1205 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1206 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1207 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1208 * it set while DSI is enabled on pipe B 1209 */ 1210static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1211 enum pipe pipe, bool enable) 1212{ 1213 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1214 1215 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) 1216 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1217 IGNORE_KVMR_PIPE_A, 1218 enable ? IGNORE_KVMR_PIPE_A : 0); 1219} 1220 1221/* 1222 * Wa_16012360555:adl-p 1223 * SW will have to program the "LP to HS Wakeup Guardband" 1224 * to account for the repeaters on the HS Request/Ready 1225 * PPI signaling between the Display engine and the DPHY. 1226 */ 1227static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1228{ 1229 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1230 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1231 enum port port; 1232 1233 if (DISPLAY_VER(i915) == 13) { 1234 for_each_dsi_port(port, intel_dsi->ports) 1235 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), 1236 TGL_DSI_CHKN_LSHS_GB_MASK, 1237 TGL_DSI_CHKN_LSHS_GB(4)); 1238 } 1239} 1240 1241static void gen11_dsi_enable(struct intel_atomic_state *state, 1242 struct intel_encoder *encoder, 1243 const struct intel_crtc_state *crtc_state, 1244 const struct drm_connector_state *conn_state) 1245{ 1246 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1247 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1248 1249 /* Wa_1409054076:icl,jsl,ehl */ 1250 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1251 1252 /* Wa_16012360555:adl-p */ 1253 adlp_set_lp_hs_wakeup_gb(encoder); 1254 1255 /* step6d: enable dsi transcoder */ 1256 gen11_dsi_enable_transcoder(encoder); 1257 1258 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1259 1260 /* step7: enable backlight */ 1261 intel_backlight_enable(crtc_state, conn_state); 1262 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1263 1264 intel_crtc_vblank_on(crtc_state); 1265} 1266 1267static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1268{ 1269 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1270 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1271 enum port port; 1272 enum transcoder dsi_trans; 1273 1274 for_each_dsi_port(port, intel_dsi->ports) { 1275 dsi_trans = dsi_port_to_transcoder(port); 1276 1277 /* disable transcoder */ 1278 intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), TRANSCONF_ENABLE, 0); 1279 1280 /* wait for transcoder to be disabled */ 1281 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dsi_trans), 1282 TRANSCONF_STATE_ENABLE, 50)) 1283 drm_err(&dev_priv->drm, 1284 "DSI trancoder not disabled\n"); 1285 } 1286} 1287 1288static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1289{ 1290 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1291 1292 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1293 1294 /* ensure cmds dispatched to panel */ 1295 wait_for_cmds_dispatched_to_panel(encoder); 1296} 1297 1298static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1299{ 1300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1301 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1302 enum port port; 1303 enum transcoder dsi_trans; 1304 u32 tmp; 1305 1306 /* disable periodic update mode */ 1307 if (is_cmd_mode(intel_dsi)) { 1308 for_each_dsi_port(port, intel_dsi->ports) 1309 intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 1310 DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0); 1311 } 1312 1313 /* put dsi link in ULPS */ 1314 for_each_dsi_port(port, intel_dsi->ports) { 1315 dsi_trans = dsi_port_to_transcoder(port); 1316 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1317 tmp |= LINK_ENTER_ULPS; 1318 tmp &= ~LINK_ULPS_TYPE_LP11; 1319 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1320 1321 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1322 LINK_IN_ULPS), 1323 10)) 1324 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1325 } 1326 1327 /* disable ddi function */ 1328 for_each_dsi_port(port, intel_dsi->ports) { 1329 dsi_trans = dsi_port_to_transcoder(port); 1330 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), 1331 TRANS_DDI_FUNC_ENABLE, 0); 1332 } 1333 1334 /* disable port sync mode if dual link */ 1335 if (intel_dsi->dual_link) { 1336 for_each_dsi_port(port, intel_dsi->ports) { 1337 dsi_trans = dsi_port_to_transcoder(port); 1338 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans), 1339 PORT_SYNC_MODE_ENABLE, 0); 1340 } 1341 } 1342} 1343 1344static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1345{ 1346 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1347 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1348 enum port port; 1349 1350 gen11_dsi_ungate_clocks(encoder); 1351 for_each_dsi_port(port, intel_dsi->ports) { 1352 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 1353 1354 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1355 DDI_BUF_IS_IDLE), 1356 8)) 1357 drm_err(&dev_priv->drm, 1358 "DDI port:%c buffer not idle\n", 1359 port_name(port)); 1360 } 1361 gen11_dsi_gate_clocks(encoder); 1362} 1363 1364static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1365{ 1366 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1367 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1368 enum port port; 1369 1370 for_each_dsi_port(port, intel_dsi->ports) { 1371 intel_wakeref_t wakeref; 1372 1373 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1374 intel_display_power_put(dev_priv, 1375 port == PORT_A ? 1376 POWER_DOMAIN_PORT_DDI_IO_A : 1377 POWER_DOMAIN_PORT_DDI_IO_B, 1378 wakeref); 1379 } 1380 1381 /* set mode to DDI */ 1382 for_each_dsi_port(port, intel_dsi->ports) 1383 intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port), 1384 COMBO_PHY_MODE_DSI, 0); 1385} 1386 1387static void gen11_dsi_disable(struct intel_atomic_state *state, 1388 struct intel_encoder *encoder, 1389 const struct intel_crtc_state *old_crtc_state, 1390 const struct drm_connector_state *old_conn_state) 1391{ 1392 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1393 1394 /* step1: turn off backlight */ 1395 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1396 intel_backlight_disable(old_conn_state); 1397} 1398 1399static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1400 struct intel_encoder *encoder, 1401 const struct intel_crtc_state *old_crtc_state, 1402 const struct drm_connector_state *old_conn_state) 1403{ 1404 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1405 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1406 1407 intel_crtc_vblank_off(old_crtc_state); 1408 1409 /* step2d,e: disable transcoder and wait */ 1410 gen11_dsi_disable_transcoder(encoder); 1411 1412 /* Wa_1409054076:icl,jsl,ehl */ 1413 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1414 1415 /* step2f,g: powerdown panel */ 1416 gen11_dsi_powerdown_panel(encoder); 1417 1418 /* step2h,i,j: deconfig trancoder */ 1419 gen11_dsi_deconfigure_trancoder(encoder); 1420 1421 intel_dsc_disable(old_crtc_state); 1422 skl_scaler_disable(old_crtc_state); 1423 1424 /* step3: disable port */ 1425 gen11_dsi_disable_port(encoder); 1426 1427 gen11_dsi_config_util_pin(encoder, false); 1428 1429 /* step4: disable IO power */ 1430 gen11_dsi_disable_io_power(encoder); 1431 1432 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1433 1434 msleep(intel_dsi->panel_off_delay); 1435 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1436 1437 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1438} 1439 1440static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1441 struct drm_display_mode *mode) 1442{ 1443 struct drm_i915_private *i915 = to_i915(connector->dev); 1444 enum drm_mode_status status; 1445 1446 status = intel_cpu_transcoder_mode_valid(i915, mode); 1447 if (status != MODE_OK) 1448 return status; 1449 1450 /* FIXME: DSC? */ 1451 return intel_dsi_mode_valid(connector, mode); 1452} 1453 1454static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1455 struct intel_crtc_state *pipe_config) 1456{ 1457 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1458 struct drm_display_mode *adjusted_mode = 1459 &pipe_config->hw.adjusted_mode; 1460 1461 if (pipe_config->dsc.compressed_bpp_x16) { 1462 int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16); 1463 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1464 1465 adjusted_mode->crtc_htotal = 1466 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1467 adjusted_mode->crtc_hsync_start = 1468 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1469 adjusted_mode->crtc_hsync_end = 1470 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1471 } 1472 1473 if (intel_dsi->dual_link) { 1474 adjusted_mode->crtc_hdisplay *= 2; 1475 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1476 adjusted_mode->crtc_hdisplay -= 1477 intel_dsi->pixel_overlap; 1478 adjusted_mode->crtc_htotal *= 2; 1479 } 1480 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1481 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1482 1483 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1484 if (intel_dsi->dual_link) { 1485 adjusted_mode->crtc_hsync_start *= 2; 1486 adjusted_mode->crtc_hsync_end *= 2; 1487 } 1488 } 1489 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1490 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1491} 1492 1493static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1494{ 1495 struct drm_device *dev = intel_dsi->base.base.dev; 1496 struct drm_i915_private *dev_priv = to_i915(dev); 1497 enum transcoder dsi_trans; 1498 u32 val; 1499 1500 if (intel_dsi->ports == BIT(PORT_B)) 1501 dsi_trans = TRANSCODER_DSI_1; 1502 else 1503 dsi_trans = TRANSCODER_DSI_0; 1504 1505 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 1506 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1507} 1508 1509static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1510 struct intel_crtc_state *pipe_config) 1511{ 1512 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1513 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1514 I915_MODE_FLAG_DSI_USE_TE0; 1515 else if (intel_dsi->ports == BIT(PORT_B)) 1516 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1517 else 1518 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1519} 1520 1521static void gen11_dsi_get_config(struct intel_encoder *encoder, 1522 struct intel_crtc_state *pipe_config) 1523{ 1524 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1525 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1526 1527 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1528 1529 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1530 if (intel_dsi->dual_link) 1531 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1532 1533 gen11_dsi_get_timings(encoder, pipe_config); 1534 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1535 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1536 1537 /* Get the details on which TE should be enabled */ 1538 if (is_cmd_mode(intel_dsi)) 1539 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1540 1541 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1542 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1543} 1544 1545static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1546 const struct intel_crtc_state *crtc_state) 1547{ 1548 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1549 struct intel_crtc *intel_crtc; 1550 enum pipe pipe; 1551 1552 if (!crtc_state) 1553 return; 1554 1555 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1556 pipe = intel_crtc->pipe; 1557 1558 /* wa verify 1409054076:icl,jsl,ehl */ 1559 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && 1560 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1561 drm_dbg_kms(&dev_priv->drm, 1562 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1563 encoder->base.base.id, 1564 encoder->base.name); 1565} 1566 1567static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1568 struct intel_crtc_state *crtc_state) 1569{ 1570 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1571 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1572 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; 1573 bool use_dsc; 1574 int ret; 1575 1576 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1577 if (!use_dsc) 1578 return 0; 1579 1580 if (crtc_state->pipe_bpp < 8 * 3) 1581 return -EINVAL; 1582 1583 /* FIXME: split only when necessary */ 1584 if (crtc_state->dsc.slice_count > 1) 1585 crtc_state->dsc.dsc_split = true; 1586 1587 /* FIXME: initialize from VBT */ 1588 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1589 1590 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1591 1592 ret = intel_dsc_compute_params(crtc_state); 1593 if (ret) 1594 return ret; 1595 1596 /* DSI specific sanity checks on the common code */ 1597 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1598 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1599 drm_WARN_ON(&dev_priv->drm, 1600 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1601 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1602 drm_WARN_ON(&dev_priv->drm, 1603 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1604 1605 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1606 if (ret) 1607 return ret; 1608 1609 crtc_state->dsc.compression_enable = true; 1610 1611 return 0; 1612} 1613 1614static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1615 struct intel_crtc_state *pipe_config, 1616 struct drm_connector_state *conn_state) 1617{ 1618 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1619 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1620 base); 1621 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1622 struct drm_display_mode *adjusted_mode = 1623 &pipe_config->hw.adjusted_mode; 1624 int ret; 1625 1626 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1627 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1628 1629 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1630 if (ret) 1631 return ret; 1632 1633 ret = intel_panel_fitting(pipe_config, conn_state); 1634 if (ret) 1635 return ret; 1636 1637 adjusted_mode->flags = 0; 1638 1639 /* Dual link goes to trancoder DSI'0' */ 1640 if (intel_dsi->ports == BIT(PORT_B)) 1641 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1642 else 1643 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1644 1645 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1646 pipe_config->pipe_bpp = 24; 1647 else 1648 pipe_config->pipe_bpp = 18; 1649 1650 pipe_config->clock_set = true; 1651 1652 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1653 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); 1654 1655 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1656 1657 /* 1658 * In case of TE GATE cmd mode, we 1659 * receive TE from the slave if 1660 * dual link is enabled 1661 */ 1662 if (is_cmd_mode(intel_dsi)) 1663 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1664 1665 return 0; 1666} 1667 1668static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1669 struct intel_crtc_state *crtc_state) 1670{ 1671 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1672 1673 get_dsi_io_power_domains(i915, 1674 enc_to_intel_dsi(encoder)); 1675} 1676 1677static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1678 enum pipe *pipe) 1679{ 1680 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1681 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1682 enum transcoder dsi_trans; 1683 intel_wakeref_t wakeref; 1684 enum port port; 1685 bool ret = false; 1686 u32 tmp; 1687 1688 wakeref = intel_display_power_get_if_enabled(dev_priv, 1689 encoder->power_domain); 1690 if (!wakeref) 1691 return false; 1692 1693 for_each_dsi_port(port, intel_dsi->ports) { 1694 dsi_trans = dsi_port_to_transcoder(port); 1695 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1696 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1697 case TRANS_DDI_EDP_INPUT_A_ON: 1698 *pipe = PIPE_A; 1699 break; 1700 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1701 *pipe = PIPE_B; 1702 break; 1703 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1704 *pipe = PIPE_C; 1705 break; 1706 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1707 *pipe = PIPE_D; 1708 break; 1709 default: 1710 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1711 goto out; 1712 } 1713 1714 tmp = intel_de_read(dev_priv, TRANSCONF(dsi_trans)); 1715 ret = tmp & TRANSCONF_ENABLE; 1716 } 1717out: 1718 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1719 return ret; 1720} 1721 1722static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1723 struct intel_crtc_state *crtc_state) 1724{ 1725 if (crtc_state->dsc.compression_enable) { 1726 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1727 crtc_state->uapi.mode_changed = true; 1728 1729 return false; 1730 } 1731 1732 return true; 1733} 1734 1735static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1736{ 1737 intel_encoder_destroy(encoder); 1738} 1739 1740static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1741 .destroy = gen11_dsi_encoder_destroy, 1742}; 1743 1744static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1745 .detect = intel_panel_detect, 1746 .late_register = intel_connector_register, 1747 .early_unregister = intel_connector_unregister, 1748 .destroy = intel_connector_destroy, 1749 .fill_modes = drm_helper_probe_single_connector_modes, 1750 .atomic_get_property = intel_digital_connector_atomic_get_property, 1751 .atomic_set_property = intel_digital_connector_atomic_set_property, 1752 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1753 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1754}; 1755 1756static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1757 .get_modes = intel_dsi_get_modes, 1758 .mode_valid = gen11_dsi_mode_valid, 1759 .atomic_check = intel_digital_connector_atomic_check, 1760}; 1761 1762static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1763 struct mipi_dsi_device *dsi) 1764{ 1765 return 0; 1766} 1767 1768static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1769 struct mipi_dsi_device *dsi) 1770{ 1771 return 0; 1772} 1773 1774static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1775 const struct mipi_dsi_msg *msg) 1776{ 1777 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1778 struct mipi_dsi_packet dsi_pkt; 1779 ssize_t ret; 1780 bool enable_lpdt = false; 1781 1782 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1783 if (ret < 0) 1784 return ret; 1785 1786 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1787 enable_lpdt = true; 1788 1789 /* only long packet contains payload */ 1790 if (mipi_dsi_packet_format_is_long(msg->type)) { 1791 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1792 if (ret < 0) 1793 return ret; 1794 } 1795 1796 /* send packet header */ 1797 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1798 if (ret < 0) 1799 return ret; 1800 1801 //TODO: add payload receive code if needed 1802 1803 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1804 1805 return ret; 1806} 1807 1808static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1809 .attach = gen11_dsi_host_attach, 1810 .detach = gen11_dsi_host_detach, 1811 .transfer = gen11_dsi_host_transfer, 1812}; 1813 1814#define ICL_PREPARE_CNT_MAX 0x7 1815#define ICL_CLK_ZERO_CNT_MAX 0xf 1816#define ICL_TRAIL_CNT_MAX 0x7 1817#define ICL_TCLK_PRE_CNT_MAX 0x3 1818#define ICL_TCLK_POST_CNT_MAX 0x7 1819#define ICL_HS_ZERO_CNT_MAX 0xf 1820#define ICL_EXIT_ZERO_CNT_MAX 0x7 1821 1822static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1823{ 1824 struct drm_device *dev = intel_dsi->base.base.dev; 1825 struct drm_i915_private *dev_priv = to_i915(dev); 1826 struct intel_connector *connector = intel_dsi->attached_connector; 1827 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1828 u32 tlpx_ns; 1829 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1830 u32 ths_prepare_ns, tclk_trail_ns; 1831 u32 hs_zero_cnt; 1832 u32 tclk_pre_cnt; 1833 1834 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1835 1836 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1837 ths_prepare_ns = max(mipi_config->ths_prepare, 1838 mipi_config->tclk_prepare); 1839 1840 /* 1841 * prepare cnt in escape clocks 1842 * this field represents a hexadecimal value with a precision 1843 * of 1.2 ��� i.e. the most significant bit is the integer 1844 * and the least significant 2 bits are fraction bits. 1845 * so, the field can represent a range of 0.25 to 1.75 1846 */ 1847 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1848 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1849 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1850 prepare_cnt); 1851 prepare_cnt = ICL_PREPARE_CNT_MAX; 1852 } 1853 1854 /* clk zero count in escape clocks */ 1855 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1856 ths_prepare_ns, tlpx_ns); 1857 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1858 drm_dbg_kms(&dev_priv->drm, 1859 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1860 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1861 } 1862 1863 /* trail cnt in escape clocks*/ 1864 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1865 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1866 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1867 trail_cnt); 1868 trail_cnt = ICL_TRAIL_CNT_MAX; 1869 } 1870 1871 /* tclk pre count in escape clocks */ 1872 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1873 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1874 drm_dbg_kms(&dev_priv->drm, 1875 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1876 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1877 } 1878 1879 /* hs zero cnt in escape clocks */ 1880 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1881 ths_prepare_ns, tlpx_ns); 1882 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1883 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1884 hs_zero_cnt); 1885 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1886 } 1887 1888 /* hs exit zero cnt in escape clocks */ 1889 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1890 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1891 drm_dbg_kms(&dev_priv->drm, 1892 "exit_zero_cnt out of range (%d)\n", 1893 exit_zero_cnt); 1894 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1895 } 1896 1897 /* clock lane dphy timings */ 1898 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1899 CLK_PREPARE(prepare_cnt) | 1900 CLK_ZERO_OVERRIDE | 1901 CLK_ZERO(clk_zero_cnt) | 1902 CLK_PRE_OVERRIDE | 1903 CLK_PRE(tclk_pre_cnt) | 1904 CLK_TRAIL_OVERRIDE | 1905 CLK_TRAIL(trail_cnt)); 1906 1907 /* data lanes dphy timings */ 1908 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1909 HS_PREPARE(prepare_cnt) | 1910 HS_ZERO_OVERRIDE | 1911 HS_ZERO(hs_zero_cnt) | 1912 HS_TRAIL_OVERRIDE | 1913 HS_TRAIL(trail_cnt) | 1914 HS_EXIT_OVERRIDE | 1915 HS_EXIT(exit_zero_cnt)); 1916 1917 intel_dsi_log_params(intel_dsi); 1918} 1919 1920static void icl_dsi_add_properties(struct intel_connector *connector) 1921{ 1922 const struct drm_display_mode *fixed_mode = 1923 intel_panel_preferred_fixed_mode(connector); 1924 1925 intel_attach_scaling_mode_property(&connector->base); 1926 1927 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1928 intel_dsi_get_panel_orientation(connector), 1929 fixed_mode->hdisplay, 1930 fixed_mode->vdisplay); 1931} 1932 1933void icl_dsi_init(struct drm_i915_private *dev_priv, 1934 const struct intel_bios_encoder_data *devdata) 1935{ 1936 struct intel_dsi *intel_dsi; 1937 struct intel_encoder *encoder; 1938 struct intel_connector *intel_connector; 1939 struct drm_connector *connector; 1940 enum port port; 1941 1942 port = intel_bios_encoder_port(devdata); 1943 if (port == PORT_NONE) 1944 return; 1945 1946 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1947 if (!intel_dsi) 1948 return; 1949 1950 intel_connector = intel_connector_alloc(); 1951 if (!intel_connector) { 1952 kfree(intel_dsi); 1953 return; 1954 } 1955 1956 encoder = &intel_dsi->base; 1957 intel_dsi->attached_connector = intel_connector; 1958 connector = &intel_connector->base; 1959 1960 encoder->devdata = devdata; 1961 1962 /* register DSI encoder with DRM subsystem */ 1963 drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs, 1964 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1965 1966 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 1967 encoder->pre_enable = gen11_dsi_pre_enable; 1968 encoder->enable = gen11_dsi_enable; 1969 encoder->disable = gen11_dsi_disable; 1970 encoder->post_disable = gen11_dsi_post_disable; 1971 encoder->port = port; 1972 encoder->get_config = gen11_dsi_get_config; 1973 encoder->sync_state = gen11_dsi_sync_state; 1974 encoder->update_pipe = intel_backlight_update; 1975 encoder->compute_config = gen11_dsi_compute_config; 1976 encoder->get_hw_state = gen11_dsi_get_hw_state; 1977 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 1978 encoder->type = INTEL_OUTPUT_DSI; 1979 encoder->cloneable = 0; 1980 encoder->pipe_mask = ~0; 1981 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1982 encoder->get_power_domains = gen11_dsi_get_power_domains; 1983 encoder->disable_clock = gen11_dsi_gate_clocks; 1984 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 1985 encoder->shutdown = intel_dsi_shutdown; 1986 1987 /* register DSI connector with DRM subsystem */ 1988 drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs, 1989 DRM_MODE_CONNECTOR_DSI); 1990 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 1991 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1992 intel_connector->get_hw_state = intel_connector_get_hw_state; 1993 1994 /* attach connector to encoder */ 1995 intel_connector_attach_encoder(intel_connector, encoder); 1996 1997 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1998 1999 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, NULL); 2000 2001 mutex_lock(&dev_priv->drm.mode_config.mutex); 2002 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 2003 mutex_unlock(&dev_priv->drm.mode_config.mutex); 2004 2005 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2006 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 2007 goto err; 2008 } 2009 2010 intel_panel_init(intel_connector, NULL); 2011 2012 intel_backlight_setup(intel_connector, INVALID_PIPE); 2013 2014 if (intel_connector->panel.vbt.dsi.config->dual_link) 2015 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2016 else 2017 intel_dsi->ports = BIT(port); 2018 2019 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 2020 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 2021 2022 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 2023 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 2024 2025 for_each_dsi_port(port, intel_dsi->ports) { 2026 struct intel_dsi_host *host; 2027 2028 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2029 if (!host) 2030 goto err; 2031 2032 intel_dsi->dsi_hosts[port] = host; 2033 } 2034 2035 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2036 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 2037 goto err; 2038 } 2039 2040 icl_dphy_param_init(intel_dsi); 2041 2042 icl_dsi_add_properties(intel_connector); 2043 return; 2044 2045err: 2046 drm_connector_cleanup(connector); 2047 drm_encoder_cleanup(&encoder->base); 2048 kfree(intel_dsi); 2049 kfree(intel_connector); 2050} 2051