Lines Matching refs:intel_de_read
77 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
86 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
216 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
258 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
265 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
286 u32 val = intel_de_read(dev_priv, reg);
330 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
339 u32 val = intel_de_read(dev_priv, reg);
361 u32 val = intel_de_read(dev_priv, reg);
408 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
416 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
435 u32 val = intel_de_read(dev_priv, reg);
480 *data++ = intel_de_read(dev_priv,
489 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
513 u32 val = intel_de_read(dev_priv, ctl_reg);
555 *data++ = intel_de_read(dev_priv,
563 u32 val = intel_de_read(dev_priv,
871 u32 val = intel_de_read(dev_priv, reg);
1021 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1056 u32 val = intel_de_read(dev_priv, reg);
1114 u32 val = intel_de_read(dev_priv, reg);
1163 u32 val = intel_de_read(dev_priv, reg);
1219 u32 val = intel_de_read(dev_priv, reg);
1477 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1555 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1559 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,