Searched refs:rt2x00_set_field32 (Results 1 - 9 of 9) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/wireless/rt2x00/
H A Drt2400pci.c71 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
72 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
73 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
74 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
99 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
100 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
101 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
126 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
127 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
128 rt2x00_set_field32(
[all...]
H A Drt61pci.c80 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
81 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
82 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
83 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
108 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
109 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
110 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
135 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
136 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
137 rt2x00_set_field32(
[all...]
H A Drt2800lib.c99 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
156 rt2x00_set_field32(
[all...]
H A Drt2500pci.c71 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
72 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
73 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
74 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
99 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
100 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
101 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
126 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
127 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
128 rt2x00_set_field32(
[all...]
H A Drt2800pci.c121 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
122 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
123 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
125 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
205 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
250 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
254 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
258 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
305 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
306 rt2x00_set_field32(
[all...]
H A Drt73usb.c79 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
80 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
81 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
82 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
107 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
108 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
109 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
134 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
139 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
142 rt2x00_set_field32(
[all...]
H A Drt2800usb.c128 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
158 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
159 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
187 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
193 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
194 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
195 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
200 rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
201 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN, 0);
202 rt2x00_set_field32(
[all...]
H A Drt2500usb.c603 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
634 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
1054 rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, txdesc->retry_limit);
1055 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1057 rt2x00_set_field32(&word, TXD_W0_ACK,
1059 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1061 rt2x00_set_field32(&word, TXD_W0_OFDM,
1063 rt2x00_set_field32(&word, TXD_W0_NEW_SEQ,
1065 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1066 rt2x00_set_field32(
[all...]
H A Drt2x00reg.h270 #define rt2x00_set_field32(__reg, __field, __value) \ macro

Completed in 69 milliseconds