1/* 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 3 <http://rt2x00.serialmonkey.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the 17 Free Software Foundation, Inc., 18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21/* 22 Module: rt61pci 23 Abstract: rt61pci device specific routines. 24 Supported chipsets: RT2561, RT2561s, RT2661. 25 */ 26 27#include <linux/crc-itu-t.h> 28#include <linux/delay.h> 29#include <linux/etherdevice.h> 30#include <linux/init.h> 31#include <linux/kernel.h> 32#include <linux/module.h> 33#include <linux/slab.h> 34#include <linux/pci.h> 35#include <linux/eeprom_93cx6.h> 36 37#include "rt2x00.h" 38#include "rt2x00pci.h" 39#include "rt61pci.h" 40 41/* 42 * Allow hardware encryption to be disabled. 43 */ 44static int modparam_nohwcrypt = 0; 45module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 46MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 47 48/* 49 * Register access. 50 * BBP and RF register require indirect register access, 51 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this. 52 * These indirect registers work with busy bits, 53 * and we will try maximal REGISTER_BUSY_COUNT times to access 54 * the register while taking a REGISTER_BUSY_DELAY us delay 55 * between each attempt. When the busy bit is still set at that time, 56 * the access attempt is considered to have failed, 57 * and we will print an error. 58 */ 59#define WAIT_FOR_BBP(__dev, __reg) \ 60 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg)) 61#define WAIT_FOR_RF(__dev, __reg) \ 62 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg)) 63#define WAIT_FOR_MCU(__dev, __reg) \ 64 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 65 H2M_MAILBOX_CSR_OWNER, (__reg)) 66 67static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev, 68 const unsigned int word, const u8 value) 69{ 70 u32 reg; 71 72 mutex_lock(&rt2x00dev->csr_mutex); 73 74 /* 75 * Wait until the BBP becomes available, afterwards we 76 * can safely write the new data into the register. 77 */ 78 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 79 reg = 0; 80 rt2x00_set_field32(®, PHY_CSR3_VALUE, value); 81 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); 82 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); 83 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); 84 85 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg); 86 } 87 88 mutex_unlock(&rt2x00dev->csr_mutex); 89} 90 91static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, 92 const unsigned int word, u8 *value) 93{ 94 u32 reg; 95 96 mutex_lock(&rt2x00dev->csr_mutex); 97 98 /* 99 * Wait until the BBP becomes available, afterwards we 100 * can safely write the read request into the register. 101 * After the data has been written, we wait until hardware 102 * returns the correct value, if at any time the register 103 * doesn't become available in time, reg will be 0xffffffff 104 * which means we return 0xff to the caller. 105 */ 106 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 107 reg = 0; 108 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); 109 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); 110 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); 111 112 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg); 113 114 WAIT_FOR_BBP(rt2x00dev, ®); 115 } 116 117 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); 118 119 mutex_unlock(&rt2x00dev->csr_mutex); 120} 121 122static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev, 123 const unsigned int word, const u32 value) 124{ 125 u32 reg; 126 127 mutex_lock(&rt2x00dev->csr_mutex); 128 129 /* 130 * Wait until the RF becomes available, afterwards we 131 * can safely write the new data into the register. 132 */ 133 if (WAIT_FOR_RF(rt2x00dev, ®)) { 134 reg = 0; 135 rt2x00_set_field32(®, PHY_CSR4_VALUE, value); 136 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21); 137 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); 138 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); 139 140 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg); 141 rt2x00_rf_write(rt2x00dev, word, value); 142 } 143 144 mutex_unlock(&rt2x00dev->csr_mutex); 145} 146 147static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev, 148 const u8 command, const u8 token, 149 const u8 arg0, const u8 arg1) 150{ 151 u32 reg; 152 153 mutex_lock(&rt2x00dev->csr_mutex); 154 155 /* 156 * Wait until the MCU becomes available, afterwards we 157 * can safely write the new data into the register. 158 */ 159 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 160 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 161 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 162 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 163 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 164 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); 165 166 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®); 167 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 168 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1); 169 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg); 170 } 171 172 mutex_unlock(&rt2x00dev->csr_mutex); 173 174} 175 176static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom) 177{ 178 struct rt2x00_dev *rt2x00dev = eeprom->data; 179 u32 reg; 180 181 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®); 182 183 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); 184 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); 185 eeprom->reg_data_clock = 186 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); 187 eeprom->reg_chip_select = 188 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); 189} 190 191static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom) 192{ 193 struct rt2x00_dev *rt2x00dev = eeprom->data; 194 u32 reg = 0; 195 196 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); 197 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); 198 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, 199 !!eeprom->reg_data_clock); 200 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, 201 !!eeprom->reg_chip_select); 202 203 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg); 204} 205 206#ifdef CONFIG_RT2X00_LIB_DEBUGFS 207static const struct rt2x00debug rt61pci_rt2x00debug = { 208 .owner = THIS_MODULE, 209 .csr = { 210 .read = rt2x00pci_register_read, 211 .write = rt2x00pci_register_write, 212 .flags = RT2X00DEBUGFS_OFFSET, 213 .word_base = CSR_REG_BASE, 214 .word_size = sizeof(u32), 215 .word_count = CSR_REG_SIZE / sizeof(u32), 216 }, 217 .eeprom = { 218 .read = rt2x00_eeprom_read, 219 .write = rt2x00_eeprom_write, 220 .word_base = EEPROM_BASE, 221 .word_size = sizeof(u16), 222 .word_count = EEPROM_SIZE / sizeof(u16), 223 }, 224 .bbp = { 225 .read = rt61pci_bbp_read, 226 .write = rt61pci_bbp_write, 227 .word_base = BBP_BASE, 228 .word_size = sizeof(u8), 229 .word_count = BBP_SIZE / sizeof(u8), 230 }, 231 .rf = { 232 .read = rt2x00_rf_read, 233 .write = rt61pci_rf_write, 234 .word_base = RF_BASE, 235 .word_size = sizeof(u32), 236 .word_count = RF_SIZE / sizeof(u32), 237 }, 238}; 239#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 240 241static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) 242{ 243 u32 reg; 244 245 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®); 246 return rt2x00_get_field32(reg, MAC_CSR13_BIT5); 247} 248 249#ifdef CONFIG_RT2X00_LIB_LEDS 250static void rt61pci_brightness_set(struct led_classdev *led_cdev, 251 enum led_brightness brightness) 252{ 253 struct rt2x00_led *led = 254 container_of(led_cdev, struct rt2x00_led, led_dev); 255 unsigned int enabled = brightness != LED_OFF; 256 unsigned int a_mode = 257 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); 258 unsigned int bg_mode = 259 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); 260 261 if (led->type == LED_TYPE_RADIO) { 262 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, 263 MCU_LEDCS_RADIO_STATUS, enabled); 264 265 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, 266 (led->rt2x00dev->led_mcu_reg & 0xff), 267 ((led->rt2x00dev->led_mcu_reg >> 8))); 268 } else if (led->type == LED_TYPE_ASSOC) { 269 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, 270 MCU_LEDCS_LINK_BG_STATUS, bg_mode); 271 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, 272 MCU_LEDCS_LINK_A_STATUS, a_mode); 273 274 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, 275 (led->rt2x00dev->led_mcu_reg & 0xff), 276 ((led->rt2x00dev->led_mcu_reg >> 8))); 277 } else if (led->type == LED_TYPE_QUALITY) { 278 /* 279 * The brightness is divided into 6 levels (0 - 5), 280 * this means we need to convert the brightness 281 * argument into the matching level within that range. 282 */ 283 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 284 brightness / (LED_FULL / 6), 0); 285 } 286} 287 288static int rt61pci_blink_set(struct led_classdev *led_cdev, 289 unsigned long *delay_on, 290 unsigned long *delay_off) 291{ 292 struct rt2x00_led *led = 293 container_of(led_cdev, struct rt2x00_led, led_dev); 294 u32 reg; 295 296 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, ®); 297 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); 298 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); 299 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg); 300 301 return 0; 302} 303 304static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev, 305 struct rt2x00_led *led, 306 enum led_type type) 307{ 308 led->rt2x00dev = rt2x00dev; 309 led->type = type; 310 led->led_dev.brightness_set = rt61pci_brightness_set; 311 led->led_dev.blink_set = rt61pci_blink_set; 312 led->flags = LED_INITIALIZED; 313} 314#endif /* CONFIG_RT2X00_LIB_LEDS */ 315 316/* 317 * Configuration handlers. 318 */ 319static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev, 320 struct rt2x00lib_crypto *crypto, 321 struct ieee80211_key_conf *key) 322{ 323 struct hw_key_entry key_entry; 324 struct rt2x00_field32 field; 325 u32 mask; 326 u32 reg; 327 328 if (crypto->cmd == SET_KEY) { 329 /* 330 * rt2x00lib can't determine the correct free 331 * key_idx for shared keys. We have 1 register 332 * with key valid bits. The goal is simple, read 333 * the register, if that is full we have no slots 334 * left. 335 * Note that each BSS is allowed to have up to 4 336 * shared keys, so put a mask over the allowed 337 * entries. 338 */ 339 mask = (0xf << crypto->bssidx); 340 341 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®); 342 reg &= mask; 343 344 if (reg && reg == mask) 345 return -ENOSPC; 346 347 key->hw_key_idx += reg ? ffz(reg) : 0; 348 349 /* 350 * Upload key to hardware 351 */ 352 memcpy(key_entry.key, crypto->key, 353 sizeof(key_entry.key)); 354 memcpy(key_entry.tx_mic, crypto->tx_mic, 355 sizeof(key_entry.tx_mic)); 356 memcpy(key_entry.rx_mic, crypto->rx_mic, 357 sizeof(key_entry.rx_mic)); 358 359 reg = SHARED_KEY_ENTRY(key->hw_key_idx); 360 rt2x00pci_register_multiwrite(rt2x00dev, reg, 361 &key_entry, sizeof(key_entry)); 362 363 /* 364 * The cipher types are stored over 2 registers. 365 * bssidx 0 and 1 keys are stored in SEC_CSR1 and 366 * bssidx 1 and 2 keys are stored in SEC_CSR5. 367 * Using the correct defines correctly will cause overhead, 368 * so just calculate the correct offset. 369 */ 370 if (key->hw_key_idx < 8) { 371 field.bit_offset = (3 * key->hw_key_idx); 372 field.bit_mask = 0x7 << field.bit_offset; 373 374 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, ®); 375 rt2x00_set_field32(®, field, crypto->cipher); 376 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg); 377 } else { 378 field.bit_offset = (3 * (key->hw_key_idx - 8)); 379 field.bit_mask = 0x7 << field.bit_offset; 380 381 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, ®); 382 rt2x00_set_field32(®, field, crypto->cipher); 383 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg); 384 } 385 386 /* 387 * The driver does not support the IV/EIV generation 388 * in hardware. However it doesn't support the IV/EIV 389 * inside the ieee80211 frame either, but requires it 390 * to be provided separately for the descriptor. 391 * rt2x00lib will cut the IV/EIV data out of all frames 392 * given to us by mac80211, but we must tell mac80211 393 * to generate the IV/EIV data. 394 */ 395 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 396 } 397 398 /* 399 * SEC_CSR0 contains only single-bit fields to indicate 400 * a particular key is valid. Because using the FIELD32() 401 * defines directly will cause a lot of overhead, we use 402 * a calculation to determine the correct bit directly. 403 */ 404 mask = 1 << key->hw_key_idx; 405 406 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®); 407 if (crypto->cmd == SET_KEY) 408 reg |= mask; 409 else if (crypto->cmd == DISABLE_KEY) 410 reg &= ~mask; 411 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg); 412 413 return 0; 414} 415 416static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 417 struct rt2x00lib_crypto *crypto, 418 struct ieee80211_key_conf *key) 419{ 420 struct hw_pairwise_ta_entry addr_entry; 421 struct hw_key_entry key_entry; 422 u32 mask; 423 u32 reg; 424 425 if (crypto->cmd == SET_KEY) { 426 /* 427 * rt2x00lib can't determine the correct free 428 * key_idx for pairwise keys. We have 2 registers 429 * with key valid bits. The goal is simple: read 430 * the first register. If that is full, move to 431 * the next register. 432 * When both registers are full, we drop the key. 433 * Otherwise, we use the first invalid entry. 434 */ 435 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®); 436 if (reg && reg == ~0) { 437 key->hw_key_idx = 32; 438 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®); 439 if (reg && reg == ~0) 440 return -ENOSPC; 441 } 442 443 key->hw_key_idx += reg ? ffz(reg) : 0; 444 445 /* 446 * Upload key to hardware 447 */ 448 memcpy(key_entry.key, crypto->key, 449 sizeof(key_entry.key)); 450 memcpy(key_entry.tx_mic, crypto->tx_mic, 451 sizeof(key_entry.tx_mic)); 452 memcpy(key_entry.rx_mic, crypto->rx_mic, 453 sizeof(key_entry.rx_mic)); 454 455 memset(&addr_entry, 0, sizeof(addr_entry)); 456 memcpy(&addr_entry, crypto->address, ETH_ALEN); 457 addr_entry.cipher = crypto->cipher; 458 459 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 460 rt2x00pci_register_multiwrite(rt2x00dev, reg, 461 &key_entry, sizeof(key_entry)); 462 463 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); 464 rt2x00pci_register_multiwrite(rt2x00dev, reg, 465 &addr_entry, sizeof(addr_entry)); 466 467 /* 468 * Enable pairwise lookup table for given BSS idx. 469 * Without this, received frames will not be decrypted 470 * by the hardware. 471 */ 472 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, ®); 473 reg |= (1 << crypto->bssidx); 474 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg); 475 476 /* 477 * The driver does not support the IV/EIV generation 478 * in hardware. However it doesn't support the IV/EIV 479 * inside the ieee80211 frame either, but requires it 480 * to be provided separately for the descriptor. 481 * rt2x00lib will cut the IV/EIV data out of all frames 482 * given to us by mac80211, but we must tell mac80211 483 * to generate the IV/EIV data. 484 */ 485 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 486 } 487 488 /* 489 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate 490 * a particular key is valid. Because using the FIELD32() 491 * defines directly will cause a lot of overhead, we use 492 * a calculation to determine the correct bit directly. 493 */ 494 if (key->hw_key_idx < 32) { 495 mask = 1 << key->hw_key_idx; 496 497 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®); 498 if (crypto->cmd == SET_KEY) 499 reg |= mask; 500 else if (crypto->cmd == DISABLE_KEY) 501 reg &= ~mask; 502 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg); 503 } else { 504 mask = 1 << (key->hw_key_idx - 32); 505 506 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®); 507 if (crypto->cmd == SET_KEY) 508 reg |= mask; 509 else if (crypto->cmd == DISABLE_KEY) 510 reg &= ~mask; 511 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg); 512 } 513 514 return 0; 515} 516 517static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev, 518 const unsigned int filter_flags) 519{ 520 u32 reg; 521 522 /* 523 * Start configuration steps. 524 * Note that the version error will always be dropped 525 * and broadcast frames will always be accepted since 526 * there is no filter for it at this time. 527 */ 528 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); 529 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, 530 !(filter_flags & FIF_FCSFAIL)); 531 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, 532 !(filter_flags & FIF_PLCPFAIL)); 533 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, 534 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL))); 535 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, 536 !(filter_flags & FIF_PROMISC_IN_BSS)); 537 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, 538 !(filter_flags & FIF_PROMISC_IN_BSS) && 539 !rt2x00dev->intf_ap_count); 540 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); 541 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, 542 !(filter_flags & FIF_ALLMULTI)); 543 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); 544 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 545 !(filter_flags & FIF_CONTROL)); 546 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 547} 548 549static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev, 550 struct rt2x00_intf *intf, 551 struct rt2x00intf_conf *conf, 552 const unsigned int flags) 553{ 554 unsigned int beacon_base; 555 u32 reg; 556 557 if (flags & CONFIG_UPDATE_TYPE) { 558 /* 559 * Clear current synchronisation setup. 560 * For the Beacon base registers, we only need to clear 561 * the first byte since that byte contains the VALID and OWNER 562 * bits which (when set to 0) will invalidate the entire beacon. 563 */ 564 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); 565 rt2x00pci_register_write(rt2x00dev, beacon_base, 0); 566 567 /* 568 * Enable synchronisation. 569 */ 570 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); 571 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); 572 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); 573 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); 574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 575 } 576 577 if (flags & CONFIG_UPDATE_MAC) { 578 reg = le32_to_cpu(conf->mac[1]); 579 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); 580 conf->mac[1] = cpu_to_le32(reg); 581 582 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, 583 conf->mac, sizeof(conf->mac)); 584 } 585 586 if (flags & CONFIG_UPDATE_BSSID) { 587 reg = le32_to_cpu(conf->bssid[1]); 588 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); 589 conf->bssid[1] = cpu_to_le32(reg); 590 591 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, 592 conf->bssid, sizeof(conf->bssid)); 593 } 594} 595 596static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, 597 struct rt2x00lib_erp *erp) 598{ 599 u32 reg; 600 601 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); 602 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); 603 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); 604 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 605 606 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®); 607 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); 608 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, 609 !!erp->short_preamble); 610 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); 611 612 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates); 613 614 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); 615 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 616 erp->beacon_int * 16); 617 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 618 619 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®); 620 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); 621 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); 622 623 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®); 624 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); 625 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); 626 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); 627 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg); 628} 629 630static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev, 631 struct antenna_setup *ant) 632{ 633 u8 r3; 634 u8 r4; 635 u8 r77; 636 637 rt61pci_bbp_read(rt2x00dev, 3, &r3); 638 rt61pci_bbp_read(rt2x00dev, 4, &r4); 639 rt61pci_bbp_read(rt2x00dev, 77, &r77); 640 641 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325)); 642 643 /* 644 * Configure the RX antenna. 645 */ 646 switch (ant->rx) { 647 case ANTENNA_HW_DIVERSITY: 648 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); 649 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 650 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ)); 651 break; 652 case ANTENNA_A: 653 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 654 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); 655 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) 656 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 657 else 658 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 659 break; 660 case ANTENNA_B: 661 default: 662 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 663 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); 664 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) 665 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 666 else 667 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 668 break; 669 } 670 671 rt61pci_bbp_write(rt2x00dev, 77, r77); 672 rt61pci_bbp_write(rt2x00dev, 3, r3); 673 rt61pci_bbp_write(rt2x00dev, 4, r4); 674} 675 676static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev, 677 struct antenna_setup *ant) 678{ 679 u8 r3; 680 u8 r4; 681 u8 r77; 682 683 rt61pci_bbp_read(rt2x00dev, 3, &r3); 684 rt61pci_bbp_read(rt2x00dev, 4, &r4); 685 rt61pci_bbp_read(rt2x00dev, 77, &r77); 686 687 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529)); 688 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 689 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)); 690 691 /* 692 * Configure the RX antenna. 693 */ 694 switch (ant->rx) { 695 case ANTENNA_HW_DIVERSITY: 696 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); 697 break; 698 case ANTENNA_A: 699 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 700 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 701 break; 702 case ANTENNA_B: 703 default: 704 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 705 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 706 break; 707 } 708 709 rt61pci_bbp_write(rt2x00dev, 77, r77); 710 rt61pci_bbp_write(rt2x00dev, 3, r3); 711 rt61pci_bbp_write(rt2x00dev, 4, r4); 712} 713 714static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev, 715 const int p1, const int p2) 716{ 717 u32 reg; 718 719 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®); 720 721 rt2x00_set_field32(®, MAC_CSR13_BIT4, p1); 722 rt2x00_set_field32(®, MAC_CSR13_BIT12, 0); 723 724 rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2); 725 rt2x00_set_field32(®, MAC_CSR13_BIT11, 0); 726 727 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg); 728} 729 730static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev, 731 struct antenna_setup *ant) 732{ 733 u8 r3; 734 u8 r4; 735 u8 r77; 736 737 rt61pci_bbp_read(rt2x00dev, 3, &r3); 738 rt61pci_bbp_read(rt2x00dev, 4, &r4); 739 rt61pci_bbp_read(rt2x00dev, 77, &r77); 740 741 /* 742 * Configure the RX antenna. 743 */ 744 switch (ant->rx) { 745 case ANTENNA_A: 746 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 747 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); 748 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0); 749 break; 750 case ANTENNA_HW_DIVERSITY: 751 case ANTENNA_B: 752 default: 753 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); 754 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); 755 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1); 756 break; 757 } 758 759 rt61pci_bbp_write(rt2x00dev, 77, r77); 760 rt61pci_bbp_write(rt2x00dev, 3, r3); 761 rt61pci_bbp_write(rt2x00dev, 4, r4); 762} 763 764struct antenna_sel { 765 u8 word; 766 /* 767 * value[0] -> non-LNA 768 * value[1] -> LNA 769 */ 770 u8 value[2]; 771}; 772 773static const struct antenna_sel antenna_sel_a[] = { 774 { 96, { 0x58, 0x78 } }, 775 { 104, { 0x38, 0x48 } }, 776 { 75, { 0xfe, 0x80 } }, 777 { 86, { 0xfe, 0x80 } }, 778 { 88, { 0xfe, 0x80 } }, 779 { 35, { 0x60, 0x60 } }, 780 { 97, { 0x58, 0x58 } }, 781 { 98, { 0x58, 0x58 } }, 782}; 783 784static const struct antenna_sel antenna_sel_bg[] = { 785 { 96, { 0x48, 0x68 } }, 786 { 104, { 0x2c, 0x3c } }, 787 { 75, { 0xfe, 0x80 } }, 788 { 86, { 0xfe, 0x80 } }, 789 { 88, { 0xfe, 0x80 } }, 790 { 35, { 0x50, 0x50 } }, 791 { 97, { 0x48, 0x48 } }, 792 { 98, { 0x48, 0x48 } }, 793}; 794 795static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev, 796 struct antenna_setup *ant) 797{ 798 const struct antenna_sel *sel; 799 unsigned int lna; 800 unsigned int i; 801 u32 reg; 802 803 /* 804 * We should never come here because rt2x00lib is supposed 805 * to catch this and send us the correct antenna explicitely. 806 */ 807 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || 808 ant->tx == ANTENNA_SW_DIVERSITY); 809 810 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { 811 sel = antenna_sel_a; 812 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); 813 } else { 814 sel = antenna_sel_bg; 815 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); 816 } 817 818 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) 819 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); 820 821 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®); 822 823 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 824 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); 825 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 826 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); 827 828 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg); 829 830 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) 831 rt61pci_config_antenna_5x(rt2x00dev, ant); 832 else if (rt2x00_rf(rt2x00dev, RF2527)) 833 rt61pci_config_antenna_2x(rt2x00dev, ant); 834 else if (rt2x00_rf(rt2x00dev, RF2529)) { 835 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) 836 rt61pci_config_antenna_2x(rt2x00dev, ant); 837 else 838 rt61pci_config_antenna_2529(rt2x00dev, ant); 839 } 840} 841 842static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev, 843 struct rt2x00lib_conf *libconf) 844{ 845 u16 eeprom; 846 short lna_gain = 0; 847 848 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) { 849 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) 850 lna_gain += 14; 851 852 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); 853 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); 854 } else { 855 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) 856 lna_gain += 14; 857 858 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); 859 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); 860 } 861 862 rt2x00dev->lna_gain = lna_gain; 863} 864 865static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev, 866 struct rf_channel *rf, const int txpower) 867{ 868 u8 r3; 869 u8 r94; 870 u8 smart; 871 872 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); 873 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 874 875 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)); 876 877 rt61pci_bbp_read(rt2x00dev, 3, &r3); 878 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); 879 rt61pci_bbp_write(rt2x00dev, 3, r3); 880 881 r94 = 6; 882 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) 883 r94 += txpower - MAX_TXPOWER; 884 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) 885 r94 += txpower; 886 rt61pci_bbp_write(rt2x00dev, 94, r94); 887 888 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); 889 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); 890 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 891 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); 892 893 udelay(200); 894 895 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); 896 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); 897 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 898 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); 899 900 udelay(200); 901 902 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); 903 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); 904 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 905 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); 906 907 msleep(1); 908} 909 910static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev, 911 const int txpower) 912{ 913 struct rf_channel rf; 914 915 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); 916 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); 917 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); 918 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); 919 920 rt61pci_config_channel(rt2x00dev, &rf, txpower); 921} 922 923static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, 924 struct rt2x00lib_conf *libconf) 925{ 926 u32 reg; 927 928 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®); 929 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); 930 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); 931 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); 932 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, 933 libconf->conf->long_frame_max_tx_count); 934 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, 935 libconf->conf->short_frame_max_tx_count); 936 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); 937} 938 939static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev, 940 struct rt2x00lib_conf *libconf) 941{ 942 enum dev_state state = 943 (libconf->conf->flags & IEEE80211_CONF_PS) ? 944 STATE_SLEEP : STATE_AWAKE; 945 u32 reg; 946 947 if (state == STATE_SLEEP) { 948 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, ®); 949 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 950 rt2x00dev->beacon_int - 10); 951 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 952 libconf->conf->listen_interval - 1); 953 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); 954 955 /* We must first disable autowake before it can be enabled */ 956 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); 957 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg); 958 959 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); 960 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg); 961 962 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005); 963 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c); 964 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060); 965 966 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0); 967 } else { 968 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, ®); 969 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); 970 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); 971 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); 972 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); 973 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg); 974 975 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); 976 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018); 977 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020); 978 979 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0); 980 } 981} 982 983static void rt61pci_config(struct rt2x00_dev *rt2x00dev, 984 struct rt2x00lib_conf *libconf, 985 const unsigned int flags) 986{ 987 /* Always recalculate LNA gain before changing configuration */ 988 rt61pci_config_lna_gain(rt2x00dev, libconf); 989 990 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) 991 rt61pci_config_channel(rt2x00dev, &libconf->rf, 992 libconf->conf->power_level); 993 if ((flags & IEEE80211_CONF_CHANGE_POWER) && 994 !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) 995 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level); 996 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 997 rt61pci_config_retry_limit(rt2x00dev, libconf); 998 if (flags & IEEE80211_CONF_CHANGE_PS) 999 rt61pci_config_ps(rt2x00dev, libconf); 1000} 1001 1002/* 1003 * Link tuning 1004 */ 1005static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev, 1006 struct link_qual *qual) 1007{ 1008 u32 reg; 1009 1010 /* 1011 * Update FCS error count from register. 1012 */ 1013 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®); 1014 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); 1015 1016 /* 1017 * Update False CCA count from register. 1018 */ 1019 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®); 1020 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); 1021} 1022 1023static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev, 1024 struct link_qual *qual, u8 vgc_level) 1025{ 1026 if (qual->vgc_level != vgc_level) { 1027 rt61pci_bbp_write(rt2x00dev, 17, vgc_level); 1028 qual->vgc_level = vgc_level; 1029 qual->vgc_level_reg = vgc_level; 1030 } 1031} 1032 1033static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev, 1034 struct link_qual *qual) 1035{ 1036 rt61pci_set_vgc(rt2x00dev, qual, 0x20); 1037} 1038 1039static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev, 1040 struct link_qual *qual, const u32 count) 1041{ 1042 u8 up_bound; 1043 u8 low_bound; 1044 1045 /* 1046 * Determine r17 bounds. 1047 */ 1048 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { 1049 low_bound = 0x28; 1050 up_bound = 0x48; 1051 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { 1052 low_bound += 0x10; 1053 up_bound += 0x10; 1054 } 1055 } else { 1056 low_bound = 0x20; 1057 up_bound = 0x40; 1058 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { 1059 low_bound += 0x10; 1060 up_bound += 0x10; 1061 } 1062 } 1063 1064 /* 1065 * If we are not associated, we should go straight to the 1066 * dynamic CCA tuning. 1067 */ 1068 if (!rt2x00dev->intf_associated) 1069 goto dynamic_cca_tune; 1070 1071 /* 1072 * Special big-R17 for very short distance 1073 */ 1074 if (qual->rssi >= -35) { 1075 rt61pci_set_vgc(rt2x00dev, qual, 0x60); 1076 return; 1077 } 1078 1079 /* 1080 * Special big-R17 for short distance 1081 */ 1082 if (qual->rssi >= -58) { 1083 rt61pci_set_vgc(rt2x00dev, qual, up_bound); 1084 return; 1085 } 1086 1087 /* 1088 * Special big-R17 for middle-short distance 1089 */ 1090 if (qual->rssi >= -66) { 1091 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10); 1092 return; 1093 } 1094 1095 /* 1096 * Special mid-R17 for middle distance 1097 */ 1098 if (qual->rssi >= -74) { 1099 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08); 1100 return; 1101 } 1102 1103 /* 1104 * Special case: Change up_bound based on the rssi. 1105 * Lower up_bound when rssi is weaker then -74 dBm. 1106 */ 1107 up_bound -= 2 * (-74 - qual->rssi); 1108 if (low_bound > up_bound) 1109 up_bound = low_bound; 1110 1111 if (qual->vgc_level > up_bound) { 1112 rt61pci_set_vgc(rt2x00dev, qual, up_bound); 1113 return; 1114 } 1115 1116dynamic_cca_tune: 1117 1118 /* 1119 * r17 does not yet exceed upper limit, continue and base 1120 * the r17 tuning on the false CCA count. 1121 */ 1122 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound)) 1123 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); 1124 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound)) 1125 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); 1126} 1127 1128/* 1129 * Firmware functions 1130 */ 1131static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) 1132{ 1133 u16 chip; 1134 char *fw_name; 1135 1136 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip); 1137 switch (chip) { 1138 case RT2561_PCI_ID: 1139 fw_name = FIRMWARE_RT2561; 1140 break; 1141 case RT2561s_PCI_ID: 1142 fw_name = FIRMWARE_RT2561s; 1143 break; 1144 case RT2661_PCI_ID: 1145 fw_name = FIRMWARE_RT2661; 1146 break; 1147 default: 1148 fw_name = NULL; 1149 break; 1150 } 1151 1152 return fw_name; 1153} 1154 1155static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev, 1156 const u8 *data, const size_t len) 1157{ 1158 u16 fw_crc; 1159 u16 crc; 1160 1161 /* 1162 * Only support 8kb firmware files. 1163 */ 1164 if (len != 8192) 1165 return FW_BAD_LENGTH; 1166 1167 /* 1168 * The last 2 bytes in the firmware array are the crc checksum itself. 1169 * This means that we should never pass those 2 bytes to the crc 1170 * algorithm. 1171 */ 1172 fw_crc = (data[len - 2] << 8 | data[len - 1]); 1173 1174 /* 1175 * Use the crc itu-t algorithm. 1176 */ 1177 crc = crc_itu_t(0, data, len - 2); 1178 crc = crc_itu_t_byte(crc, 0); 1179 crc = crc_itu_t_byte(crc, 0); 1180 1181 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC; 1182} 1183 1184static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, 1185 const u8 *data, const size_t len) 1186{ 1187 int i; 1188 u32 reg; 1189 1190 /* 1191 * Wait for stable hardware. 1192 */ 1193 for (i = 0; i < 100; i++) { 1194 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®); 1195 if (reg) 1196 break; 1197 msleep(1); 1198 } 1199 1200 if (!reg) { 1201 ERROR(rt2x00dev, "Unstable hardware.\n"); 1202 return -EBUSY; 1203 } 1204 1205 /* 1206 * Prepare MCU and mailbox for firmware loading. 1207 */ 1208 reg = 0; 1209 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); 1210 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); 1211 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); 1212 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 1213 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0); 1214 1215 /* 1216 * Write firmware to device. 1217 */ 1218 reg = 0; 1219 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); 1220 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1); 1221 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); 1222 1223 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, 1224 data, len); 1225 1226 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0); 1227 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); 1228 1229 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0); 1230 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); 1231 1232 for (i = 0; i < 100; i++) { 1233 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®); 1234 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY)) 1235 break; 1236 msleep(1); 1237 } 1238 1239 if (i == 100) { 1240 ERROR(rt2x00dev, "MCU Control register not ready.\n"); 1241 return -EBUSY; 1242 } 1243 1244 /* 1245 * Hardware needs another millisecond before it is ready. 1246 */ 1247 msleep(1); 1248 1249 /* 1250 * Reset MAC and BBP registers. 1251 */ 1252 reg = 0; 1253 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); 1254 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); 1255 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); 1256 1257 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); 1258 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); 1259 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); 1260 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); 1261 1262 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); 1263 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); 1264 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); 1265 1266 return 0; 1267} 1268 1269/* 1270 * Initialization functions. 1271 */ 1272static bool rt61pci_get_entry_state(struct queue_entry *entry) 1273{ 1274 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1275 u32 word; 1276 1277 if (entry->queue->qid == QID_RX) { 1278 rt2x00_desc_read(entry_priv->desc, 0, &word); 1279 1280 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); 1281 } else { 1282 rt2x00_desc_read(entry_priv->desc, 0, &word); 1283 1284 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1285 rt2x00_get_field32(word, TXD_W0_VALID)); 1286 } 1287} 1288 1289static void rt61pci_clear_entry(struct queue_entry *entry) 1290{ 1291 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1292 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1293 u32 word; 1294 1295 if (entry->queue->qid == QID_RX) { 1296 rt2x00_desc_read(entry_priv->desc, 5, &word); 1297 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, 1298 skbdesc->skb_dma); 1299 rt2x00_desc_write(entry_priv->desc, 5, word); 1300 1301 rt2x00_desc_read(entry_priv->desc, 0, &word); 1302 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 1303 rt2x00_desc_write(entry_priv->desc, 0, word); 1304 } else { 1305 rt2x00_desc_read(entry_priv->desc, 0, &word); 1306 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 1307 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 1308 rt2x00_desc_write(entry_priv->desc, 0, word); 1309 } 1310} 1311 1312static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) 1313{ 1314 struct queue_entry_priv_pci *entry_priv; 1315 u32 reg; 1316 1317 /* 1318 * Initialize registers. 1319 */ 1320 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®); 1321 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE, 1322 rt2x00dev->tx[0].limit); 1323 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE, 1324 rt2x00dev->tx[1].limit); 1325 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE, 1326 rt2x00dev->tx[2].limit); 1327 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE, 1328 rt2x00dev->tx[3].limit); 1329 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg); 1330 1331 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®); 1332 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE, 1333 rt2x00dev->tx[0].desc_size / 4); 1334 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg); 1335 1336 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 1337 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®); 1338 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, 1339 entry_priv->desc_dma); 1340 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg); 1341 1342 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 1343 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®); 1344 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, 1345 entry_priv->desc_dma); 1346 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg); 1347 1348 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; 1349 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®); 1350 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, 1351 entry_priv->desc_dma); 1352 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg); 1353 1354 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; 1355 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®); 1356 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, 1357 entry_priv->desc_dma); 1358 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg); 1359 1360 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®); 1361 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); 1362 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE, 1363 rt2x00dev->rx->desc_size / 4); 1364 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); 1365 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg); 1366 1367 entry_priv = rt2x00dev->rx->entries[0].priv_data; 1368 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®); 1369 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, 1370 entry_priv->desc_dma); 1371 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg); 1372 1373 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®); 1374 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2); 1375 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2); 1376 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2); 1377 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2); 1378 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); 1379 1380 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®); 1381 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); 1382 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); 1383 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); 1384 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); 1385 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); 1386 1387 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®); 1388 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1); 1389 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg); 1390 1391 return 0; 1392} 1393 1394static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) 1395{ 1396 u32 reg; 1397 1398 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); 1399 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); 1400 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); 1401 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); 1402 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 1403 1404 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®); 1405 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ 1406 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); 1407 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ 1408 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); 1409 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ 1410 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); 1411 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ 1412 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); 1413 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg); 1414 1415 /* 1416 * CCK TXD BBP registers 1417 */ 1418 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®); 1419 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); 1420 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); 1421 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); 1422 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); 1423 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); 1424 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); 1425 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); 1426 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); 1427 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg); 1428 1429 /* 1430 * OFDM TXD BBP registers 1431 */ 1432 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®); 1433 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); 1434 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); 1435 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); 1436 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); 1437 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); 1438 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); 1439 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg); 1440 1441 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®); 1442 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); 1443 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); 1444 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); 1445 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); 1446 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg); 1447 1448 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®); 1449 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); 1450 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); 1451 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); 1452 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); 1453 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg); 1454 1455 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); 1456 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); 1457 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); 1458 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); 1459 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); 1460 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); 1461 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); 1462 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 1463 1464 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); 1465 1466 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); 1467 1468 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®); 1469 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); 1470 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); 1471 1472 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c); 1473 1474 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) 1475 return -EBUSY; 1476 1477 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); 1478 1479 /* 1480 * Invalidate all Shared Keys (SEC_CSR0), 1481 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) 1482 */ 1483 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000); 1484 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000); 1485 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000); 1486 1487 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0); 1488 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); 1489 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606); 1490 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08); 1491 1492 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404); 1493 1494 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200); 1495 1496 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); 1497 1498 /* 1499 * Clear all beacons 1500 * For the Beacon base registers we only need to clear 1501 * the first byte since that byte contains the VALID and OWNER 1502 * bits which (when set to 0) will invalidate the entire beacon. 1503 */ 1504 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0); 1505 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0); 1506 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0); 1507 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0); 1508 1509 /* 1510 * We must clear the error counters. 1511 * These registers are cleared on read, 1512 * so we may pass a useless variable to store the value. 1513 */ 1514 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®); 1515 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®); 1516 rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®); 1517 1518 /* 1519 * Reset MAC and BBP registers. 1520 */ 1521 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); 1522 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); 1523 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); 1524 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); 1525 1526 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); 1527 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); 1528 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); 1529 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); 1530 1531 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); 1532 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); 1533 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); 1534 1535 return 0; 1536} 1537 1538static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 1539{ 1540 unsigned int i; 1541 u8 value; 1542 1543 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1544 rt61pci_bbp_read(rt2x00dev, 0, &value); 1545 if ((value != 0xff) && (value != 0x00)) 1546 return 0; 1547 udelay(REGISTER_BUSY_DELAY); 1548 } 1549 1550 ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); 1551 return -EACCES; 1552} 1553 1554static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev) 1555{ 1556 unsigned int i; 1557 u16 eeprom; 1558 u8 reg_id; 1559 u8 value; 1560 1561 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev))) 1562 return -EACCES; 1563 1564 rt61pci_bbp_write(rt2x00dev, 3, 0x00); 1565 rt61pci_bbp_write(rt2x00dev, 15, 0x30); 1566 rt61pci_bbp_write(rt2x00dev, 21, 0xc8); 1567 rt61pci_bbp_write(rt2x00dev, 22, 0x38); 1568 rt61pci_bbp_write(rt2x00dev, 23, 0x06); 1569 rt61pci_bbp_write(rt2x00dev, 24, 0xfe); 1570 rt61pci_bbp_write(rt2x00dev, 25, 0x0a); 1571 rt61pci_bbp_write(rt2x00dev, 26, 0x0d); 1572 rt61pci_bbp_write(rt2x00dev, 34, 0x12); 1573 rt61pci_bbp_write(rt2x00dev, 37, 0x07); 1574 rt61pci_bbp_write(rt2x00dev, 39, 0xf8); 1575 rt61pci_bbp_write(rt2x00dev, 41, 0x60); 1576 rt61pci_bbp_write(rt2x00dev, 53, 0x10); 1577 rt61pci_bbp_write(rt2x00dev, 54, 0x18); 1578 rt61pci_bbp_write(rt2x00dev, 60, 0x10); 1579 rt61pci_bbp_write(rt2x00dev, 61, 0x04); 1580 rt61pci_bbp_write(rt2x00dev, 62, 0x04); 1581 rt61pci_bbp_write(rt2x00dev, 75, 0xfe); 1582 rt61pci_bbp_write(rt2x00dev, 86, 0xfe); 1583 rt61pci_bbp_write(rt2x00dev, 88, 0xfe); 1584 rt61pci_bbp_write(rt2x00dev, 90, 0x0f); 1585 rt61pci_bbp_write(rt2x00dev, 99, 0x00); 1586 rt61pci_bbp_write(rt2x00dev, 102, 0x16); 1587 rt61pci_bbp_write(rt2x00dev, 107, 0x04); 1588 1589 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 1590 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); 1591 1592 if (eeprom != 0xffff && eeprom != 0x0000) { 1593 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 1594 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 1595 rt61pci_bbp_write(rt2x00dev, reg_id, value); 1596 } 1597 } 1598 1599 return 0; 1600} 1601 1602/* 1603 * Device state switch handlers. 1604 */ 1605static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev, 1606 enum dev_state state) 1607{ 1608 u32 reg; 1609 1610 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); 1611 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1612 (state == STATE_RADIO_RX_OFF) || 1613 (state == STATE_RADIO_RX_OFF_LINK)); 1614 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 1615} 1616 1617static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 1618 enum dev_state state) 1619{ 1620 int mask = (state == STATE_RADIO_IRQ_OFF) || 1621 (state == STATE_RADIO_IRQ_OFF_ISR); 1622 u32 reg; 1623 1624 /* 1625 * When interrupts are being enabled, the interrupt registers 1626 * should clear the register to assure a clean state. 1627 */ 1628 if (state == STATE_RADIO_IRQ_ON) { 1629 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®); 1630 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 1631 1632 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®); 1633 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); 1634 } 1635 1636 /* 1637 * Only toggle the interrupts bits we are going to use. 1638 * Non-checked interrupt bits are disabled by default. 1639 */ 1640 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®); 1641 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); 1642 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); 1643 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask); 1644 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); 1645 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 1646 1647 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); 1648 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); 1649 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); 1650 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); 1651 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask); 1652 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask); 1653 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask); 1654 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask); 1655 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask); 1656 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); 1657} 1658 1659static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) 1660{ 1661 u32 reg; 1662 1663 /* 1664 * Initialize all registers. 1665 */ 1666 if (unlikely(rt61pci_init_queues(rt2x00dev) || 1667 rt61pci_init_registers(rt2x00dev) || 1668 rt61pci_init_bbp(rt2x00dev))) 1669 return -EIO; 1670 1671 /* 1672 * Enable RX. 1673 */ 1674 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®); 1675 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1); 1676 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg); 1677 1678 return 0; 1679} 1680 1681static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev) 1682{ 1683 /* 1684 * Disable power 1685 */ 1686 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818); 1687} 1688 1689static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) 1690{ 1691 u32 reg, reg2; 1692 unsigned int i; 1693 char put_to_sleep; 1694 1695 put_to_sleep = (state != STATE_AWAKE); 1696 1697 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®); 1698 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); 1699 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); 1700 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg); 1701 1702 /* 1703 * Device is not guaranteed to be in the requested state yet. 1704 * We must wait until the register indicates that the 1705 * device has entered the correct state. 1706 */ 1707 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1708 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®2); 1709 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE); 1710 if (state == !put_to_sleep) 1711 return 0; 1712 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg); 1713 msleep(10); 1714 } 1715 1716 return -EBUSY; 1717} 1718 1719static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev, 1720 enum dev_state state) 1721{ 1722 int retval = 0; 1723 1724 switch (state) { 1725 case STATE_RADIO_ON: 1726 retval = rt61pci_enable_radio(rt2x00dev); 1727 break; 1728 case STATE_RADIO_OFF: 1729 rt61pci_disable_radio(rt2x00dev); 1730 break; 1731 case STATE_RADIO_RX_ON: 1732 case STATE_RADIO_RX_ON_LINK: 1733 case STATE_RADIO_RX_OFF: 1734 case STATE_RADIO_RX_OFF_LINK: 1735 rt61pci_toggle_rx(rt2x00dev, state); 1736 break; 1737 case STATE_RADIO_IRQ_ON: 1738 case STATE_RADIO_IRQ_ON_ISR: 1739 case STATE_RADIO_IRQ_OFF: 1740 case STATE_RADIO_IRQ_OFF_ISR: 1741 rt61pci_toggle_irq(rt2x00dev, state); 1742 break; 1743 case STATE_DEEP_SLEEP: 1744 case STATE_SLEEP: 1745 case STATE_STANDBY: 1746 case STATE_AWAKE: 1747 retval = rt61pci_set_state(rt2x00dev, state); 1748 break; 1749 default: 1750 retval = -ENOTSUPP; 1751 break; 1752 } 1753 1754 if (unlikely(retval)) 1755 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", 1756 state, retval); 1757 1758 return retval; 1759} 1760 1761/* 1762 * TX descriptor initialization 1763 */ 1764static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1765 struct sk_buff *skb, 1766 struct txentry_desc *txdesc) 1767{ 1768 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1769 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; 1770 __le32 *txd = entry_priv->desc; 1771 u32 word; 1772 1773 /* 1774 * Start writing the descriptor words. 1775 */ 1776 rt2x00_desc_read(txd, 1, &word); 1777 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue); 1778 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs); 1779 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min); 1780 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max); 1781 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); 1782 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1783 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 1784 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1); 1785 rt2x00_desc_write(txd, 1, word); 1786 1787 rt2x00_desc_read(txd, 2, &word); 1788 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); 1789 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); 1790 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); 1791 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); 1792 rt2x00_desc_write(txd, 2, word); 1793 1794 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { 1795 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]); 1796 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); 1797 } 1798 1799 rt2x00_desc_read(txd, 5, &word); 1800 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid); 1801 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, 1802 skbdesc->entry->entry_idx); 1803 rt2x00_set_field32(&word, TXD_W5_TX_POWER, 1804 TXPOWER_TO_DEV(rt2x00dev->tx_power)); 1805 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); 1806 rt2x00_desc_write(txd, 5, word); 1807 1808 if (txdesc->queue != QID_BEACON) { 1809 rt2x00_desc_read(txd, 6, &word); 1810 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, 1811 skbdesc->skb_dma); 1812 rt2x00_desc_write(txd, 6, word); 1813 1814 rt2x00_desc_read(txd, 11, &word); 1815 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, 1816 txdesc->length); 1817 rt2x00_desc_write(txd, 11, word); 1818 } 1819 1820 /* 1821 * Writing TXD word 0 must the last to prevent a race condition with 1822 * the device, whereby the device may take hold of the TXD before we 1823 * finished updating it. 1824 */ 1825 rt2x00_desc_read(txd, 0, &word); 1826 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); 1827 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1828 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, 1829 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 1830 rt2x00_set_field32(&word, TXD_W0_ACK, 1831 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 1832 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, 1833 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 1834 rt2x00_set_field32(&word, TXD_W0_OFDM, 1835 (txdesc->rate_mode == RATE_MODE_OFDM)); 1836 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1837 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1838 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1839 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 1840 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags)); 1841 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, 1842 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags)); 1843 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); 1844 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); 1845 rt2x00_set_field32(&word, TXD_W0_BURST, 1846 test_bit(ENTRY_TXD_BURST, &txdesc->flags)); 1847 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); 1848 rt2x00_desc_write(txd, 0, word); 1849 1850 /* 1851 * Register descriptor details in skb frame descriptor. 1852 */ 1853 skbdesc->desc = txd; 1854 skbdesc->desc_len = 1855 (txdesc->queue == QID_BEACON) ? TXINFO_SIZE : TXD_DESC_SIZE; 1856} 1857 1858/* 1859 * TX data initialization 1860 */ 1861static void rt61pci_write_beacon(struct queue_entry *entry, 1862 struct txentry_desc *txdesc) 1863{ 1864 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1865 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1866 unsigned int beacon_base; 1867 u32 reg; 1868 1869 /* 1870 * Disable beaconing while we are reloading the beacon data, 1871 * otherwise we might be sending out invalid data. 1872 */ 1873 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); 1874 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); 1875 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 1876 1877 /* 1878 * Write the TX descriptor for the beacon. 1879 */ 1880 rt61pci_write_tx_desc(rt2x00dev, entry->skb, txdesc); 1881 1882 /* 1883 * Dump beacon to userspace through debugfs. 1884 */ 1885 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); 1886 1887 /* 1888 * Write entire beacon with descriptor to register. 1889 */ 1890 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 1891 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base, 1892 entry_priv->desc, TXINFO_SIZE); 1893 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE, 1894 entry->skb->data, entry->skb->len); 1895 1896 /* 1897 * Enable beaconing again. 1898 * 1899 * For Wi-Fi faily generated beacons between participating 1900 * stations. Set TBTT phase adaptive adjustment step to 8us. 1901 */ 1902 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); 1903 1904 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); 1905 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); 1906 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); 1907 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 1908 1909 /* 1910 * Clean up beacon skb. 1911 */ 1912 dev_kfree_skb_any(entry->skb); 1913 entry->skb = NULL; 1914} 1915 1916static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 1917 const enum data_queue_qid queue) 1918{ 1919 u32 reg; 1920 1921 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); 1922 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE)); 1923 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK)); 1924 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI)); 1925 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO)); 1926 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1927} 1928 1929static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev, 1930 const enum data_queue_qid qid) 1931{ 1932 u32 reg; 1933 1934 if (qid == QID_BEACON) { 1935 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0); 1936 return; 1937 } 1938 1939 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); 1940 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE)); 1941 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK)); 1942 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI)); 1943 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO)); 1944 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); 1945} 1946 1947/* 1948 * RX control handlers 1949 */ 1950static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) 1951{ 1952 u8 offset = rt2x00dev->lna_gain; 1953 u8 lna; 1954 1955 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA); 1956 switch (lna) { 1957 case 3: 1958 offset += 90; 1959 break; 1960 case 2: 1961 offset += 74; 1962 break; 1963 case 1: 1964 offset += 64; 1965 break; 1966 default: 1967 return 0; 1968 } 1969 1970 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { 1971 if (lna == 3 || lna == 2) 1972 offset += 10; 1973 } 1974 1975 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; 1976} 1977 1978static void rt61pci_fill_rxdone(struct queue_entry *entry, 1979 struct rxdone_entry_desc *rxdesc) 1980{ 1981 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1982 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1983 u32 word0; 1984 u32 word1; 1985 1986 rt2x00_desc_read(entry_priv->desc, 0, &word0); 1987 rt2x00_desc_read(entry_priv->desc, 1, &word1); 1988 1989 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1990 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1991 1992 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG); 1993 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); 1994 1995 if (rxdesc->cipher != CIPHER_NONE) { 1996 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]); 1997 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]); 1998 rxdesc->dev_flags |= RXDONE_CRYPTO_IV; 1999 2000 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv); 2001 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV; 2002 2003 /* 2004 * Hardware has stripped IV/EIV data from 802.11 frame during 2005 * decryption. It has provided the data separately but rt2x00lib 2006 * should decide if it should be reinserted. 2007 */ 2008 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 2009 2010 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; 2011 2012 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) 2013 rxdesc->flags |= RX_FLAG_DECRYPTED; 2014 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) 2015 rxdesc->flags |= RX_FLAG_MMIC_ERROR; 2016 } 2017 2018 /* 2019 * Obtain the status about this packet. 2020 * When frame was received with an OFDM bitrate, 2021 * the signal is the PLCP value. If it was received with 2022 * a CCK bitrate the signal is the rate in 100kbit/s. 2023 */ 2024 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); 2025 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1); 2026 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 2027 2028 if (rt2x00_get_field32(word0, RXD_W0_OFDM)) 2029 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; 2030 else 2031 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; 2032 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) 2033 rxdesc->dev_flags |= RXDONE_MY_BSS; 2034} 2035 2036/* 2037 * Interrupt functions. 2038 */ 2039static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) 2040{ 2041 struct data_queue *queue; 2042 struct queue_entry *entry; 2043 struct queue_entry *entry_done; 2044 struct queue_entry_priv_pci *entry_priv; 2045 struct txdone_entry_desc txdesc; 2046 u32 word; 2047 u32 reg; 2048 int type; 2049 int index; 2050 int i; 2051 2052 /* 2053 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO 2054 * at most X times and also stop processing once the TX_STA_FIFO_VALID 2055 * flag is not set anymore. 2056 * 2057 * The legacy drivers use X=TX_RING_SIZE but state in a comment 2058 * that the TX_STA_FIFO stack has a size of 16. We stick to our 2059 * tx ring size for now. 2060 */ 2061 for (i = 0; i < TX_ENTRIES; i++) { 2062 rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®); 2063 if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) 2064 break; 2065 2066 /* 2067 * Skip this entry when it contains an invalid 2068 * queue identication number. 2069 */ 2070 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); 2071 queue = rt2x00queue_get_queue(rt2x00dev, type); 2072 if (unlikely(!queue)) 2073 continue; 2074 2075 /* 2076 * Skip this entry when it contains an invalid 2077 * index number. 2078 */ 2079 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE); 2080 if (unlikely(index >= queue->limit)) 2081 continue; 2082 2083 entry = &queue->entries[index]; 2084 entry_priv = entry->priv_data; 2085 rt2x00_desc_read(entry_priv->desc, 0, &word); 2086 2087 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 2088 !rt2x00_get_field32(word, TXD_W0_VALID)) 2089 return; 2090 2091 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 2092 while (entry != entry_done) { 2093 /* Catch up. 2094 * Just report any entries we missed as failed. 2095 */ 2096 WARNING(rt2x00dev, 2097 "TX status report missed for entry %d\n", 2098 entry_done->entry_idx); 2099 2100 txdesc.flags = 0; 2101 __set_bit(TXDONE_UNKNOWN, &txdesc.flags); 2102 txdesc.retry = 0; 2103 2104 rt2x00lib_txdone(entry_done, &txdesc); 2105 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 2106 } 2107 2108 /* 2109 * Obtain the status about this packet. 2110 */ 2111 txdesc.flags = 0; 2112 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) { 2113 case 0: /* Success, maybe with retry */ 2114 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 2115 break; 2116 case 6: /* Failure, excessive retries */ 2117 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); 2118 /* Don't break, this is a failed frame! */ 2119 default: /* Failure */ 2120 __set_bit(TXDONE_FAILURE, &txdesc.flags); 2121 } 2122 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); 2123 2124 /* 2125 * the frame was retried at least once 2126 * -> hw used fallback rates 2127 */ 2128 if (txdesc.retry) 2129 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 2130 2131 rt2x00lib_txdone(entry, &txdesc); 2132 } 2133} 2134 2135static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev) 2136{ 2137 struct ieee80211_conf conf = { .flags = 0 }; 2138 struct rt2x00lib_conf libconf = { .conf = &conf }; 2139 2140 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS); 2141} 2142 2143static irqreturn_t rt61pci_interrupt_thread(int irq, void *dev_instance) 2144{ 2145 struct rt2x00_dev *rt2x00dev = dev_instance; 2146 u32 reg = rt2x00dev->irqvalue[0]; 2147 u32 reg_mcu = rt2x00dev->irqvalue[1]; 2148 2149 /* 2150 * Handle interrupts, walk through all bits 2151 * and run the tasks, the bits are checked in order of 2152 * priority. 2153 */ 2154 2155 /* 2156 * 1 - Rx ring done interrupt. 2157 */ 2158 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE)) 2159 rt2x00pci_rxdone(rt2x00dev); 2160 2161 /* 2162 * 2 - Tx ring done interrupt. 2163 */ 2164 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE)) 2165 rt61pci_txdone(rt2x00dev); 2166 2167 /* 2168 * 3 - Handle MCU command done. 2169 */ 2170 if (reg_mcu) 2171 rt2x00pci_register_write(rt2x00dev, 2172 M2H_CMD_DONE_CSR, 0xffffffff); 2173 2174 /* 2175 * 4 - MCU Autowakeup interrupt. 2176 */ 2177 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP)) 2178 rt61pci_wakeup(rt2x00dev); 2179 2180 /* 2181 * 5 - Beacon done interrupt. 2182 */ 2183 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE)) 2184 rt2x00lib_beacondone(rt2x00dev); 2185 2186 /* Enable interrupts again. */ 2187 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 2188 STATE_RADIO_IRQ_ON_ISR); 2189 return IRQ_HANDLED; 2190} 2191 2192 2193static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) 2194{ 2195 struct rt2x00_dev *rt2x00dev = dev_instance; 2196 u32 reg_mcu; 2197 u32 reg; 2198 2199 /* 2200 * Get the interrupt sources & saved to local variable. 2201 * Write register value back to clear pending interrupts. 2202 */ 2203 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu); 2204 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); 2205 2206 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®); 2207 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 2208 2209 if (!reg && !reg_mcu) 2210 return IRQ_NONE; 2211 2212 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 2213 return IRQ_HANDLED; 2214 2215 /* Store irqvalues for use in the interrupt thread. */ 2216 rt2x00dev->irqvalue[0] = reg; 2217 rt2x00dev->irqvalue[1] = reg_mcu; 2218 2219 /* Disable interrupts, will be enabled again in the interrupt thread. */ 2220 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 2221 STATE_RADIO_IRQ_OFF_ISR); 2222 return IRQ_WAKE_THREAD; 2223} 2224 2225/* 2226 * Device probe functions. 2227 */ 2228static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) 2229{ 2230 struct eeprom_93cx6 eeprom; 2231 u32 reg; 2232 u16 word; 2233 u8 *mac; 2234 s8 value; 2235 2236 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®); 2237 2238 eeprom.data = rt2x00dev; 2239 eeprom.register_read = rt61pci_eepromregister_read; 2240 eeprom.register_write = rt61pci_eepromregister_write; 2241 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ? 2242 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; 2243 eeprom.reg_data_in = 0; 2244 eeprom.reg_data_out = 0; 2245 eeprom.reg_data_clock = 0; 2246 eeprom.reg_chip_select = 0; 2247 2248 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, 2249 EEPROM_SIZE / sizeof(u16)); 2250 2251 /* 2252 * Start validation of the data that has been read. 2253 */ 2254 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 2255 if (!is_valid_ether_addr(mac)) { 2256 random_ether_addr(mac); 2257 EEPROM(rt2x00dev, "MAC: %pM\n", mac); 2258 } 2259 2260 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); 2261 if (word == 0xffff) { 2262 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); 2263 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2264 ANTENNA_B); 2265 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2266 ANTENNA_B); 2267 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0); 2268 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); 2269 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); 2270 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225); 2271 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); 2272 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); 2273 } 2274 2275 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); 2276 if (word == 0xffff) { 2277 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0); 2278 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0); 2279 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0); 2280 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0); 2281 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0); 2282 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); 2283 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0); 2284 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); 2285 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); 2286 } 2287 2288 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); 2289 if (word == 0xffff) { 2290 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, 2291 LED_MODE_DEFAULT); 2292 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); 2293 EEPROM(rt2x00dev, "Led: 0x%04x\n", word); 2294 } 2295 2296 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); 2297 if (word == 0xffff) { 2298 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 2299 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); 2300 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 2301 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); 2302 } 2303 2304 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); 2305 if (word == 0xffff) { 2306 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); 2307 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); 2308 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); 2309 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); 2310 } else { 2311 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1); 2312 if (value < -10 || value > 10) 2313 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); 2314 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2); 2315 if (value < -10 || value > 10) 2316 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); 2317 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); 2318 } 2319 2320 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); 2321 if (word == 0xffff) { 2322 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); 2323 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); 2324 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); 2325 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); 2326 } else { 2327 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); 2328 if (value < -10 || value > 10) 2329 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); 2330 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2); 2331 if (value < -10 || value > 10) 2332 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); 2333 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); 2334 } 2335 2336 return 0; 2337} 2338 2339static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) 2340{ 2341 u32 reg; 2342 u16 value; 2343 u16 eeprom; 2344 2345 /* 2346 * Read EEPROM word for configuration. 2347 */ 2348 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); 2349 2350 /* 2351 * Identify RF chipset. 2352 */ 2353 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 2354 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®); 2355 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), 2356 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); 2357 2358 if (!rt2x00_rf(rt2x00dev, RF5225) && 2359 !rt2x00_rf(rt2x00dev, RF5325) && 2360 !rt2x00_rf(rt2x00dev, RF2527) && 2361 !rt2x00_rf(rt2x00dev, RF2529)) { 2362 ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); 2363 return -ENODEV; 2364 } 2365 2366 /* 2367 * Determine number of antennas. 2368 */ 2369 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2) 2370 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags); 2371 2372 /* 2373 * Identify default antenna configuration. 2374 */ 2375 rt2x00dev->default_ant.tx = 2376 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); 2377 rt2x00dev->default_ant.rx = 2378 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); 2379 2380 /* 2381 * Read the Frame type. 2382 */ 2383 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) 2384 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags); 2385 2386 /* 2387 * Detect if this device has a hardware controlled radio. 2388 */ 2389 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) 2390 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); 2391 2392 /* 2393 * Read frequency offset and RF programming sequence. 2394 */ 2395 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); 2396 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ)) 2397 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags); 2398 2399 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 2400 2401 /* 2402 * Read external LNA informations. 2403 */ 2404 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 2405 2406 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) 2407 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); 2408 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) 2409 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); 2410 2411 /* 2412 * When working with a RF2529 chip without double antenna, 2413 * the antenna settings should be gathered from the NIC 2414 * eeprom word. 2415 */ 2416 if (rt2x00_rf(rt2x00dev, RF2529) && 2417 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) { 2418 rt2x00dev->default_ant.rx = 2419 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED); 2420 rt2x00dev->default_ant.tx = 2421 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED); 2422 2423 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) 2424 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY; 2425 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) 2426 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY; 2427 } 2428 2429 /* 2430 * Store led settings, for correct led behaviour. 2431 * If the eeprom value is invalid, 2432 * switch to default led mode. 2433 */ 2434#ifdef CONFIG_RT2X00_LIB_LEDS 2435 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); 2436 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE); 2437 2438 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 2439 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 2440 if (value == LED_MODE_SIGNAL_STRENGTH) 2441 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual, 2442 LED_TYPE_QUALITY); 2443 2444 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); 2445 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, 2446 rt2x00_get_field16(eeprom, 2447 EEPROM_LED_POLARITY_GPIO_0)); 2448 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, 2449 rt2x00_get_field16(eeprom, 2450 EEPROM_LED_POLARITY_GPIO_1)); 2451 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, 2452 rt2x00_get_field16(eeprom, 2453 EEPROM_LED_POLARITY_GPIO_2)); 2454 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, 2455 rt2x00_get_field16(eeprom, 2456 EEPROM_LED_POLARITY_GPIO_3)); 2457 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, 2458 rt2x00_get_field16(eeprom, 2459 EEPROM_LED_POLARITY_GPIO_4)); 2460 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, 2461 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); 2462 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, 2463 rt2x00_get_field16(eeprom, 2464 EEPROM_LED_POLARITY_RDY_G)); 2465 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, 2466 rt2x00_get_field16(eeprom, 2467 EEPROM_LED_POLARITY_RDY_A)); 2468#endif /* CONFIG_RT2X00_LIB_LEDS */ 2469 2470 return 0; 2471} 2472 2473/* 2474 * RF value list for RF5225 & RF5325 2475 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled 2476 */ 2477static const struct rf_channel rf_vals_noseq[] = { 2478 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, 2479 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, 2480 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, 2481 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, 2482 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, 2483 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, 2484 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, 2485 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, 2486 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, 2487 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, 2488 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, 2489 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, 2490 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, 2491 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, 2492 2493 /* 802.11 UNI / HyperLan 2 */ 2494 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 }, 2495 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 }, 2496 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b }, 2497 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 }, 2498 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b }, 2499 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 }, 2500 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 }, 2501 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b }, 2502 2503 /* 802.11 HyperLan 2 */ 2504 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 }, 2505 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b }, 2506 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 }, 2507 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b }, 2508 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 }, 2509 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 }, 2510 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b }, 2511 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 }, 2512 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b }, 2513 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 }, 2514 2515 /* 802.11 UNII */ 2516 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 }, 2517 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f }, 2518 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 }, 2519 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 }, 2520 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f }, 2521 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 }, 2522 2523 /* MMAC(Japan)J52 ch 34,38,42,46 */ 2524 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b }, 2525 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 }, 2526 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b }, 2527 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 }, 2528}; 2529 2530/* 2531 * RF value list for RF5225 & RF5325 2532 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled 2533 */ 2534static const struct rf_channel rf_vals_seq[] = { 2535 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, 2536 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, 2537 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, 2538 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, 2539 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, 2540 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, 2541 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, 2542 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, 2543 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, 2544 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, 2545 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, 2546 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, 2547 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, 2548 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, 2549 2550 /* 802.11 UNI / HyperLan 2 */ 2551 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 }, 2552 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 }, 2553 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b }, 2554 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b }, 2555 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 }, 2556 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 }, 2557 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 }, 2558 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b }, 2559 2560 /* 802.11 HyperLan 2 */ 2561 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 }, 2562 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 }, 2563 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 }, 2564 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 }, 2565 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 }, 2566 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 }, 2567 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b }, 2568 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b }, 2569 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 }, 2570 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 }, 2571 2572 /* 802.11 UNII */ 2573 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 }, 2574 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b }, 2575 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b }, 2576 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 }, 2577 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 }, 2578 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 }, 2579 2580 /* MMAC(Japan)J52 ch 34,38,42,46 */ 2581 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b }, 2582 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 }, 2583 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b }, 2584 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 }, 2585}; 2586 2587static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 2588{ 2589 struct hw_mode_spec *spec = &rt2x00dev->spec; 2590 struct channel_info *info; 2591 char *tx_power; 2592 unsigned int i; 2593 2594 /* 2595 * Disable powersaving as default. 2596 */ 2597 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 2598 2599 /* 2600 * Initialize all hw fields. 2601 */ 2602 rt2x00dev->hw->flags = 2603 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 2604 IEEE80211_HW_SIGNAL_DBM | 2605 IEEE80211_HW_SUPPORTS_PS | 2606 IEEE80211_HW_PS_NULLFUNC_STACK; 2607 2608 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 2609 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 2610 rt2x00_eeprom_addr(rt2x00dev, 2611 EEPROM_MAC_ADDR_0)); 2612 2613 /* 2614 * As rt61 has a global fallback table we cannot specify 2615 * more then one tx rate per frame but since the hw will 2616 * try several rates (based on the fallback table) we should 2617 * still initialize max_rates to the maximum number of rates 2618 * we are going to try. Otherwise mac80211 will truncate our 2619 * reported tx rates and the rc algortihm will end up with 2620 * incorrect data. 2621 */ 2622 rt2x00dev->hw->max_rates = 7; 2623 rt2x00dev->hw->max_rate_tries = 1; 2624 2625 /* 2626 * Initialize hw_mode information. 2627 */ 2628 spec->supported_bands = SUPPORT_BAND_2GHZ; 2629 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 2630 2631 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) { 2632 spec->num_channels = 14; 2633 spec->channels = rf_vals_noseq; 2634 } else { 2635 spec->num_channels = 14; 2636 spec->channels = rf_vals_seq; 2637 } 2638 2639 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) { 2640 spec->supported_bands |= SUPPORT_BAND_5GHZ; 2641 spec->num_channels = ARRAY_SIZE(rf_vals_seq); 2642 } 2643 2644 /* 2645 * Create channel information array 2646 */ 2647 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); 2648 if (!info) 2649 return -ENOMEM; 2650 2651 spec->channels_info = info; 2652 2653 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); 2654 for (i = 0; i < 14; i++) { 2655 info[i].max_power = MAX_TXPOWER; 2656 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); 2657 } 2658 2659 if (spec->num_channels > 14) { 2660 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); 2661 for (i = 14; i < spec->num_channels; i++) { 2662 info[i].max_power = MAX_TXPOWER; 2663 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); 2664 } 2665 } 2666 2667 return 0; 2668} 2669 2670static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev) 2671{ 2672 int retval; 2673 2674 /* 2675 * Disable power saving. 2676 */ 2677 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); 2678 2679 /* 2680 * Allocate eeprom data. 2681 */ 2682 retval = rt61pci_validate_eeprom(rt2x00dev); 2683 if (retval) 2684 return retval; 2685 2686 retval = rt61pci_init_eeprom(rt2x00dev); 2687 if (retval) 2688 return retval; 2689 2690 /* 2691 * Initialize hw specifications. 2692 */ 2693 retval = rt61pci_probe_hw_mode(rt2x00dev); 2694 if (retval) 2695 return retval; 2696 2697 /* 2698 * This device has multiple filters for control frames, 2699 * but has no a separate filter for PS Poll frames. 2700 */ 2701 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags); 2702 2703 /* 2704 * This device requires firmware and DMA mapped skbs. 2705 */ 2706 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); 2707 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); 2708 if (!modparam_nohwcrypt) 2709 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); 2710 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); 2711 2712 /* 2713 * Set the rssi offset. 2714 */ 2715 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 2716 2717 return 0; 2718} 2719 2720/* 2721 * IEEE80211 stack callback functions. 2722 */ 2723static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, 2724 const struct ieee80211_tx_queue_params *params) 2725{ 2726 struct rt2x00_dev *rt2x00dev = hw->priv; 2727 struct data_queue *queue; 2728 struct rt2x00_field32 field; 2729 int retval; 2730 u32 reg; 2731 u32 offset; 2732 2733 /* 2734 * First pass the configuration through rt2x00lib, that will 2735 * update the queue settings and validate the input. After that 2736 * we are free to update the registers based on the value 2737 * in the queue parameter. 2738 */ 2739 retval = rt2x00mac_conf_tx(hw, queue_idx, params); 2740 if (retval) 2741 return retval; 2742 2743 /* 2744 * We only need to perform additional register initialization 2745 * for WMM queues. 2746 */ 2747 if (queue_idx >= 4) 2748 return 0; 2749 2750 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 2751 2752 /* Update WMM TXOP register */ 2753 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); 2754 field.bit_offset = (queue_idx & 1) * 16; 2755 field.bit_mask = 0xffff << field.bit_offset; 2756 2757 rt2x00pci_register_read(rt2x00dev, offset, ®); 2758 rt2x00_set_field32(®, field, queue->txop); 2759 rt2x00pci_register_write(rt2x00dev, offset, reg); 2760 2761 /* Update WMM registers */ 2762 field.bit_offset = queue_idx * 4; 2763 field.bit_mask = 0xf << field.bit_offset; 2764 2765 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, ®); 2766 rt2x00_set_field32(®, field, queue->aifs); 2767 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg); 2768 2769 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, ®); 2770 rt2x00_set_field32(®, field, queue->cw_min); 2771 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg); 2772 2773 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, ®); 2774 rt2x00_set_field32(®, field, queue->cw_max); 2775 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg); 2776 2777 return 0; 2778} 2779 2780static u64 rt61pci_get_tsf(struct ieee80211_hw *hw) 2781{ 2782 struct rt2x00_dev *rt2x00dev = hw->priv; 2783 u64 tsf; 2784 u32 reg; 2785 2786 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®); 2787 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; 2788 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®); 2789 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); 2790 2791 return tsf; 2792} 2793 2794static const struct ieee80211_ops rt61pci_mac80211_ops = { 2795 .tx = rt2x00mac_tx, 2796 .start = rt2x00mac_start, 2797 .stop = rt2x00mac_stop, 2798 .add_interface = rt2x00mac_add_interface, 2799 .remove_interface = rt2x00mac_remove_interface, 2800 .config = rt2x00mac_config, 2801 .configure_filter = rt2x00mac_configure_filter, 2802 .set_key = rt2x00mac_set_key, 2803 .sw_scan_start = rt2x00mac_sw_scan_start, 2804 .sw_scan_complete = rt2x00mac_sw_scan_complete, 2805 .get_stats = rt2x00mac_get_stats, 2806 .bss_info_changed = rt2x00mac_bss_info_changed, 2807 .conf_tx = rt61pci_conf_tx, 2808 .get_tsf = rt61pci_get_tsf, 2809 .rfkill_poll = rt2x00mac_rfkill_poll, 2810}; 2811 2812static const struct rt2x00lib_ops rt61pci_rt2x00_ops = { 2813 .irq_handler = rt61pci_interrupt, 2814 .irq_handler_thread = rt61pci_interrupt_thread, 2815 .probe_hw = rt61pci_probe_hw, 2816 .get_firmware_name = rt61pci_get_firmware_name, 2817 .check_firmware = rt61pci_check_firmware, 2818 .load_firmware = rt61pci_load_firmware, 2819 .initialize = rt2x00pci_initialize, 2820 .uninitialize = rt2x00pci_uninitialize, 2821 .get_entry_state = rt61pci_get_entry_state, 2822 .clear_entry = rt61pci_clear_entry, 2823 .set_device_state = rt61pci_set_device_state, 2824 .rfkill_poll = rt61pci_rfkill_poll, 2825 .link_stats = rt61pci_link_stats, 2826 .reset_tuner = rt61pci_reset_tuner, 2827 .link_tuner = rt61pci_link_tuner, 2828 .write_tx_desc = rt61pci_write_tx_desc, 2829 .write_beacon = rt61pci_write_beacon, 2830 .kick_tx_queue = rt61pci_kick_tx_queue, 2831 .kill_tx_queue = rt61pci_kill_tx_queue, 2832 .fill_rxdone = rt61pci_fill_rxdone, 2833 .config_shared_key = rt61pci_config_shared_key, 2834 .config_pairwise_key = rt61pci_config_pairwise_key, 2835 .config_filter = rt61pci_config_filter, 2836 .config_intf = rt61pci_config_intf, 2837 .config_erp = rt61pci_config_erp, 2838 .config_ant = rt61pci_config_ant, 2839 .config = rt61pci_config, 2840}; 2841 2842static const struct data_queue_desc rt61pci_queue_rx = { 2843 .entry_num = RX_ENTRIES, 2844 .data_size = DATA_FRAME_SIZE, 2845 .desc_size = RXD_DESC_SIZE, 2846 .priv_size = sizeof(struct queue_entry_priv_pci), 2847}; 2848 2849static const struct data_queue_desc rt61pci_queue_tx = { 2850 .entry_num = TX_ENTRIES, 2851 .data_size = DATA_FRAME_SIZE, 2852 .desc_size = TXD_DESC_SIZE, 2853 .priv_size = sizeof(struct queue_entry_priv_pci), 2854}; 2855 2856static const struct data_queue_desc rt61pci_queue_bcn = { 2857 .entry_num = 4 * BEACON_ENTRIES, 2858 .data_size = 0, /* No DMA required for beacons */ 2859 .desc_size = TXINFO_SIZE, 2860 .priv_size = sizeof(struct queue_entry_priv_pci), 2861}; 2862 2863static const struct rt2x00_ops rt61pci_ops = { 2864 .name = KBUILD_MODNAME, 2865 .max_sta_intf = 1, 2866 .max_ap_intf = 4, 2867 .eeprom_size = EEPROM_SIZE, 2868 .rf_size = RF_SIZE, 2869 .tx_queues = NUM_TX_QUEUES, 2870 .extra_tx_headroom = 0, 2871 .rx = &rt61pci_queue_rx, 2872 .tx = &rt61pci_queue_tx, 2873 .bcn = &rt61pci_queue_bcn, 2874 .lib = &rt61pci_rt2x00_ops, 2875 .hw = &rt61pci_mac80211_ops, 2876#ifdef CONFIG_RT2X00_LIB_DEBUGFS 2877 .debugfs = &rt61pci_rt2x00debug, 2878#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 2879}; 2880 2881/* 2882 * RT61pci module information. 2883 */ 2884static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = { 2885 /* RT2561s */ 2886 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) }, 2887 /* RT2561 v2 */ 2888 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) }, 2889 /* RT2661 */ 2890 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) }, 2891 { 0, } 2892}; 2893 2894MODULE_AUTHOR(DRV_PROJECT); 2895MODULE_VERSION(DRV_VERSION); 2896MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver."); 2897MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 " 2898 "PCI & PCMCIA chipset based cards"); 2899MODULE_DEVICE_TABLE(pci, rt61pci_device_table); 2900MODULE_FIRMWARE(FIRMWARE_RT2561); 2901MODULE_FIRMWARE(FIRMWARE_RT2561s); 2902MODULE_FIRMWARE(FIRMWARE_RT2661); 2903MODULE_LICENSE("GPL"); 2904 2905static struct pci_driver rt61pci_driver = { 2906 .name = KBUILD_MODNAME, 2907 .id_table = rt61pci_device_table, 2908 .probe = rt2x00pci_probe, 2909 .remove = __devexit_p(rt2x00pci_remove), 2910 .suspend = rt2x00pci_suspend, 2911 .resume = rt2x00pci_resume, 2912}; 2913 2914static int __init rt61pci_init(void) 2915{ 2916 return pci_register_driver(&rt61pci_driver); 2917} 2918 2919static void __exit rt61pci_exit(void) 2920{ 2921 pci_unregister_driver(&rt61pci_driver); 2922} 2923 2924module_init(rt61pci_init); 2925module_exit(rt61pci_exit); 2926