Lines Matching refs:rt2x00_set_field32
99 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value);
100 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
101 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
102 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0);
103 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
128 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
129 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
130 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1);
131 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
156 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value);
157 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
158 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1);
159 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
184 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
185 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0);
186 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
211 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value);
212 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0);
213 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0);
214 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1);
242 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
243 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
244 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
245 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
249 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
392 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
393 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
394 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
395 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
396 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
438 rt2x00_set_field32(&word, TXWI_W0_FRAG,
440 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
441 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
442 rt2x00_set_field32(&word, TXWI_W0_TS,
444 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
446 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
447 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
448 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
449 rt2x00_set_field32(&word, TXWI_W0_BW,
451 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
453 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
454 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
458 rt2x00_set_field32(&word, TXWI_W1_ACK,
460 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
462 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
463 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
466 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
468 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
584 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
620 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
621 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
622 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
737 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, *delay_on);
738 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, *delay_off);
771 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB,
778 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER,
780 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
782 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX,
784 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
786 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
849 rt2x00_set_field32(®, field,
913 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR,
915 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR,
917 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME,
919 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
920 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1);
921 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST,
923 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0);
924 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1);
925 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK,
927 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END,
929 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK,
931 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS,
933 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS,
935 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL,
937 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 1);
938 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 0);
939 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL,
960 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
961 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync);
962 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE,
971 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER,
979 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
988 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3);
989 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1003 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY,
1005 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE,
1010 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL,
1019 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
1023 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs);
1027 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
1104 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1107 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1110 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1111 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1113 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1122 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1128 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
1131 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1137 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
1140 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
1142 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
1146 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1245 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1246 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14);
1247 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14);
1254 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1255 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1260 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1261 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1264 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1265 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1266 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1267 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1268 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1269 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1338 rt2x00_set_field32(®, TX_PWR_CFG_RATE0,
1346 rt2x00_set_field32(®, TX_PWR_CFG_RATE1,
1354 rt2x00_set_field32(®, TX_PWR_CFG_RATE2,
1362 rt2x00_set_field32(®, TX_PWR_CFG_RATE3,
1374 rt2x00_set_field32(®, TX_PWR_CFG_RATE4,
1382 rt2x00_set_field32(®, TX_PWR_CFG_RATE5,
1390 rt2x00_set_field32(®, TX_PWR_CFG_RATE6,
1398 rt2x00_set_field32(®, TX_PWR_CFG_RATE7,
1414 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT,
1416 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT,
1433 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1434 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1436 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1442 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1443 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1444 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1545 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1546 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1547 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1548 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1549 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1557 rt2x00_set_field32(®, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1558 rt2x00_set_field32(®, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1559 rt2x00_set_field32(®, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1560 rt2x00_set_field32(®, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1564 rt2x00_set_field32(®, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1565 rt2x00_set_field32(®, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1566 rt2x00_set_field32(®, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1567 rt2x00_set_field32(®, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1576 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
1577 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
1578 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0);
1579 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
1580 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
1581 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1587 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1588 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1629 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1630 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0);
1631 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1632 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0);
1633 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0);
1634 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1635 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0);
1636 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0);
1640 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1641 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1642 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1646 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1650 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2);
1652 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1);
1653 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0);
1654 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0);
1658 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70);
1659 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30);
1660 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3);
1661 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3);
1662 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3);
1663 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3);
1664 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1);
1670 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1671 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1672 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1673 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1674 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0);
1675 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1679 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1);
1680 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1681 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1682 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0);
1683 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1684 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1685 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1689 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3);
1690 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0);
1691 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV, 1);
1692 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1693 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1694 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1695 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1696 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1697 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1698 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1);
1702 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3);
1703 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1704 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV, 1);
1705 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1706 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1707 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1708 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1709 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1710 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1711 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1);
1715 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1716 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0);
1717 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV, 1);
1718 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1719 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1720 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1721 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1722 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1723 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1724 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0);
1728 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1729 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL,
1731 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV, 1);
1732 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1733 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1734 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1735 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1736 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1737 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1738 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0);
1742 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1743 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0);
1744 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV, 1);
1745 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1746 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1747 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1748 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1749 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1750 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1751 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0);
1755 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1756 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0);
1757 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV, 1);
1758 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1759 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1760 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1761 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1762 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1763 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1764 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0);
1771 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1772 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1773 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1774 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1775 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1776 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1777 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1778 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1779 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1787 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1788 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES,
1790 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0);
1803 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1804 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
1805 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1806 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314);
1807 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1842 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30);
1847 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0);
1848 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0);
1849 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1);
1850 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2);
1851 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3);
1852 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4);
1853 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5);
1854 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6);
1858 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8);
1859 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8);
1860 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9);
1861 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10);
1862 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11);
1863 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12);
1864 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13);
1865 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14);
1869 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1870 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1871 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1872 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1873 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1874 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1875 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1876 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1880 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0);
1881 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0);
1882 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1);
1883 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2);
1902 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2224 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
2225 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2236 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
2241 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2243 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2248 rt2x00_set_field32(®, GPIO_SWITCH_5, 0);
2292 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1);
2380 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i);
2381 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0);
2382 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1);
2933 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value);
2937 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled);
2941 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2945 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled);
2949 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled);
2953 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled);
2957 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled);
2999 rt2x00_set_field32(®, field, queue->txop);
3007 rt2x00_set_field32(®, field, queue->aifs);
3011 rt2x00_set_field32(®, field, queue->cw_min);
3015 rt2x00_set_field32(®, field, queue->cw_max);
3022 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
3023 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs);
3024 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3025 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max);