Lines Matching refs:rt2x00_set_field32
80 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
81 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
82 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
83 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
108 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
109 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
110 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
135 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
136 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
137 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
138 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
160 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
161 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
162 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
163 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
167 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
168 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
196 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
197 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
198 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
200 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
297 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on);
298 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off);
375 rt2x00_set_field32(®, field, crypto->cipher);
382 rt2x00_set_field32(®, field, crypto->cipher);
529 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
531 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
533 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
535 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
537 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
540 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
541 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
543 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
544 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS,
571 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
572 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync);
573 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
579 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
588 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3);
602 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
603 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
607 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
608 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
615 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
620 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time);
624 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs);
625 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
626 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs);
721 rt2x00_set_field32(®, MAC_CSR13_BIT4, p1);
722 rt2x00_set_field32(®, MAC_CSR13_BIT12, 0);
724 rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2);
725 rt2x00_set_field32(®, MAC_CSR13_BIT11, 0);
823 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
825 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
872 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
873 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
929 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
930 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
931 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
932 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT,
934 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT,
949 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN,
951 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP,
953 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5);
956 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0);
959 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1);
969 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0);
970 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
971 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0);
972 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0);
1209 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1219 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1220 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
1226 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
1229 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
1253 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1254 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1258 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1259 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1263 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1297 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1302 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1306 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1307 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1321 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
1323 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
1325 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
1327 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
1332 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
1338 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
1344 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
1350 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
1356 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
1361 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1362 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
1364 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1369 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
1374 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
1375 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
1376 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
1377 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
1381 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1382 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1383 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1384 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1388 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
1399 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
1400 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
1401 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1405 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1406 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
1407 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1408 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
1409 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1410 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
1411 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1412 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
1419 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
1420 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
1421 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
1422 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
1423 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
1424 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
1425 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
1426 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
1433 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
1434 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
1435 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
1436 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
1437 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
1438 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
1442 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1443 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1444 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1445 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1449 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1450 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1451 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1452 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1456 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0);
1457 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
1458 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0);
1459 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
1460 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1461 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1469 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1522 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1523 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1527 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1528 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1532 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1611 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1641 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
1642 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
1643 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1644 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1648 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
1649 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
1650 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
1651 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
1652 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
1653 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
1654 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
1655 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
1675 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1698 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1699 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1777 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1778 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1779 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1780 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1781 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1782 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1784 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1788 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1789 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1790 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1791 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1800 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1801 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1803 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1805 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1810 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1815 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1826 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1827 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1828 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1830 rt2x00_set_field32(&word, TXD_W0_ACK,
1832 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1834 rt2x00_set_field32(&word, TXD_W0_OFDM,
1836 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1837 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1839 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1841 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1843 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1844 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1845 rt2x00_set_field32(&word, TXD_W0_BURST,
1847 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1874 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1904 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
1905 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
1906 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1922 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1923 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1924 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1925 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1940 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE));
1941 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK));
1942 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI));
1943 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO));
2758 rt2x00_set_field32(®, field, queue->txop);
2766 rt2x00_set_field32(®, field, queue->aifs);
2770 rt2x00_set_field32(®, field, queue->cw_min);
2774 rt2x00_set_field32(®, field, queue->cw_max);