wireless/rt2x00/rt2400pci.c

71 		rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
72 		rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
73 		rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
74 		rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
99 		rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
100 		rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
101 		rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
126 		rt2x00_set_field32(&reg, RFCSR_VALUE, value);
127 		rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
128 		rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
129 		rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
158 	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
159 	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
160 	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
162 	rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
223 		rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
225 		rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
239 	rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
240 	rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
272 	rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
274 	rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
276 	rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
278 	rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
280 	rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
283 	rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
301 		rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
308 		rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
309 		rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
310 		rt2x00_set_field32(&reg, CSR14_TBCN, 1);
335 	rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
336 	rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
337 	rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
338 	rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
342 	rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
343 	rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
344 	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
348 	rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
349 	rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
350 	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
354 	rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
355 	rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
356 	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
360 	rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
361 	rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
362 	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
368 	rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
372 	rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
373 	rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
377 	rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
378 	rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
382 	rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
383 	rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
445 	rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
446 	rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
478 	rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
479 	rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
501 	rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
503 	rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
518 		rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
520 		rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
524 		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
527 		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
531 		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
559 	rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
560 	rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
649 		rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
653 		rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
657 		rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
661 		rt2x00_set_field32(&word, TXD_W0_VALID, 0);
662 		rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
676 	rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
677 	rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
678 	rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
679 	rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
684 	rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
690 	rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
696 	rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
702 	rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
707 	rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
708 	rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
713 	rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
730 	rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
731 	rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
732 	rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
736 	rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
741 	rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
742 	rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
743 	rt2x00_set_field32(&reg, CSR14_TBCN, 0);
744 	rt2x00_set_field32(&reg, CSR14_TCFP, 0);
745 	rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
746 	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
747 	rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
748 	rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
754 	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
755 	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
756 	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
757 	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
761 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
762 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
763 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
764 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
765 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
766 	rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
778 	rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
782 	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
783 	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
784 	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
785 	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
789 	rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
790 	rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
791 	rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
795 	rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
796 	rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
873 	rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
900 	rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
901 	rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
902 	rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
903 	rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
904 	rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
941 	rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
942 	rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
943 	rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
944 	rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1023 	rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1027 	rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1028 	rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1032 	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1033 	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1034 	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1035 	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1036 	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1037 	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1041 	rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1042 	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1043 	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1044 	rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1045 	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1046 	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1055 	rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1056 	rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1057 	rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1059 	rt2x00_set_field32(&word, TXD_W0_ACK,
1061 	rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1063 	rt2x00_set_field32(&word, TXD_W0_RTS,
1065 	rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1066 	rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1091 	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1109 	rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1110 	rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1111 	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1121 	rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1122 	rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1123 	rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1136 		rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);