Lines Matching refs:rt2x00_set_field32
79 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
80 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
81 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
82 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
107 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
108 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
109 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
134 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
139 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS,
142 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
143 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
245 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on);
246 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off);
323 rt2x00_set_field32(®, field, crypto->cipher);
330 rt2x00_set_field32(®, field, crypto->cipher);
480 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
482 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
484 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
486 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
488 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
491 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
492 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
494 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
495 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS,
522 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
523 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync);
524 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
530 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
539 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3);
553 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
554 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
558 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
559 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
566 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
571 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time);
575 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs);
576 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
577 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs);
726 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
728 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
766 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
767 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
819 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
820 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
821 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
822 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT,
824 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT,
839 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN,
841 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP,
843 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5);
846 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0);
849 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1);
856 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0);
857 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
858 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0);
859 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0);
1111 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
1112 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
1113 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1117 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1118 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
1119 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1120 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
1121 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1122 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
1123 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1124 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
1131 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
1132 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
1133 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
1134 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
1135 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
1136 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
1137 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
1138 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
1145 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
1146 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
1147 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
1148 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
1149 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
1150 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
1154 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1155 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1156 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1157 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1161 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1162 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1163 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1164 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1168 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0);
1169 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
1170 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0);
1171 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
1172 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1173 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1179 rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1199 rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1);
1207 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1234 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1235 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1239 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1240 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1244 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1324 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1363 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1364 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1441 rt2x00_set_field32(&word, TXD_W0_BURST,
1443 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1444 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1446 rt2x00_set_field32(&word, TXD_W0_ACK,
1448 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1450 rt2x00_set_field32(&word, TXD_W0_OFDM,
1452 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1453 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1455 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1457 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1459 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1460 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1461 rt2x00_set_field32(&word, TXD_W0_BURST2,
1463 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1467 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1468 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1469 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1470 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1471 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1472 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1477 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1478 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1479 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1480 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1489 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1491 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1517 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1551 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
1552 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
1553 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
2188 rt2x00_set_field32(®, field, queue->txop);
2196 rt2x00_set_field32(®, field, queue->aifs);
2200 rt2x00_set_field32(®, field, queue->cw_min);
2204 rt2x00_set_field32(®, field, queue->cw_max);