Lines Matching refs:rt2x00_set_field32
71 rt2x00_set_field32(®, BBPCSR_VALUE, value);
72 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
73 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
74 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
99 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
100 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
101 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
126 rt2x00_set_field32(®, RFCSR_VALUE, value);
127 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
128 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
129 rt2x00_set_field32(®, RFCSR_BUSY, 1);
158 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
159 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
160 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
162 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
223 rt2x00_set_field32(®, LEDCSR_LINK, enabled);
225 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled);
239 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on);
240 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off);
273 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
275 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
277 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
279 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
281 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
284 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
285 rt2x00_set_field32(®, RXCSR0_DROP_MCAST,
287 rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0);
306 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
307 rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min);
314 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
315 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
316 rt2x00_set_field32(®, CSR14_TBCN, 1);
341 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x162);
342 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0xa2);
343 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
344 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
348 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
349 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
350 rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
354 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
355 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
356 rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
360 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
361 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
362 rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
366 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
367 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
368 rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
374 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time);
378 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
379 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
383 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs);
384 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs);
388 rt2x00_set_field32(®, CSR19_DIFS, erp->difs);
389 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs);
417 rt2x00_set_field32(®, BBPCSR1_CCK, 0);
418 rt2x00_set_field32(®, BBPCSR1_OFDM, 0);
423 rt2x00_set_field32(®, BBPCSR1_CCK, 2);
424 rt2x00_set_field32(®, BBPCSR1_OFDM, 2);
446 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1);
447 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1);
455 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0);
456 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0);
472 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
479 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
480 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
520 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
524 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
539 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
549 rt2x00_set_field32(®, CSR11_LONG_RETRY,
551 rt2x00_set_field32(®, CSR11_SHORT_RETRY,
566 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN,
568 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP,
572 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
575 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1);
579 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
738 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
742 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
746 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
747 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
761 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
762 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
763 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
764 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
769 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
775 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
781 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
787 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
792 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
793 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
798 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
815 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
816 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
817 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
821 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
829 rt2x00_set_field32(®, CSR11_CW_SELECT, 0);
833 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
834 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
835 rt2x00_set_field32(®, CSR14_TBCN, 0);
836 rt2x00_set_field32(®, CSR14_TCFP, 0);
837 rt2x00_set_field32(®, CSR14_TATIMW, 0);
838 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
839 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0);
840 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0);
846 rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10);
847 rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1);
848 rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11);
849 rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1);
850 rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13);
851 rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1);
852 rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12);
853 rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1);
857 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112);
858 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56);
859 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20);
860 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10);
864 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45);
865 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37);
866 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33);
867 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29);
871 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29);
872 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25);
873 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25);
874 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25);
878 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */
879 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
880 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */
881 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
882 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
883 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
884 rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */
885 rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1);
889 rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0);
890 rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0);
891 rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3);
892 rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1);
893 rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1);
894 rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1);
895 rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1);
910 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
914 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
915 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26);
916 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1);
917 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
918 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26);
919 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1);
927 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
928 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
929 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
933 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
934 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
1027 rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
1054 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
1055 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
1056 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
1057 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
1058 rt2x00_set_field32(®, CSR8_RXDONE, mask);
1095 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
1096 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
1097 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
1098 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1177 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1181 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1182 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1183 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1184 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1188 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1189 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1190 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1191 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1195 rt2x00_set_field32(&word, TXD_W10_RTS,
1205 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1206 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1207 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1209 rt2x00_set_field32(&word, TXD_W0_ACK,
1211 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1213 rt2x00_set_field32(&word, TXD_W0_OFDM,
1215 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1216 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1217 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1219 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1220 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1244 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
1262 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
1263 rt2x00_set_field32(®, CSR14_TBCN, 1);
1264 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1274 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1275 rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1276 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1289 rt2x00_set_field32(®, TXCSR0_ABORT, 1);