Searched refs:chip (Results 1 - 25 of 64) sorted by relevance

123

/freebsd-9.3-release/sys/contrib/octeon-sdk/
H A Dcvmx-csr-db-support.c64 * Figure out which database to use for this chip. The passed
138 int chip = cvmx_db_get_chipindex(identifier); local
142 while (cvmx_csr_db_addresses[chip][i].name)
144 if (strcasecmp(name, cvmx_csr_db_addresses[chip][i].name) == 0)
145 return &(cvmx_csr_db_addresses[chip][i]);
152 static void __cvmx_csr_db_decode_csr(int chip, int index, uint64_t value) argument
155 int csr = cvmx_csr_db_addresses[chip][index].csroff;
156 PRINTF("%s(0x%016llx) = 0x%016llx\n", cvmx_csr_db_addresses[chip][index].name, (unsigned long long)cvmx_csr_db_addresses[chip][index].address, (unsigned long long)value);
157 for (field=cvmx_csr_db[chip][cs
185 int chip = cvmx_db_get_chipindex(identifier); local
208 int chip = cvmx_db_get_chipindex(identifier); local
233 int chip = cvmx_db_get_chipindex(identifier); local
[all...]
H A Dcvmx-nand.c94 ** parameter page of the ONFI flash chip. */
142 * Array indexed by bootbus chip select with information
380 /* Internal helper function to set chip configuration to use default values */
381 static void __set_chip_defaults(int chip, int clocks_us) argument
385 cvmx_nand_state[chip].page_size = cvmx_nand_default.page_size; /* NAND page size in bytes */
386 cvmx_nand_state[chip].oob_size = cvmx_nand_default.oob_size; /* NAND OOB (spare) size in bytes (per page) */
387 cvmx_nand_state[chip].pages_per_block = cvmx_nand_default.pages_per_block;
388 cvmx_nand_state[chip].blocks = cvmx_nand_default.blocks;
389 cvmx_nand_state[chip].onfi_timing = cvmx_nand_default.onfi_timing;
390 __set_onfi_timing_mode(cvmx_nand_state[chip]
403 __wait_for_busy_done(int chip) argument
459 int chip; local
784 int chip; local
811 cvmx_nand_set_timing(int chip, int tim_mult, int tim_par[8], int clen[4], int alen[4], int rdn[4], int wrn[2]) argument
923 __cvmx_nand_get_column_bits(int chip) argument
938 __cvmx_nand_get_row_bits(int chip) argument
953 __cvmx_nand_get_address_cycles(int chip) argument
977 __cvmx_nand_build_pre_cmd(int chip, int cmd_data, int num_address_cycles, uint64_t nand_address, int cmd_data2) argument
1130 __cvmx_nand_setup_dma(int chip, int is_write, uint64_t buffer_address, int buffer_length) argument
1200 __cvmx_nand_low_level_read(int chip, int nand_command1, int address_cycles, uint64_t nand_address, int nand_command2, uint64_t buffer_address, int buffer_length) argument
1294 cvmx_nand_page_read(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length) argument
1341 cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_t buffer_address) argument
1425 cvmx_nand_block_erase(int chip, uint64_t nand_address) argument
1487 cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length) argument
1528 cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_length) argument
1562 cvmx_nand_get_status(int chip) argument
1593 cvmx_nand_get_page_size(int chip) argument
1612 cvmx_nand_get_oob_size(int chip) argument
1632 cvmx_nand_get_pages_per_block(int chip) argument
1651 cvmx_nand_get_blocks(int chip) argument
1670 cvmx_nand_reset(int chip) argument
[all...]
H A Dcvmx-nand.h62 * Octeon's NAND controller assumes a single NAND chip is connected to a boot
63 * bus chip select. Throughout this API, NAND chips are referred to by the chip
64 * select they are connected to (0-7). Chip select 0 will only be a NAND chip
191 uint64_t chip : 3; member in struct:__anon6523
494 * Each bit in this parameter represents a chip select that might
495 * contain NAND flash. Any chip select present in this bitmask may
497 * let the API probe all 8 chip selects.
507 * for NAND chips that do not identify themselves in a way that allows autoconfiguration. (ONFI chip with
538 * Returns a bitmask representing the chip select
[all...]
/freebsd-9.3-release/sys/mips/atheros/
H A Dar71xx_setup.c74 char *chip = "????"; local
92 chip = "7130";
97 chip = "7141";
102 chip = "7161";
109 chip = "7240";
116 chip = "7241";
123 chip = "7242";
136 chip = "9130";
141 chip = "9132";
148 panic("ar71xx: unknown chip i
[all...]
/freebsd-9.3-release/sys/dev/utopia/
H A Dutopia.h141 const struct utopia_chip *chip; /* chip operations */ member in struct:utopia
146 /* type and name of the chip */
153 /* reset chip to known state */
192 #define utopia_reset(S) ((S)->chip->reset((S)))
193 #define utopia_set_sdh(S, SDH) ((S)->chip->set_sdh((S), (SDH)))
194 #define utopia_set_unass(S, U) ((S)->chip->set_unass((S), (U)))
195 #define utopia_set_noscramb(S, N) ((S)->chip->set_noscramb((S), (N)))
196 #define utopia_update_carrier(S) ((S)->chip->update_carrier((S)))
197 #define utopia_update_stats(S) ((S)->chip
[all...]
H A Dutopia.c98 utp->chip->name, reg, nreg, err);
105 utp->chip->name, reg, nreg, err);
231 if (utp->chip->type != UTP_TYPE_UNKNOWN && utp->state & UTP_ST_ACTIVE) {
268 if (utp->chip->type != UTP_TYPE_UNKNOWN && utp->state & UTP_ST_ACTIVE) {
338 * Try to find out what chip we have
346 utp->chip = &utopia_chip_622;
357 utp->chip = &utopia_chip_idt77155;
359 utp->chip = &utopia_chip_lite;
363 utp->chip = &utopia_chip_ultra;
368 utp->chip
[all...]
/freebsd-9.3-release/sys/dev/ata/chipsets/
H A Data-acerlabs.c94 if (!(ctlr->chip = ata_match_chip(dev, ids)))
113 switch (ctlr->chip->cfg2) {
115 ctlr->channels = ctlr->chip->cfg1;
122 if ((ctlr->chip->chipid == ATA_ALI_5288) &&
149 if (ctlr->chip->chiprev < 0xc7)
155 (ctlr->chip->chiprev >= 0xc7 ? 0x03 : 0x01), 1);
158 if (ctlr->chip->chiprev <= 0xc4)
184 if (ctlr->chip->cfg2 == ALI_SATA) {
208 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip
[all...]
H A Data-amd.c81 if (!(ctlr->chip = ata_match_chip(dev, ids)))
98 if (ctlr->chip->cfg1 & AMD_BUG)
122 mode = min(mode, ctlr->chip->max_dma);
123 if (ctlr->chip->cfg1 & AMD_CABLE) {
153 if (ctlr->chip->cfg1 & AMD_CABLE)
H A Data-jmicron.c87 ctlr->chip = idx;
112 ctlr->channels = ctlr->chip->cfg2;
119 if (ctlr->chip->cfg1) {
130 ctlr->channels = ctlr->chip->cfg2;
151 mode = min(mode, ctlr->chip->max_dma);
H A Data-highpoint.c105 ctlr->chip = idx;
118 if (ctlr->chip->cfg2 == HPT_OLD) {
131 if (ctlr->chip->cfg1 < HPT_372)
154 if (ctlr->chip->cfg1 == HPT_366)
185 mode = min(mode, ctlr->chip->max_dma);
194 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
206 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) {
H A Data-nvidia.c181 if (!(ctlr->chip = ata_match_chip(dev, ids)))
185 if ((ctlr->chip->cfg1 & NVAHCI) &&
186 ((force_ahci == 1 && (ctlr->chip->cfg1 & NVNOFORCE) == 0) ||
202 if (ctlr->chip->cfg1 & NVAHCI) {
205 } else if (ctlr->chip->max_dma >= ATA_SA150) {
213 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010;
223 if (ctlr->chip->cfg1 & NVQ) {
292 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010;
293 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2);
297 if (ctlr->chip
[all...]
H A Data-via.c135 if (!(ctlr->chip = ata_find_chip(dev, ids, -99)))
139 if (!(ctlr->chip = ata_match_chip(dev, new_ids)))
157 if (ctlr->chip->cfg2 & VIAAHCI) {
162 if (ctlr->chip->cfg2 & VIASATA) {
170 if (ctlr->chip->max_dma >= ATA_SA150) {
179 if (ctlr->chip->cfg2 & VIABAR) {
189 if (ctlr->chip->cfg2 & VIACLK)
193 if (ctlr->chip->cfg2 & VIABUG)
222 if (ctlr->chip->cfg2 & VIABAR) {
257 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip
[all...]
H A Data-acard.c95 if (!(ctlr->chip = ata_match_chip(dev, ids)))
119 if (ctlr->chip->cfg1 == ATP_OLD) {
145 if (ctlr->chip->cfg1 == ATP_OLD) {
175 if (ctlr->chip->cfg1 == ATP_OLD &&
206 mode = min(mode, ctlr->chip->max_dma);
230 mode = min(mode, ctlr->chip->max_dma);
H A Data-promise.c211 ctlr->chip = idx;
225 switch (ctlr->chip->cfg1) {
253 if (ctlr->chip->cfg2 == PR_SX4X &&
266 if (ctlr->chip->cfg2 == PR_SX4X) {
315 switch (ctlr->chip->cfg2) {
347 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2))
376 if (ctlr->chip->cfg1 == PR_NEW) {
479 mode = min(mode, ctlr->chip->max_dma);
481 switch (ctlr->chip
[all...]
H A Data-ati.c105 if (!(ctlr->chip = ata_match_chip(dev, ids)))
110 switch (ctlr->chip->cfg1) {
140 if (ctlr->chip->cfg1 == ATI_AHCI) {
145 switch (ctlr->chip->chipid) {
222 mode = min(mode, ctlr->chip->max_dma);
H A Data-sis.c86 { ATA_SIS745, 0x00, SIS_100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
87 { ATA_SIS735, 0x00, SIS_100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
88 { ATA_SIS733, 0x00, SIS_100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
89 { ATA_SIS730, 0x00, SIS_100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
91 { ATA_SIS635, 0x00, SIS_100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
93 { ATA_SIS630, 0x30, SIS_100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
94 { ATA_SIS630, 0x00, SIS_66, 0, ATA_UDMA4, "630" }, /* 1chip */
95 { ATA_SIS620, 0x00, SIS_66, 0, ATA_UDMA4, "620" }, /* 1chip */
156 ctlr->chip = idx;
169 switch (ctlr->chip
[all...]
H A Data-adaptec.c73 if (!(ctlr->chip = ata_match_chip(dev, ids)))
H A Data-ite.c76 if (!(ctlr->chip = ata_match_chip(dev, ids)))
92 if (ctlr->chip->chipid == ATA_IT8213F) {
142 mode = min(mode, ctlr->chip->max_dma);
192 mode = min(mode, ctlr->chip->max_dma);
H A Data-intel.c238 if (!(ctlr->chip = ata_match_chip(dev, ids)))
261 if (ctlr->chip->chipid == ATA_I82371FB) {
266 else if (ctlr->chip->chipid == ATA_I31244) {
283 else if (ctlr->chip->chipid == ATA_ISCH) {
290 else if (ctlr->chip->max_dma < ATA_SA150) {
291 ctlr->channels = ctlr->chip->cfg2;
310 if ((ctlr->chip->cfg1 & INTEL_AHCI) &&
316 if ((ctlr->chip->cfg1 & INTEL_ICH7)) {
330 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 ||
338 (ctlr->chip
[all...]
H A Data-serverworks.c95 if (!(ctlr->chip = ata_match_chip(dev, ids)))
133 if (ctlr->chip->cfg1 == SWKS_MIO) {
140 ctlr->channels = ctlr->chip->cfg2;
148 else if (ctlr->chip->cfg1 == SWKS_33) {
168 (ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02, 1);
214 if (ctlr->chip->chipid == ATA_K2) {
243 /* chip does not reliably do 64K DMA transfers */
356 mode = min(mode, ctlr->chip->max_dma);
390 if (ctlr->chip->cfg1 != SWKS_33) {
H A Data-siliconimage.c112 if (!(ctlr->chip = ata_match_chip(dev, ids)))
128 switch (ctlr->chip->cfg1) {
159 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
172 if (ctlr->chip->chipid != ATA_SII0680 ||
177 if (ctlr->chip->cfg2 & SII_SETCLK) {
183 ctlr->chip->text);
187 if (ctlr->chip->cfg2 & SII_4CH) {
204 if (ctlr->chip->max_dma >= ATA_SA150) {
240 if (ctlr->chip->cfg2 & SII_INTR)
281 mode = min(mode, ctlr->chip
[all...]
/freebsd-9.3-release/sys/dev/drm/
H A Dsavage_drv.h96 /* these chip tags should match the ones in the 2D driver in savage_regs.h. */
113 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
115 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \
116 || (chip==S3_PROSAVAGE) \
117 || (chip==S3_TWISTER) \
118 || (chip==S3_PROSAVAGEDDR))
120 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chi
[all...]
/freebsd-9.3-release/cddl/lib/libdtrace/
H A Dsched.d38 chipid_t cpu_chip; /* chip identifier */
79 inline chipid_t chip = curcpu->cpu_chip;
80 #pragma D attributes Stable/Stable/Common chip
81 #pragma D binding "1.0" chip
/freebsd-9.3-release/sys/dev/advansys/
H A Dadw_pci.c321 adw->chip = ADW_CHIP_NONE;
338 adw->chip = ADW_CHIP_ASC3550;
375 adw->chip = ADW_CHIP_ASC38C0800;
391 adw->chip = ADW_CHIP_ASC38C1600;
/freebsd-9.3-release/sys/dev/aic7xxx/
H A Daic7770.c102 /* Generic chip probes for devices we don't know 'exactly' */
184 switch (ahc->chip & (AHC_EISA|AHC_VL)) {
389 ahc->chip |= AHC_VL;
399 ahc->chip |= AHC_EISA;
408 ahc->chip = AHC_AIC7770;

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