1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_cmd_ch_attach(device_t dev); 56static int ata_cmd_status(device_t dev); 57static int ata_cmd_setmode(device_t dev, int target, int mode); 58static int ata_sii_ch_attach(device_t dev); 59static int ata_sii_ch_detach(device_t dev); 60static int ata_sii_status(device_t dev); 61static void ata_sii_reset(device_t dev); 62static int ata_sii_setmode(device_t dev, int target, int mode); 63static int ata_siiprb_ch_attach(device_t dev); 64static int ata_siiprb_ch_detach(device_t dev); 65static int ata_siiprb_status(device_t dev); 66static int ata_siiprb_begin_transaction(struct ata_request *request); 67static int ata_siiprb_end_transaction(struct ata_request *request); 68static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result); 70static u_int32_t ata_siiprb_softreset(device_t dev, int port); 71static void ata_siiprb_reset(device_t dev); 72static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73static void ata_siiprb_dmainit(device_t dev); 74 75/* misc defines */ 76#define SII_MEMIO 1 77#define SII_PRBIO 2 78#define SII_INTR 0x01 79#define SII_SETCLK 0x02 80#define SII_BUG 0x04 81#define SII_4CH 0x08 82 83/* 84 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 85 */ 86static int 87ata_sii_probe(device_t dev) 88{ 89 struct ata_pci_controller *ctlr = device_get_softc(dev); 90 static const struct ata_chip_id ids[] = 91 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 92 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 93 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 94 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 95 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 96 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 97 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 98 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" }, 99 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 100 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 101 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" }, 102 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 103 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 104 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 105 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 106 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 107 { 0, 0, 0, 0, 0, 0}}; 108 109 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 110 return ENXIO; 111 112 if (!(ctlr->chip = ata_match_chip(dev, ids))) 113 return ENXIO; 114 115 ata_set_desc(dev); 116 ctlr->chipinit = ata_sii_chipinit; 117 return (BUS_PROBE_DEFAULT); 118} 119 120int 121ata_sii_chipinit(device_t dev) 122{ 123 struct ata_pci_controller *ctlr = device_get_softc(dev); 124 125 if (ata_setup_interrupt(dev, ata_generic_intr)) 126 return ENXIO; 127 128 switch (ctlr->chip->cfg1) { 129 case SII_PRBIO: 130 ctlr->r_type1 = SYS_RES_MEMORY; 131 ctlr->r_rid1 = PCIR_BAR(0); 132 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 133 &ctlr->r_rid1, RF_ACTIVE))) 134 return ENXIO; 135 136 ctlr->r_rid2 = PCIR_BAR(2); 137 ctlr->r_type2 = SYS_RES_MEMORY; 138 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 139 &ctlr->r_rid2, RF_ACTIVE))){ 140 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 141 return ENXIO; 142 } 143#ifdef __sparc64__ 144 if (!bus_space_map(rman_get_bustag(ctlr->r_res2), 145 rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2), 146 BUS_SPACE_MAP_LINEAR, NULL)) { 147 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, 148 ctlr->r_res1); 149 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, 150 ctlr->r_res2); 151 return (ENXIO); 152 } 153#endif 154 ctlr->ch_attach = ata_siiprb_ch_attach; 155 ctlr->ch_detach = ata_siiprb_ch_detach; 156 ctlr->reset = ata_siiprb_reset; 157 ctlr->setmode = ata_sata_setmode; 158 ctlr->getrev = ata_sata_getrev; 159 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2; 160 161 /* reset controller */ 162 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 163 DELAY(10000); 164 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 165 break; 166 167 case SII_MEMIO: 168 ctlr->r_type2 = SYS_RES_MEMORY; 169 ctlr->r_rid2 = PCIR_BAR(5); 170 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 171 &ctlr->r_rid2, RF_ACTIVE))){ 172 if (ctlr->chip->chipid != ATA_SII0680 || 173 (pci_read_config(dev, 0x8a, 1) & 1)) 174 return ENXIO; 175 } 176 177 if (ctlr->chip->cfg2 & SII_SETCLK) { 178 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 179 pci_write_config(dev, 0x8a, 180 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 181 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 182 device_printf(dev, "%s could not set ATA133 clock\n", 183 ctlr->chip->text); 184 } 185 186 /* if we have 4 channels enable the second set */ 187 if (ctlr->chip->cfg2 & SII_4CH) { 188 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 189 ctlr->channels = 4; 190 } 191 192 /* dont block interrupts from any channel */ 193 pci_write_config(dev, 0x48, 194 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 195 196 /* enable PCI interrupt as BIOS might not */ 197 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 198 199 if (ctlr->r_res2) { 200 ctlr->ch_attach = ata_sii_ch_attach; 201 ctlr->ch_detach = ata_sii_ch_detach; 202 } 203 204 if (ctlr->chip->max_dma >= ATA_SA150) { 205 ctlr->reset = ata_sii_reset; 206 ctlr->setmode = ata_sata_setmode; 207 ctlr->getrev = ata_sata_getrev; 208 } 209 else 210 ctlr->setmode = ata_sii_setmode; 211 break; 212 213 default: 214 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 215 device_printf(dev, "HW has secondary channel disabled\n"); 216 ctlr->channels = 1; 217 } 218 219 /* enable interrupt as BIOS might not */ 220 pci_write_config(dev, 0x71, 0x01, 1); 221 222 ctlr->ch_attach = ata_cmd_ch_attach; 223 ctlr->ch_detach = ata_pci_ch_detach; 224 ctlr->setmode = ata_cmd_setmode; 225 break; 226 } 227 return 0; 228} 229 230static int 231ata_cmd_ch_attach(device_t dev) 232{ 233 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 234 struct ata_channel *ch = device_get_softc(dev); 235 236 /* setup the usual register normal pci style */ 237 if (ata_pci_ch_attach(dev)) 238 return ENXIO; 239 240 if (ctlr->chip->cfg2 & SII_INTR) 241 ch->hw.status = ata_cmd_status; 242 243#ifdef ATA_CAM 244 ch->flags |= ATA_NO_ATAPI_DMA; 245#endif 246 247 return 0; 248} 249 250static int 251ata_cmd_status(device_t dev) 252{ 253 struct ata_channel *ch = device_get_softc(dev); 254 u_int8_t reg71; 255 256 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 257 (ch->unit ? 0x08 : 0x04))) { 258 pci_write_config(device_get_parent(dev), 0x71, 259 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 260 return ata_pci_status(dev); 261 } 262 return 0; 263} 264 265static int 266ata_cmd_setmode(device_t dev, int target, int mode) 267{ 268 device_t parent = device_get_parent(dev); 269 struct ata_pci_controller *ctlr = device_get_softc(parent); 270 struct ata_channel *ch = device_get_softc(dev); 271 int devno = (ch->unit << 1) + target; 272 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 273 int ureg = ch->unit ? 0x7b : 0x73; 274 int piomode; 275 static const uint8_t piotimings[] = 276 { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f }; 277 static const uint8_t udmatimings[][2] = 278 { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 }, 279 { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } }; 280 281 mode = min(mode, ctlr->chip->max_dma); 282 if (mode >= ATA_UDMA0) { 283 u_int8_t umode = pci_read_config(parent, ureg, 1); 284 285 umode &= ~(target == 0 ? 0x35 : 0xca); 286 umode |= udmatimings[mode & ATA_MODE_MASK][target]; 287 pci_write_config(parent, ureg, umode, 1); 288 piomode = ATA_PIO4; 289 } else { 290 pci_write_config(parent, ureg, 291 pci_read_config(parent, ureg, 1) & 292 ~(target == 0 ? 0x35 : 0xca), 1); 293 piomode = mode; 294 } 295 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1); 296 return (mode); 297} 298 299static int 300ata_sii_ch_attach(device_t dev) 301{ 302 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 303 struct ata_channel *ch = device_get_softc(dev); 304 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 305 int i; 306 307 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 308 ch->r_io[i].res = ctlr->r_res2; 309 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 310 } 311 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 312 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 313 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 314 ata_default_registers(dev); 315 316 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 317 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 318 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 319 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 320 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 321 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 322 323 if (ctlr->chip->max_dma >= ATA_SA150) { 324 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 325 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 326 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 327 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 328 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 329 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 330 ch->flags |= ATA_NO_SLAVE; 331 ch->flags |= ATA_SATA; 332 ch->flags |= ATA_KNOWN_PRESENCE; 333 334 /* enable PHY state change interrupt */ 335 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 336 } 337 338 if (ctlr->chip->cfg2 & SII_BUG) { 339 /* work around errata in early chips */ 340 ch->dma.boundary = 8192; 341 ch->dma.segsize = 15 * DEV_BSIZE; 342 } 343 344 ata_pci_hw(dev); 345 ch->hw.status = ata_sii_status; 346 if (ctlr->chip->cfg2 & SII_SETCLK) 347 ch->flags |= ATA_CHECKS_CABLE; 348 349 ata_pci_dmainit(dev); 350 351 return 0; 352} 353 354static int 355ata_sii_ch_detach(device_t dev) 356{ 357 358 ata_pci_dmafini(dev); 359 return (0); 360} 361 362static int 363ata_sii_status(device_t dev) 364{ 365 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 366 struct ata_channel *ch = device_get_softc(dev); 367 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 368 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 369 370 /* do we have any PHY events ? */ 371 if (ctlr->chip->max_dma >= ATA_SA150 && 372 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 373 ata_sata_phy_check_events(dev, -1); 374 375 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 376 return ata_pci_status(dev); 377 else 378 return 0; 379} 380 381static void 382ata_sii_reset(device_t dev) 383{ 384 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 385 struct ata_channel *ch = device_get_softc(dev); 386 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8); 387 uint32_t val; 388 389 /* Apply R_ERR on DMA activate FIS errata workaround. */ 390 val = ATA_INL(ctlr->r_res2, 0x14c + offset); 391 if ((val & 0x3) == 0x1) 392 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3); 393 394 if (ata_sata_phy_reset(dev, -1, 1)) 395 ata_generic_reset(dev); 396 else 397 ch->devices = 0; 398} 399 400static int 401ata_sii_setmode(device_t dev, int target, int mode) 402{ 403 device_t parent = device_get_parent(dev); 404 struct ata_pci_controller *ctlr = device_get_softc(parent); 405 struct ata_channel *ch = device_get_softc(dev); 406 int rego = (ch->unit << 4) + (target << 1); 407 int mreg = ch->unit ? 0x84 : 0x80; 408 int mask = 0x03 << (target << 2); 409 int mval = pci_read_config(parent, mreg, 1) & ~mask; 410 int piomode; 411 u_int8_t preg = 0xa4 + rego; 412 u_int8_t dreg = 0xa8 + rego; 413 u_int8_t ureg = 0xac + rego; 414 static const uint16_t piotimings[] = 415 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 416 static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 417 static const uint8_t udmatimings[] = 418 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 419 420 mode = min(mode, ctlr->chip->max_dma); 421 422 if (ctlr->chip->cfg2 & SII_SETCLK) { 423 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 424 (pci_read_config(parent, 0x79, 1) & 425 (ch->unit ? 0x02 : 0x01))) { 426 ata_print_cable(dev, "controller"); 427 mode = ATA_UDMA2; 428 } 429 } 430 if (mode >= ATA_UDMA0) { 431 pci_write_config(parent, mreg, 432 mval | (0x03 << (target << 2)), 1); 433 pci_write_config(parent, ureg, 434 (pci_read_config(parent, ureg, 1) & ~0x3f) | 435 udmatimings[mode & ATA_MODE_MASK], 1); 436 piomode = ATA_PIO4; 437 } else if (mode >= ATA_WDMA0) { 438 pci_write_config(parent, mreg, 439 mval | (0x02 << (target << 2)), 1); 440 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 441 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 442 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 443 } else { 444 pci_write_config(parent, mreg, 445 mval | (0x01 << (target << 2)), 1); 446 piomode = mode; 447 } 448 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2); 449 return (mode); 450} 451 452struct ata_siiprb_dma_prdentry { 453 u_int64_t addr; 454 u_int32_t count; 455 u_int32_t control; 456} __packed; 457 458#define ATA_SIIPRB_DMA_ENTRIES 129 459struct ata_siiprb_ata_command { 460 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 461} __packed; 462 463struct ata_siiprb_atapi_command { 464 u_int8_t ccb[16]; 465 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES]; 466} __packed; 467 468struct ata_siiprb_command { 469 u_int16_t control; 470 u_int16_t protocol_override; 471 u_int32_t transfer_count; 472 u_int8_t fis[24]; 473 union { 474 struct ata_siiprb_ata_command ata; 475 struct ata_siiprb_atapi_command atapi; 476 } u; 477} __packed; 478 479static int 480ata_siiprb_ch_attach(device_t dev) 481{ 482 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 483 struct ata_channel *ch = device_get_softc(dev); 484 int offset = ch->unit * 0x2000; 485 486 ata_siiprb_dmainit(dev); 487 488 /* set the SATA resources */ 489 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 490 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 491 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 492 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 493 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 494 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 495 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 496 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 497 498 ch->hw.status = ata_siiprb_status; 499 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 500 ch->hw.end_transaction = ata_siiprb_end_transaction; 501 ch->hw.command = NULL; /* not used here */ 502 ch->hw.softreset = ata_siiprb_softreset; 503 ch->hw.pm_read = ata_siiprb_pm_read; 504 ch->hw.pm_write = ata_siiprb_pm_write; 505 ch->flags |= ATA_NO_SLAVE; 506 ch->flags |= ATA_SATA; 507 return 0; 508} 509 510static int 511ata_siiprb_ch_detach(device_t dev) 512{ 513 struct ata_channel *ch = device_get_softc(dev); 514 515 if (ch->dma.work_tag && ch->dma.work_map) 516 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 517 BUS_DMASYNC_POSTWRITE); 518 ata_dmafini(dev); 519 return 0; 520} 521 522static int 523ata_siiprb_status(device_t dev) 524{ 525 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 526 struct ata_channel *ch = device_get_softc(dev); 527 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044); 528 int offset = ch->unit * 0x2000; 529 530 if (action & (1 << ch->unit)) { 531 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 532 533 /* do we have any PHY events ? */ 534 ata_sata_phy_check_events(dev, -1); 535 536 /* clear interrupt(s) */ 537 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 538 539 /* do we have any device action ? */ 540 return (istatus & 0x00000003); 541 } 542 return 0; 543} 544 545static int 546ata_siiprb_begin_transaction(struct ata_request *request) 547{ 548 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 549 struct ata_channel *ch = device_get_softc(request->parent); 550 struct ata_siiprb_command *prb; 551 struct ata_siiprb_dma_prdentry *prd; 552 int offset = ch->unit * 0x2000; 553 u_int64_t prb_bus; 554 555 /* SOS XXX */ 556 if (request->u.ata.command == ATA_DEVICE_RESET) { 557 request->result = 0; 558 return ATA_OP_FINISHED; 559 } 560 561 /* get a piece of the workspace for this request */ 562 prb = (struct ata_siiprb_command *)ch->dma.work; 563 564 /* clear the prb structure */ 565 bzero(prb, sizeof(struct ata_siiprb_command)); 566 567 /* setup the FIS for this request */ 568 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 569 device_printf(request->parent, "setting up SATA FIS failed\n"); 570 request->result = EIO; 571 return ATA_OP_FINISHED; 572 } 573 574 /* setup transfer type */ 575 if (request->flags & ATA_R_ATAPI) { 576 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16); 577 if (request->flags & ATA_R_ATAPI16) 578 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020); 579 else 580 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020); 581 if (request->flags & ATA_R_READ) 582 prb->control = htole16(0x0010); 583 if (request->flags & ATA_R_WRITE) 584 prb->control = htole16(0x0020); 585 prd = &prb->u.atapi.prd[0]; 586 } 587 else 588 prd = &prb->u.ata.prd[0]; 589 590 /* if request moves data setup and load SG list */ 591 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 592 if (ch->dma.load(request, prd, NULL)) { 593 device_printf(request->parent, "setting up DMA failed\n"); 594 request->result = EIO; 595 return ATA_OP_FINISHED; 596 } 597 } 598 599 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE); 600 601 /* activate the prb */ 602 prb_bus = ch->dma.work_bus; 603 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 604 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32); 605 606 /* start the timeout */ 607 callout_reset(&request->callout, request->timeout * hz, 608 (timeout_t*)ata_timeout, request); 609 return ATA_OP_CONTINUES; 610} 611 612static int 613ata_siiprb_end_transaction(struct ata_request *request) 614{ 615 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 616 struct ata_channel *ch = device_get_softc(request->parent); 617 struct ata_siiprb_command *prb; 618 int offset = ch->unit * 0x2000; 619 int error, timeout; 620 621 /* kill the timeout */ 622 callout_stop(&request->callout); 623 624 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE); 625 626 prb = (struct ata_siiprb_command *) 627 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 628 629 /* any controller errors flagged ? */ 630 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 631 if (bootverbose) 632 printf("ata_siiprb_end_transaction %s error=%08x\n", 633 ata_cmd2str(request), error); 634 635 /* if device error status get details */ 636 if (error == 1 || error == 2) { 637 request->status = prb->fis[2]; 638 if (request->status & ATA_S_ERROR) 639 request->error = prb->fis[3]; 640 } 641 642 /* SOS XXX handle other controller errors here */ 643 644 /* initialize port */ 645 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); 646 647 /* poll for port ready */ 648 for (timeout = 0; timeout < 1000; timeout++) { 649 DELAY(1000); 650 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) 651 break; 652 } 653 if (bootverbose) { 654 if (timeout >= 1000) 655 device_printf(ch->dev, "port initialize timeout\n"); 656 else 657 device_printf(ch->dev, "port initialize time=%dms\n", timeout); 658 } 659 } 660 661 /* Read back registers to the request struct. */ 662 if ((request->flags & ATA_R_ATAPI) == 0 && 663 ((request->status & ATA_S_ERROR) || 664 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT)))) { 665 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); 666 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | 667 ((u_int64_t)prb->fis[6] << 16); 668 if (request->flags & ATA_R_48BIT) 669 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | 670 ((u_int64_t)prb->fis[9] << 32) | 671 ((u_int64_t)prb->fis[10] << 40); 672 else 673 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); 674 } 675 676 /* update progress */ 677 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 678 if (request->flags & ATA_R_READ) 679 request->donecount = le32toh(prb->transfer_count); 680 else 681 request->donecount = request->bytecount; 682 } 683 684 /* release SG list etc */ 685 ch->dma.unload(request); 686 687 return ATA_OP_FINISHED; 688} 689 690static int 691ata_siiprb_issue_cmd(device_t dev) 692{ 693 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 694 struct ata_channel *ch = device_get_softc(dev); 695 u_int64_t prb_bus = ch->dma.work_bus; 696 u_int32_t status; 697 int offset = ch->unit * 0x2000; 698 int timeout; 699 700 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE); 701 702 /* issue command to chip */ 703 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus); 704 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32); 705 706 /* poll for command finished */ 707 for (timeout = 0; timeout < 10000; timeout++) { 708 DELAY(1000); 709 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 710 break; 711 } 712 713 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE); 714 715 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000); 716 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff); 717 718 if (timeout >= 1000) 719 return EIO; 720 721 if (bootverbose) 722 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n", 723 timeout, status); 724 return 0; 725} 726 727static int 728ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result) 729{ 730 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 731 struct ata_channel *ch = device_get_softc(dev); 732 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 733 int offset = ch->unit * 0x2000; 734 735 if (port < 0) { 736 *result = ATA_IDX_INL(ch, reg); 737 return (0); 738 } 739 if (port < ATA_PM) { 740 switch (reg) { 741 case ATA_SSTATUS: 742 reg = 0; 743 break; 744 case ATA_SERROR: 745 reg = 1; 746 break; 747 case ATA_SCONTROL: 748 reg = 2; 749 break; 750 default: 751 return (EINVAL); 752 } 753 } 754 bzero(prb, sizeof(struct ata_siiprb_command)); 755 prb->fis[0] = 0x27; /* host to device */ 756 prb->fis[1] = 0x8f; /* command FIS to PM port */ 757 prb->fis[2] = ATA_READ_PM; 758 prb->fis[3] = reg; 759 prb->fis[7] = port; 760 if (ata_siiprb_issue_cmd(dev)) { 761 device_printf(dev, "error reading PM port\n"); 762 return EIO; 763 } 764 prb = (struct ata_siiprb_command *) 765 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 766 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 767 return 0; 768} 769 770static int 771ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value) 772{ 773 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 774 struct ata_channel *ch = device_get_softc(dev); 775 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 776 int offset = ch->unit * 0x2000; 777 778 if (port < 0) { 779 ATA_IDX_OUTL(ch, reg, value); 780 return (0); 781 } 782 if (port < ATA_PM) { 783 switch (reg) { 784 case ATA_SSTATUS: 785 reg = 0; 786 break; 787 case ATA_SERROR: 788 reg = 1; 789 break; 790 case ATA_SCONTROL: 791 reg = 2; 792 break; 793 default: 794 return (EINVAL); 795 } 796 } 797 bzero(prb, sizeof(struct ata_siiprb_command)); 798 prb->fis[0] = 0x27; /* host to device */ 799 prb->fis[1] = 0x8f; /* command FIS to PM port */ 800 prb->fis[2] = ATA_WRITE_PM; 801 prb->fis[3] = reg; 802 prb->fis[7] = port; 803 prb->fis[12] = value & 0xff; 804 prb->fis[4] = (value >> 8) & 0xff; 805 prb->fis[5] = (value >> 16) & 0xff; 806 prb->fis[6] = (value >> 24) & 0xff; 807 if (ata_siiprb_issue_cmd(dev)) { 808 device_printf(dev, "error writing PM port\n"); 809 return ATA_E_ABORT; 810 } 811 prb = (struct ata_siiprb_command *) 812 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 813 return prb->fis[3]; 814} 815 816static u_int32_t 817ata_siiprb_softreset(device_t dev, int port) 818{ 819 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 820 struct ata_channel *ch = device_get_softc(dev); 821 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work; 822 u_int32_t signature; 823 int offset = ch->unit * 0x2000; 824 825 /* setup the workspace for a soft reset command */ 826 bzero(prb, sizeof(struct ata_siiprb_command)); 827 prb->control = htole16(0x0080); 828 prb->fis[1] = port & 0x0f; 829 830 /* issue soft reset */ 831 if (ata_siiprb_issue_cmd(dev)) 832 return -1; 833 834 ata_udelay(150000); 835 836 /* get possible signature */ 837 prb = (struct ata_siiprb_command *) 838 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); 839 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 840 841 /* clear error bits/interrupt */ 842 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); 843 844 return signature; 845} 846 847static void 848ata_siiprb_reset(device_t dev) 849{ 850 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 851 struct ata_channel *ch = device_get_softc(dev); 852 int offset = ch->unit * 0x2000; 853 u_int32_t status, signature; 854 int timeout; 855 856 /* disable interrupts */ 857 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff); 858 859 /* reset channel HW */ 860 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 861 DELAY(1000); 862 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 863 DELAY(10000); 864 865 /* poll for channel ready */ 866 for (timeout = 0; timeout < 1000; timeout++) { 867 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000) 868 break; 869 DELAY(1000); 870 } 871 872 if (bootverbose) { 873 if (timeout >= 1000) 874 device_printf(dev, "channel HW reset timeout\n"); 875 else 876 device_printf(dev, "channel HW reset time=%dms\n", timeout); 877 } 878 879 /* reset phy */ 880 if (!ata_sata_phy_reset(dev, -1, 1)) { 881 if (bootverbose) 882 device_printf(dev, "phy reset found no device\n"); 883 ch->devices = 0; 884 goto finish; 885 } 886 887 /* issue soft reset */ 888 signature = ata_siiprb_softreset(dev, ATA_PM); 889 if (bootverbose) 890 device_printf(dev, "SIGNATURE=%08x\n", signature); 891 892 /* figure out whats there */ 893 switch (signature >> 16) { 894 case 0x0000: 895 ch->devices = ATA_ATA_MASTER; 896 break; 897 case 0x9669: 898 ch->devices = ATA_PORTMULTIPLIER; 899 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */ 900 //SOS XXX need to clear all PM status and interrupts!!!! 901 ata_pm_identify(dev); 902 break; 903 case 0xeb14: 904 ch->devices = ATA_ATAPI_MASTER; 905 break; 906 default: 907 ch->devices = 0; 908 } 909 if (bootverbose) 910 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices); 911 912finish: 913 /* clear interrupt(s) */ 914 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 915 916 /* require explicit interrupt ack */ 917 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 918 919 /* 64bit mode */ 920 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 921 922 /* enable interrupts wanted */ 923 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 924} 925 926static void 927ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 928{ 929 struct ata_dmasetprd_args *args = xsc; 930 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 931 int i; 932 933 if ((args->error = error)) 934 return; 935 936 for (i = 0; i < nsegs; i++) { 937 prd[i].addr = htole64(segs[i].ds_addr); 938 prd[i].count = htole32(segs[i].ds_len); 939 } 940 prd[i - 1].control = htole32(ATA_DMA_EOT); 941 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n")); 942 args->nsegs = nsegs; 943} 944 945static void 946ata_siiprb_dmainit(device_t dev) 947{ 948 struct ata_channel *ch = device_get_softc(dev); 949 950 /* note start and stop are not used here */ 951 ch->dma.setprd = ata_siiprb_dmasetprd; 952 ch->dma.max_address = BUS_SPACE_MAXADDR; 953 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE; 954 ata_dmainit(dev); 955} 956 957ATA_DECLARE_DRIVER(ata_sii); 958