1263970Sdes/*- 2224638Sbrooks * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 392559Sdes * All rights reserved. 465668Skris * 565668Skris * Redistribution and use in source and binary forms, with or without 665668Skris * modification, are permitted provided that the following conditions 765668Skris * are met: 865668Skris * 1. Redistributions of source code must retain the above copyright 965668Skris * notice, this list of conditions and the following disclaimer, 1065668Skris * without modification, immediately at the beginning of the file. 1165668Skris * 2. Redistributions in binary form must reproduce the above copyright 1265668Skris * notice, this list of conditions and the following disclaimer in the 1365668Skris * documentation and/or other materials provided with the distribution. 1465668Skris * 1565668Skris * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1692559Sdes * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1765668Skris * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1865668Skris * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1965668Skris * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2065668Skris * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2165668Skris * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2265668Skris * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2365668Skris * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2465668Skris * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2565668Skris */ 2665668Skris 2765668Skris#include <sys/cdefs.h> 2865668Skris__FBSDID("$FreeBSD$"); 2965668Skris 3065668Skris#include "opt_ata.h" 3165668Skris#include <sys/param.h> 3265668Skris#include <sys/module.h> 3365668Skris#include <sys/systm.h> 3465668Skris#include <sys/kernel.h> 3565668Skris#include <sys/ata.h> 3665668Skris#include <sys/bus.h> 3765668Skris#include <sys/endian.h> 3857429Smarkm#include <sys/malloc.h> 3992559Sdes#include <sys/lock.h> 4092559Sdes#include <sys/mutex.h> 4157429Smarkm#include <sys/sema.h> 4257429Smarkm#include <sys/taskqueue.h> 4357429Smarkm#include <vm/uma.h> 4457429Smarkm#include <machine/stdarg.h> 4557429Smarkm#include <machine/resource.h> 4657429Smarkm#include <machine/bus.h> 4757429Smarkm#include <sys/rman.h> 4860573Skris#include <dev/pci/pcivar.h> 4960573Skris#include <dev/pci/pcireg.h> 5060573Skris#include <dev/ata/ata-all.h> 5160573Skris#include <dev/ata/ata-pci.h> 5260573Skris#include <ata_if.h> 5376262Sgreen 5476262Sgreen/* local prototypes */ 5576262Sgreenstatic int ata_serverworks_chipinit(device_t dev); 5692559Sdesstatic int ata_serverworks_ch_attach(device_t dev); 57204917Sdesstatic int ata_serverworks_ch_detach(device_t dev); 58204917Sdesstatic void ata_serverworks_tf_read(struct ata_request *request); 59263970Sdesstatic void ata_serverworks_tf_write(struct ata_request *request); 60263970Sdesstatic int ata_serverworks_setmode(device_t dev, int target, int mode); 6157429Smarkmstatic void ata_serverworks_sata_reset(device_t dev); 62247485Sdesstatic int ata_serverworks_status(device_t dev); 63247485Sdes 6465668Skris/* misc defines */ 6565668Skris#define SWKS_33 0 6665668Skris#define SWKS_66 1 67215116Sdes#define SWKS_100 2 6892559Sdes#define SWKS_MIO 3 69157019Sdes 70181111Sdes 71157019Sdes/* 7257429Smarkm * ServerWorks chipset support functions 73181111Sdes */ 74181111Sdesstatic int 75181111Sdesata_serverworks_probe(device_t dev) 76181111Sdes{ 77181111Sdes struct ata_pci_controller *ctlr = device_get_softc(dev); 78181111Sdes static const struct ata_chip_id ids[] = 79181111Sdes {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_WDMA2, "ROSB4" }, 80181111Sdes { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" }, 81181111Sdes { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" }, 82181111Sdes { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" }, 83181111Sdes { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" }, 84181111Sdes { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" }, 85181111Sdes { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 86181111Sdes { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 87181111Sdes { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" }, 88181111Sdes { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" }, 89181111Sdes { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" }, 90181111Sdes { 0, 0, 0, 0, 0, 0}}; 91204917Sdes 92204917Sdes if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID) 93204917Sdes return ENXIO; 9465668Skris 9557429Smarkm if (!(ctlr->chip = ata_match_chip(dev, ids))) 9657429Smarkm return ENXIO; 9757429Smarkm 9892559Sdes ata_set_desc(dev); 9992559Sdes ctlr->chipinit = ata_serverworks_chipinit; 10060573Skris return (BUS_PROBE_DEFAULT); 10160573Skris} 10260573Skris 10360573Skrisstatic int 10460573Skrisata_serverworks_status(device_t dev) 105204917Sdes{ 10674500Sgreen struct ata_channel *ch = device_get_softc(dev); 107263970Sdes struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 108106130Sdes 109263970Sdes /* 110147005Sdes * Check if this interrupt belongs to our channel. 11192559Sdes */ 112247485Sdes if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit))) 113204917Sdes return (0); 114204917Sdes 115204917Sdes /* 116204917Sdes * We need to do a 4-byte read on the status reg before the values 117263970Sdes * will report correctly 11857429Smarkm */ 11957429Smarkm 12057429Smarkm ATA_IDX_INL(ch,ATA_STATUS); 12157429Smarkm 12260573Skris return ata_pci_status(dev); 123192595Sdes} 12492559Sdes 12557429Smarkmstatic int 126247485Sdesata_serverworks_chipinit(device_t dev) 12757429Smarkm{ 12857429Smarkm struct ata_pci_controller *ctlr = device_get_softc(dev); 12960573Skris 13099063Sdes if (ata_setup_interrupt(dev, ata_generic_intr)) 13199063Sdes return ENXIO; 13299063Sdes 13399063Sdes if (ctlr->chip->cfg1 == SWKS_MIO) { 13499063Sdes ctlr->r_type2 = SYS_RES_MEMORY; 13599063Sdes ctlr->r_rid2 = PCIR_BAR(5); 136247485Sdes if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 137224638Sbrooks &ctlr->r_rid2, RF_ACTIVE))) 13860573Skris return ENXIO; 13992559Sdes 14060573Skris ctlr->channels = ctlr->chip->cfg2; 14160573Skris ctlr->ch_attach = ata_serverworks_ch_attach; 14260573Skris ctlr->ch_detach = ata_serverworks_ch_detach; 14360573Skris ctlr->setmode = ata_sata_setmode; 144215116Sdes ctlr->getrev = ata_sata_getrev; 145181111Sdes ctlr->reset = ata_serverworks_sata_reset; 14692559Sdes return 0; 147157019Sdes } 148181111Sdes else if (ctlr->chip->cfg1 == SWKS_33) { 14960573Skris device_t *children; 15065668Skris int nchildren, i; 151157019Sdes 152157019Sdes /* locate the ISA part in the southbridge and enable UDMA33 */ 153181111Sdes if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 154181111Sdes for (i = 0; i < nchildren; i++) { 155157019Sdes if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 156181111Sdes pci_write_config(children[i], 0x64, 157181111Sdes (pci_read_config(children[i], 0x64, 4) & 158181111Sdes ~0x00002000) | 0x00004000, 4); 159181111Sdes break; 160181111Sdes } 161204917Sdes } 162204917Sdes free(children, M_TEMP); 163204917Sdes } 164204917Sdes } 165215116Sdes else { 16665668Skris pci_write_config(dev, 0x5a, 16765668Skris (pci_read_config(dev, 0x5a, 1) & ~0x40) | 16860573Skris (ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02, 1); 16960573Skris } 17060573Skris ctlr->setmode = ata_serverworks_setmode; 17160573Skris return 0; 17265668Skris} 17392559Sdes 174181111Sdesstatic int 17592559Sdesata_serverworks_ch_attach(device_t dev) 176181111Sdes{ 17792559Sdes struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 17892559Sdes struct ata_channel *ch = device_get_softc(dev); 179224638Sbrooks int ch_offset; 180224638Sbrooks int i; 18192559Sdes 18292559Sdes ch_offset = ch->unit * 0x100; 18392559Sdes 18492559Sdes for (i = ATA_DATA; i < ATA_MAX_RES; i++) 18592559Sdes ch->r_io[i].res = ctlr->r_res2; 18665668Skris 18792559Sdes /* setup ATA registers */ 18892559Sdes ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 18992559Sdes ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 19092559Sdes ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 19192559Sdes ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 19260573Skris ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 19392559Sdes ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 19492559Sdes ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 19598684Sdes ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 19698684Sdes ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 197204917Sdes ata_default_registers(dev); 19860573Skris 199157019Sdes /* setup DMA registers */ 200157019Sdes ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 20198684Sdes ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 20298684Sdes ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 20398684Sdes 20498684Sdes /* setup SATA registers */ 20598684Sdes ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 20698684Sdes ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 20798684Sdes ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 208149753Sdes 20998684Sdes ch->flags |= ATA_NO_SLAVE | ATA_SATA | ATA_KNOWN_PRESENCE; 21098684Sdes ata_pci_hw(dev); 21192559Sdes ch->hw.tf_read = ata_serverworks_tf_read; 21260573Skris ch->hw.tf_write = ata_serverworks_tf_write; 213157019Sdes 21492559Sdes if (ctlr->chip->chipid == ATA_K2) { 21599063Sdes /* 216181111Sdes * Set SICR registers to turn off waiting for a status message 21792559Sdes * before sending FIS. Values obtained from the Darwin driver. 21892559Sdes */ 21992559Sdes 22069587Sgreen ATA_OUTL(ctlr->r_res2, ch_offset + 0x80, 22192559Sdes ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000); 22292559Sdes ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0); 223157019Sdes 224215116Sdes /* 225181111Sdes * Some controllers have a bug where they will send the command 226181111Sdes * to the drive before seeing a DMA start, and then can begin 227181111Sdes * receiving data before the DMA start arrives. The controller 228181111Sdes * will then become confused and either corrupt the data or crash. 22992559Sdes * Remedy this by starting DMA before sending the drive command. 23092559Sdes */ 231137019Sdes 23260573Skris ch->flags |= ATA_DMA_BEFORE_CMD; 23392559Sdes 23460573Skris /* 23592559Sdes * The status register must be read as a long to fill the other 23692559Sdes * registers. 23792559Sdes */ 23892559Sdes 23992559Sdes ch->hw.status = ata_serverworks_status; 24092559Sdes ch->flags |= ATA_STATUS_IS_LONG; 24192559Sdes } 24292559Sdes 24392559Sdes /* chip does not reliably do 64K DMA transfers */ 24492559Sdes ch->dma.max_iosize = 64 * DEV_BSIZE; 245181111Sdes 24660573Skris ata_pci_dmainit(dev); 24792559Sdes 24860573Skris return 0; 249247485Sdes} 250247485Sdes 25192559Sdesstatic int 25292559Sdesata_serverworks_ch_detach(device_t dev) 25360573Skris{ 25492559Sdes 25592559Sdes ata_pci_dmafini(dev); 25692559Sdes return (0); 25792559Sdes} 25892559Sdes 25960573Skrisstatic void 26092559Sdesata_serverworks_tf_read(struct ata_request *request) 26192559Sdes{ 26292559Sdes struct ata_channel *ch = device_get_softc(request->parent); 26392559Sdes 264162856Sdes if (request->flags & ATA_R_48BIT) { 265247485Sdes u_int16_t temp; 266247485Sdes 26792559Sdes request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT); 268162856Sdes temp = ATA_IDX_INW(ch, ATA_SECTOR); 269181111Sdes request->u.ata.lba = (u_int64_t)(temp & 0x00ff) | 270162856Sdes ((u_int64_t)(temp & 0xff00) << 24); 271181111Sdes temp = ATA_IDX_INW(ch, ATA_CYL_LSB); 272204917Sdes request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) | 273181111Sdes ((u_int64_t)(temp & 0xff00) << 32); 274162856Sdes temp = ATA_IDX_INW(ch, ATA_CYL_MSB); 275147005Sdes request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) | 276147005Sdes ((u_int64_t)(temp & 0xff00) << 40); 277147005Sdes } 278247485Sdes else { 279192595Sdes request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff; 280137019Sdes request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) | 281247485Sdes ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) | 282247485Sdes ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) | 28360573Skris ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24); 28492559Sdes } 28560573Skris} 28692559Sdes 287149753Sdesstatic void 28892559Sdesata_serverworks_tf_write(struct ata_request *request) 289149753Sdes{ 290247485Sdes struct ata_channel *ch = device_get_softc(request->parent); 29192559Sdes#ifndef ATA_CAM 29260573Skris struct ata_device *atadev = device_get_softc(request->dev); 29392559Sdes#endif 29460573Skris 29592559Sdes if (request->flags & ATA_R_48BIT) { 29660573Skris ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 29792559Sdes ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 29860573Skris ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 29992559Sdes (request->u.ata.lba & 0x00ff)); 30092559Sdes ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 30160573Skris ((request->u.ata.lba >> 8) & 0x00ff)); 30292559Sdes ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 30360573Skris ((request->u.ata.lba >> 16) & 0x00ff)); 30492559Sdes ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 305181111Sdes } 30692559Sdes else { 30792559Sdes ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 30876262Sgreen ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 30992559Sdes#ifndef ATA_CAM 31092559Sdes if (atadev->flags & ATA_D_USE_CHS) { 31192559Sdes int heads, sectors; 31276262Sgreen 313224638Sbrooks if (atadev->param.atavalid & ATA_FLAG_54_58) { 314224638Sbrooks heads = atadev->param.current_heads; 315247485Sdes sectors = atadev->param.current_sectors; 316247485Sdes } 31757429Smarkm else { 318 heads = atadev->param.heads; 319 sectors = atadev->param.sectors; 320 } 321 ATA_IDX_OUTW(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1); 322 ATA_IDX_OUTW(ch, ATA_CYL_LSB, 323 (request->u.ata.lba / (sectors * heads))); 324 ATA_IDX_OUTW(ch, ATA_CYL_MSB, 325 (request->u.ata.lba / (sectors * heads)) >> 8); 326 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) | 327 (((request->u.ata.lba% (sectors * heads)) / 328 sectors) & 0xf)); 329 } 330 else { 331#endif 332 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba); 333 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 334 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 335 ATA_IDX_OUTW(ch, ATA_DRIVE, 336 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 337 ((request->u.ata.lba >> 24) & 0x0f)); 338#ifndef ATA_CAM 339 } 340#endif 341 } 342} 343 344static int 345ata_serverworks_setmode(device_t dev, int target, int mode) 346{ 347 device_t parent = device_get_parent(dev); 348 struct ata_pci_controller *ctlr = device_get_softc(parent); 349 struct ata_channel *ch = device_get_softc(dev); 350 int devno = (ch->unit << 1) + target; 351 int offset = (devno ^ 0x01) << 3; 352 int piomode; 353 static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 354 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 355 356 mode = min(mode, ctlr->chip->max_dma); 357 if (mode >= ATA_UDMA0) { 358 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */ 359 pci_write_config(parent, 0x56, 360 (pci_read_config(parent, 0x56, 2) & 361 ~(0xf << (devno << 2))) | 362 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 363 pci_write_config(parent, 0x54, 364 pci_read_config(parent, 0x54, 1) | 365 (0x01 << devno), 1); 366 pci_write_config(parent, 0x44, 367 (pci_read_config(parent, 0x44, 4) & 368 ~(0xff << offset)) | 369 (dmatimings[2] << offset), 4); 370 piomode = ATA_PIO4; 371 } else if (mode >= ATA_WDMA0) { 372 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */ 373 pci_write_config(parent, 0x54, 374 pci_read_config(parent, 0x54, 1) & 375 ~(0x01 << devno), 1); 376 pci_write_config(parent, 0x44, 377 (pci_read_config(parent, 0x44, 4) & 378 ~(0xff << offset)) | 379 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 380 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 381 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 382 } else { 383 /* Disable UDMA, set requested PIO. */ 384 pci_write_config(parent, 0x54, 385 pci_read_config(parent, 0x54, 1) & 386 ~(0x01 << devno), 1); 387 piomode = mode; 388 } 389 /* Set PIO mode and timings, calculated above. */ 390 if (ctlr->chip->cfg1 != SWKS_33) { 391 pci_write_config(parent, 0x4a, 392 (pci_read_config(parent, 0x4a, 2) & 393 ~(0xf << (devno << 2))) | 394 ((piomode - ATA_PIO0) << (devno<<2)),2); 395 } 396 pci_write_config(parent, 0x40, 397 (pci_read_config(parent, 0x40, 4) & 398 ~(0xff << offset)) | 399 (piotimings[ata_mode2idx(piomode)] << offset), 4); 400 return (mode); 401} 402 403static void 404ata_serverworks_sata_reset(device_t dev) 405{ 406 struct ata_channel *ch = device_get_softc(dev); 407 408 if (ata_sata_phy_reset(dev, -1, 0)) 409 ata_generic_reset(dev); 410 else 411 ch->devices = 0; 412} 413 414ATA_DECLARE_DRIVER(ata_serverworks); 415