1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_via_chipinit(device_t dev); 56static int ata_via_ch_attach(device_t dev); 57static int ata_via_ch_detach(device_t dev); 58static void ata_via_reset(device_t dev); 59static int ata_via_status(device_t dev); 60static int ata_via_old_setmode(device_t dev, int target, int mode); 61static void ata_via_southbridge_fixup(device_t dev); 62static int ata_via_new_setmode(device_t dev, int target, int mode); 63static int ata_via_sata_ch_attach(device_t dev); 64static int ata_via_sata_getrev(device_t dev, int target); 65static int ata_via_sata_setmode(device_t dev, int target, int mode); 66static void ata_via_sata_reset(device_t dev); 67static int ata_via_sata_scr_read(device_t dev, int port, int reg, 68 u_int32_t *result); 69static int ata_via_sata_scr_write(device_t dev, int port, int reg, 70 u_int32_t value); 71static int ata_via_sata_status(device_t dev); 72 73/* misc defines */ 74#define VIA33 0 75#define VIA66 1 76#define VIA100 2 77#define VIA133 3 78 79#define VIACLK 0x01 80#define VIABUG 0x02 81#define VIABAR 0x04 82#define VIAAHCI 0x08 83#define VIASATA 0x10 84 85/* 86 * VIA Technologies Inc. chipset support functions 87 */ 88static int 89ata_via_probe(device_t dev) 90{ 91 struct ata_pci_controller *ctlr = device_get_softc(dev); 92 static const struct ata_chip_id ids[] = 93 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 94 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 95 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 96 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 97 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 98 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 99 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 100 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 101 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 102 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 103 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 104 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 105 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 106 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 107 { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" }, 108 { ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 109 { ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 110 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 111 { ATA_VIACX700, 0x00, VIA133, VIASATA, ATA_SA150, "CX700" }, 112 { ATA_VIAVX800, 0x00, VIA133, VIASATA, ATA_SA150, "VX800" }, 113 { ATA_VIAVX855, 0x00, VIA133, 0x00, ATA_UDMA6, "VX855" }, 114 { ATA_VIAVX900, 0x00, VIA133, VIASATA, ATA_SA300, "VX900" }, 115 { 0, 0, 0, 0, 0, 0 }}; 116 static const struct ata_chip_id new_ids[] = 117 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 118 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 119 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 120 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 121 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" }, 122 { ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 123 { ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" }, 124 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 125 { 0, 0, 0, 0, 0, 0 }}; 126 127 if (pci_get_vendor(dev) != ATA_VIA_ID) 128 return ENXIO; 129 130 if (pci_get_devid(dev) == ATA_VIA82C571 || 131 pci_get_devid(dev) == ATA_VIACX700IDE || 132 pci_get_devid(dev) == ATA_VIASATAIDE || 133 pci_get_devid(dev) == ATA_VIASATAIDE2 || 134 pci_get_devid(dev) == ATA_VIASATAIDE3) { 135 if (!(ctlr->chip = ata_find_chip(dev, ids, -99))) 136 return ENXIO; 137 } 138 else { 139 if (!(ctlr->chip = ata_match_chip(dev, new_ids))) 140 return ENXIO; 141 } 142 143 ata_set_desc(dev); 144 ctlr->chipinit = ata_via_chipinit; 145 return (BUS_PROBE_DEFAULT); 146} 147 148static int 149ata_via_chipinit(device_t dev) 150{ 151 struct ata_pci_controller *ctlr = device_get_softc(dev); 152 153 if (ata_setup_interrupt(dev, ata_generic_intr)) 154 return ENXIO; 155 156 /* AHCI SATA */ 157 if (ctlr->chip->cfg2 & VIAAHCI) { 158 if (ata_ahci_chipinit(dev) != ENXIO) 159 return (0); 160 } 161 /* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */ 162 if (ctlr->chip->cfg2 & VIASATA) { 163 ctlr->ch_attach = ata_via_sata_ch_attach; 164 ctlr->setmode = ata_via_sata_setmode; 165 ctlr->getrev = ata_via_sata_getrev; 166 ctlr->reset = ata_via_sata_reset; 167 return 0; 168 } 169 /* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */ 170 if (ctlr->chip->max_dma >= ATA_SA150) { 171 ctlr->r_type2 = SYS_RES_IOPORT; 172 ctlr->r_rid2 = PCIR_BAR(5); 173 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 174 &ctlr->r_rid2, RF_ACTIVE))) { 175 ctlr->ch_attach = ata_via_ch_attach; 176 ctlr->ch_detach = ata_via_ch_detach; 177 ctlr->reset = ata_via_reset; 178 } 179 if (ctlr->chip->cfg2 & VIABAR) { 180 ctlr->channels = 3; 181 ctlr->setmode = ata_via_new_setmode; 182 } else 183 ctlr->setmode = ata_sata_setmode; 184 ctlr->getrev = ata_sata_getrev; 185 return 0; 186 } 187 188 /* prepare for ATA-66 on the 82C686a and 82C596b */ 189 if (ctlr->chip->cfg2 & VIACLK) 190 pci_write_config(dev, 0x50, 0x030b030b, 4); 191 192 /* the southbridge might need the data corruption fix */ 193 if (ctlr->chip->cfg2 & VIABUG) 194 ata_via_southbridge_fixup(dev); 195 196 /* set fifo configuration half'n'half */ 197 pci_write_config(dev, 0x43, 198 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 199 200 /* set status register read retry */ 201 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 202 203 /* set DMA read & end-of-sector fifo flush */ 204 pci_write_config(dev, 0x46, 205 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 206 207 /* set sector size */ 208 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 209 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 210 211 ctlr->setmode = ata_via_old_setmode; 212 return 0; 213} 214 215static int 216ata_via_ch_attach(device_t dev) 217{ 218 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 219 struct ata_channel *ch = device_get_softc(dev); 220 221 /* newer SATA chips has resources in one BAR for each channel */ 222 if (ctlr->chip->cfg2 & VIABAR) { 223 struct resource *r_io; 224 int i, rid; 225 226 ata_pci_dmainit(dev); 227 228 rid = PCIR_BAR(ch->unit); 229 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 230 SYS_RES_IOPORT, 231 &rid, RF_ACTIVE))) 232 return ENXIO; 233 234 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 235 ch->r_io[i].res = r_io; 236 ch->r_io[i].offset = i; 237 } 238 ch->r_io[ATA_CONTROL].res = r_io; 239 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 240 ch->r_io[ATA_IDX_ADDR].res = r_io; 241 ata_default_registers(dev); 242 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 243 ch->r_io[i].res = ctlr->r_res1; 244 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 245 } 246 ata_pci_hw(dev); 247 if (ch->unit >= 2) 248 return 0; 249 } 250 else { 251 /* setup the usual register normal pci style */ 252 if (ata_pci_ch_attach(dev)) 253 return ENXIO; 254 } 255 256 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 257 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 258 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 259 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 260 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 261 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 262 ch->hw.status = ata_via_status; 263 ch->flags |= ATA_NO_SLAVE; 264 ch->flags |= ATA_SATA; 265 ch->flags |= ATA_PERIODIC_POLL; 266 267 ata_sata_scr_write(ch, -1, ATA_SERROR, 0xffffffff); 268 269 return 0; 270} 271 272static int 273ata_via_ch_detach(device_t dev) 274{ 275 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 276 struct ata_channel *ch = device_get_softc(dev); 277 278 /* newer SATA chips has resources in one BAR for each channel */ 279 if (ctlr->chip->cfg2 & VIABAR) { 280 int rid; 281 282 rid = PCIR_BAR(ch->unit); 283 bus_release_resource(device_get_parent(dev), 284 SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res); 285 286 ata_pci_dmafini(dev); 287 } 288 else { 289 /* setup the usual register normal pci style */ 290 if (ata_pci_ch_detach(dev)) 291 return ENXIO; 292 } 293 294 return 0; 295} 296 297static void 298ata_via_reset(device_t dev) 299{ 300 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 301 struct ata_channel *ch = device_get_softc(dev); 302 303 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 304 ata_generic_reset(dev); 305 else { 306 if (ata_sata_phy_reset(dev, -1, 1)) 307 ata_generic_reset(dev); 308 else 309 ch->devices = 0; 310 } 311} 312 313static int 314ata_via_status(device_t dev) 315{ 316 317 ata_sata_phy_check_events(dev, -1); 318 return (ata_pci_status(dev)); 319} 320 321static int 322ata_via_new_setmode(device_t dev, int target, int mode) 323{ 324 device_t parent = device_get_parent(dev); 325 struct ata_pci_controller *ctlr = device_get_softc(parent); 326 struct ata_channel *ch = device_get_softc(dev); 327 328 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 329 int piomode; 330 static const uint8_t pio_timings[] = 331 { 0xa8, 0x65, 0x65, 0x32, 0x20 }; 332 static const uint8_t dma_timings[] = 333 { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 334 335 /* This chip can't do WDMA. */ 336 if (mode >= ATA_WDMA0 && mode < ATA_UDMA0) 337 mode = ATA_PIO4; 338 if (mode >= ATA_UDMA0) { 339 pci_write_config(parent, 0xb3, 340 dma_timings[mode & ATA_MODE_MASK], 1); 341 piomode = ATA_PIO4; 342 } else 343 piomode = mode; 344 pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1); 345 } else 346 mode = ata_sata_setmode(dev, target, mode); 347 return (mode); 348} 349 350static int 351ata_via_old_setmode(device_t dev, int target, int mode) 352{ 353 device_t parent = device_get_parent(dev); 354 struct ata_pci_controller *ctlr = device_get_softc(parent); 355 struct ata_channel *ch = device_get_softc(dev); 356 int devno = (ch->unit << 1) + target; 357 int reg = 0x53 - devno; 358 int piomode; 359 static const uint8_t timings[] = 360 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 }; 361 static const uint8_t modes[][7] = { 362 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 363 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 364 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 365 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */ 366 367 mode = min(mode, ctlr->chip->max_dma); 368 /* Set UDMA timings */ 369 if (mode >= ATA_UDMA0) { 370 pci_write_config(parent, reg, 371 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 372 piomode = ATA_PIO4; 373 } else { 374 pci_write_config(parent, reg, 0x8b, 1); 375 piomode = mode; 376 } 377 /* Set WDMA/PIO timings */ 378 pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1); 379 return (mode); 380} 381 382static void 383ata_via_southbridge_fixup(device_t dev) 384{ 385 device_t *children; 386 int nchildren, i; 387 388 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 389 return; 390 391 for (i = 0; i < nchildren; i++) { 392 if (pci_get_devid(children[i]) == ATA_VIA8363 || 393 pci_get_devid(children[i]) == ATA_VIA8371 || 394 pci_get_devid(children[i]) == ATA_VIA8662 || 395 pci_get_devid(children[i]) == ATA_VIA8361) { 396 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 397 398 if ((reg76 & 0xf0) != 0xd0) { 399 device_printf(dev, 400 "Correcting VIA config for southbridge data corruption bug\n"); 401 pci_write_config(children[i], 0x75, 0x80, 1); 402 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 403 } 404 break; 405 } 406 } 407 free(children, M_TEMP); 408} 409 410static int 411ata_via_sata_ch_attach(device_t dev) 412{ 413 struct ata_channel *ch = device_get_softc(dev); 414 415 if (ata_pci_ch_attach(dev)) 416 return ENXIO; 417 if (ch->unit == 0) { 418 ch->hw.status = ata_via_sata_status; 419 ch->hw.pm_read = ata_via_sata_scr_read; 420 ch->hw.pm_write = ata_via_sata_scr_write; 421 ch->flags |= ATA_PERIODIC_POLL; 422 ch->flags |= ATA_SATA; 423 ata_sata_scr_write(ch, 0, ATA_SERROR, 0xffffffff); 424 ata_sata_scr_write(ch, 1, ATA_SERROR, 0xffffffff); 425 } 426 return (0); 427} 428 429static int 430ata_via_sata_getrev(device_t dev, int target) 431{ 432 device_t parent = device_get_parent(dev); 433 struct ata_channel *ch = device_get_softc(dev); 434 435 if (ch->unit == 0) { 436 if (pci_read_config(parent, 0xa0 + target, 1) & 0x10) 437 return (2); 438 else 439 return (1); 440 } 441 return (0); 442} 443 444static int 445ata_via_sata_setmode(device_t dev, int target, int mode) 446{ 447 struct ata_channel *ch = device_get_softc(dev); 448 449 if (ch->unit == 0) 450 return (mode); 451 return (ata_via_old_setmode(dev, target, mode)); 452} 453 454static void 455ata_via_sata_reset(device_t dev) 456{ 457 struct ata_channel *ch = device_get_softc(dev); 458 int devs; 459 460 if (ch->unit == 0) { 461 devs = ata_sata_phy_reset(dev, 0, 0); 462 DELAY(10000); 463 devs += ata_sata_phy_reset(dev, 1, 0); 464 } else 465 devs = 1; 466 if (devs) 467 ata_generic_reset(dev); 468 else 469 ch->devices = 0; 470} 471 472static int 473ata_via_sata_scr_read(device_t dev, int port, int reg, u_int32_t *result) 474{ 475 device_t parent; 476 uint32_t val; 477 478 parent = device_get_parent(dev); 479 port = (port == 1) ? 1 : 0; 480 switch (reg) { 481 case ATA_SSTATUS: 482 val = pci_read_config(parent, 0xa0 + port, 1); 483 *result = val & 0x03; 484 if (*result != ATA_SS_DET_NO_DEVICE) { 485 if (val & 0x04) 486 *result |= ATA_SS_IPM_PARTIAL; 487 else if (val & 0x08) 488 *result |= ATA_SS_IPM_SLUMBER; 489 else 490 *result |= ATA_SS_IPM_ACTIVE; 491 if (val & 0x10) 492 *result |= ATA_SS_SPD_GEN2; 493 else 494 *result |= ATA_SS_SPD_GEN1; 495 } 496 break; 497 case ATA_SERROR: 498 *result = pci_read_config(parent, 0xa8 + port * 4, 4); 499 break; 500 case ATA_SCONTROL: 501 val = pci_read_config(parent, 0xa4 + port, 1); 502 *result = 0; 503 if (val & 0x01) 504 *result |= ATA_SC_DET_RESET; 505 if (val & 0x02) 506 *result |= ATA_SC_DET_DISABLE; 507 if (val & 0x04) 508 *result |= ATA_SC_IPM_DIS_PARTIAL; 509 if (val & 0x08) 510 *result |= ATA_SC_IPM_DIS_SLUMBER; 511 break; 512 default: 513 return (EINVAL); 514 } 515 return (0); 516} 517 518static int 519ata_via_sata_scr_write(device_t dev, int port, int reg, u_int32_t value) 520{ 521 device_t parent; 522 uint32_t val; 523 524 parent = device_get_parent(dev); 525 port = (port == 1) ? 1 : 0; 526 switch (reg) { 527 case ATA_SERROR: 528 pci_write_config(parent, 0xa8 + port * 4, value, 4); 529 break; 530 case ATA_SCONTROL: 531 val = 0; 532 if (value & ATA_SC_DET_RESET) 533 val |= 0x01; 534 if (value & ATA_SC_DET_DISABLE) 535 val |= 0x02; 536 if (value & ATA_SC_IPM_DIS_PARTIAL) 537 val |= 0x04; 538 if (value & ATA_SC_IPM_DIS_SLUMBER) 539 val |= 0x08; 540 pci_write_config(parent, 0xa4 + port, val, 1); 541 break; 542 default: 543 return (EINVAL); 544 } 545 return (0); 546} 547 548static int 549ata_via_sata_status(device_t dev) 550{ 551 552 ata_sata_phy_check_events(dev, 0); 553 ata_sata_phy_check_events(dev, 1); 554 return (ata_pci_status(dev)); 555} 556 557ATA_DECLARE_DRIVER(ata_via); 558MODULE_DEPEND(ata_via, ata_ahci, 1, 1, 1); 559