1183724Ssos/*- 2183724Ssos * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3183724Ssos * All rights reserved. 4183724Ssos * 5183724Ssos * Redistribution and use in source and binary forms, with or without 6183724Ssos * modification, are permitted provided that the following conditions 7183724Ssos * are met: 8183724Ssos * 1. Redistributions of source code must retain the above copyright 9183724Ssos * notice, this list of conditions and the following disclaimer, 10183724Ssos * without modification, immediately at the beginning of the file. 11183724Ssos * 2. Redistributions in binary form must reproduce the above copyright 12183724Ssos * notice, this list of conditions and the following disclaimer in the 13183724Ssos * documentation and/or other materials provided with the distribution. 14183724Ssos * 15183724Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183724Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17183724Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18183724Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19183724Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20183724Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21183724Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22183724Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23183724Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24183724Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25183724Ssos */ 26183724Ssos 27183724Ssos#include <sys/cdefs.h> 28183724Ssos__FBSDID("$FreeBSD$"); 29183724Ssos 30183724Ssos#include "opt_ata.h" 31183724Ssos#include <sys/param.h> 32183724Ssos#include <sys/module.h> 33183724Ssos#include <sys/systm.h> 34183724Ssos#include <sys/kernel.h> 35183724Ssos#include <sys/ata.h> 36183724Ssos#include <sys/bus.h> 37183724Ssos#include <sys/endian.h> 38183724Ssos#include <sys/malloc.h> 39183724Ssos#include <sys/lock.h> 40183724Ssos#include <sys/mutex.h> 41183724Ssos#include <sys/sema.h> 42183724Ssos#include <sys/taskqueue.h> 43183724Ssos#include <vm/uma.h> 44183724Ssos#include <machine/stdarg.h> 45183724Ssos#include <machine/resource.h> 46183724Ssos#include <machine/bus.h> 47183724Ssos#include <sys/rman.h> 48183724Ssos#include <dev/pci/pcivar.h> 49183724Ssos#include <dev/pci/pcireg.h> 50183724Ssos#include <dev/ata/ata-all.h> 51183724Ssos#include <dev/ata/ata-pci.h> 52183724Ssos#include <ata_if.h> 53183724Ssos 54183724Ssos/* local prototypes */ 55183724Ssosstatic int ata_highpoint_chipinit(device_t dev); 56188765Smavstatic int ata_highpoint_ch_attach(device_t dev); 57200171Smavstatic int ata_highpoint_setmode(device_t dev, int target, int mode); 58183724Ssosstatic int ata_highpoint_check_80pin(device_t dev, int mode); 59183724Ssos 60183724Ssos/* misc defines */ 61183724Ssos#define HPT_366 0 62183724Ssos#define HPT_370 1 63183724Ssos#define HPT_372 2 64183724Ssos#define HPT_374 3 65183724Ssos#define HPT_OLD 1 66183724Ssos 67183724Ssos 68183724Ssos/* 69183724Ssos * HighPoint chipset support functions 70183724Ssos */ 71183724Ssosstatic int 72183724Ssosata_highpoint_probe(device_t dev) 73183724Ssos{ 74183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 75233717Smarius const struct ata_chip_id *idx; 76242908Sdim static const struct ata_chip_id ids[] = 77183724Ssos {{ ATA_HPT374, 0x07, HPT_374, 0, ATA_UDMA6, "HPT374" }, 78183724Ssos { ATA_HPT372, 0x02, HPT_372, 0, ATA_UDMA6, "HPT372N" }, 79183724Ssos { ATA_HPT372, 0x01, HPT_372, 0, ATA_UDMA6, "HPT372" }, 80183724Ssos { ATA_HPT371, 0x01, HPT_372, 0, ATA_UDMA6, "HPT371" }, 81183724Ssos { ATA_HPT366, 0x05, HPT_372, 0, ATA_UDMA6, "HPT372" }, 82183724Ssos { ATA_HPT366, 0x03, HPT_370, 0, ATA_UDMA5, "HPT370" }, 83183724Ssos { ATA_HPT366, 0x02, HPT_366, 0, ATA_UDMA4, "HPT368" }, 84183724Ssos { ATA_HPT366, 0x00, HPT_366, HPT_OLD, ATA_UDMA4, "HPT366" }, 85183724Ssos { ATA_HPT302, 0x01, HPT_372, 0, ATA_UDMA6, "HPT302" }, 86183724Ssos { 0, 0, 0, 0, 0, 0}}; 87183724Ssos char buffer[64]; 88183724Ssos 89183724Ssos if (pci_get_vendor(dev) != ATA_HIGHPOINT_ID) 90183724Ssos return ENXIO; 91183724Ssos 92183724Ssos if (!(idx = ata_match_chip(dev, ids))) 93183724Ssos return ENXIO; 94183724Ssos 95183724Ssos strcpy(buffer, "HighPoint "); 96183724Ssos strcat(buffer, idx->text); 97183724Ssos if (idx->cfg1 == HPT_374) { 98183724Ssos if (pci_get_function(dev) == 0) 99183724Ssos strcat(buffer, " (channel 0+1)"); 100183724Ssos if (pci_get_function(dev) == 1) 101183724Ssos strcat(buffer, " (channel 2+3)"); 102183724Ssos } 103183724Ssos sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 104183724Ssos device_set_desc_copy(dev, buffer); 105183724Ssos ctlr->chip = idx; 106183724Ssos ctlr->chipinit = ata_highpoint_chipinit; 107194893Smav return (BUS_PROBE_DEFAULT); 108183724Ssos} 109183724Ssos 110183724Ssosstatic int 111183724Ssosata_highpoint_chipinit(device_t dev) 112183724Ssos{ 113183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 114183724Ssos 115183724Ssos if (ata_setup_interrupt(dev, ata_generic_intr)) 116183724Ssos return ENXIO; 117183724Ssos 118183724Ssos if (ctlr->chip->cfg2 == HPT_OLD) { 119183724Ssos /* disable interrupt prediction */ 120183724Ssos pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 121183724Ssos } 122183724Ssos else { 123183724Ssos /* disable interrupt prediction */ 124183724Ssos pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 125183724Ssos pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 126183724Ssos 127183724Ssos /* enable interrupts */ 128183724Ssos pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 129183724Ssos 130183724Ssos /* set clocks etc */ 131183724Ssos if (ctlr->chip->cfg1 < HPT_372) 132183724Ssos pci_write_config(dev, 0x5b, 0x22, 1); 133183724Ssos else 134183724Ssos pci_write_config(dev, 0x5b, 135183724Ssos (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 136183724Ssos } 137188765Smav ctlr->ch_attach = ata_highpoint_ch_attach; 138188769Smav ctlr->ch_detach = ata_pci_ch_detach; 139183724Ssos ctlr->setmode = ata_highpoint_setmode; 140183724Ssos return 0; 141183724Ssos} 142183724Ssos 143183724Ssosstatic int 144188765Smavata_highpoint_ch_attach(device_t dev) 145183724Ssos{ 146200171Smav struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 147200171Smav struct ata_channel *ch = device_get_softc(dev); 148183724Ssos 149200171Smav /* setup the usual register normal pci style */ 150200171Smav if (ata_pci_ch_attach(dev)) 151200171Smav return (ENXIO); 152200171Smav ch->flags |= ATA_ALWAYS_DMASTAT; 153200171Smav ch->flags |= ATA_CHECKS_CABLE; 154200171Smav if (ctlr->chip->cfg1 == HPT_366) 155200171Smav ch->flags |= ATA_NO_ATAPI_DMA; 156200171Smav return (0); 157183724Ssos} 158183724Ssos 159200171Smavstatic int 160200171Smavata_highpoint_setmode(device_t dev, int target, int mode) 161183724Ssos{ 162200171Smav device_t parent = device_get_parent(dev); 163200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 164200171Smav struct ata_channel *ch = device_get_softc(dev); 165200171Smav int devno = (ch->unit << 1) + target; 166233717Smarius static const uint32_t timings33[][4] = { 167233717Smarius /* HPT366 HPT370 HPT372 HPT374 mode */ 168183724Ssos { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ 169183724Ssos { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ 170183724Ssos { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ 171183724Ssos { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ 172183724Ssos { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ 173183724Ssos { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ 174183724Ssos { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ 175183724Ssos { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ 176183724Ssos { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */ 177183724Ssos { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */ 178183724Ssos { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */ 179183724Ssos { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */ 180183724Ssos { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */ 181183724Ssos { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */ 182183724Ssos { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */ 183200171Smav }; 184183724Ssos 185200171Smav mode = min(mode, ctlr->chip->max_dma); 186200171Smav mode = ata_highpoint_check_80pin(dev, mode); 187200171Smav /* 188200171Smav * most if not all HPT chips cant really handle that the device is 189200171Smav * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to 190200171Smav * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance 191200171Smav */ 192200171Smav mode = min(mode, ATA_UDMA5); 193200171Smav pci_write_config(parent, 0x40 + (devno << 2), 194183724Ssos timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 195200171Smav return (mode); 196183724Ssos} 197183724Ssos 198183724Ssosstatic int 199183724Ssosata_highpoint_check_80pin(device_t dev, int mode) 200183724Ssos{ 201200171Smav device_t parent = device_get_parent(dev); 202200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 203200171Smav struct ata_channel *ch = device_get_softc(dev); 204183724Ssos u_int8_t reg, val, res; 205183724Ssos 206200171Smav if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) { 207183724Ssos reg = ch->unit ? 0x57 : 0x53; 208200171Smav val = pci_read_config(parent, reg, 1); 209200171Smav pci_write_config(parent, reg, val | 0x80, 1); 210183724Ssos } 211183724Ssos else { 212183724Ssos reg = 0x5b; 213200171Smav val = pci_read_config(parent, reg, 1); 214200171Smav pci_write_config(parent, reg, val & 0xfe, 1); 215183724Ssos } 216200171Smav res = pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x1:0x2); 217200171Smav pci_write_config(parent, reg, val, 1); 218183724Ssos 219209872Smav if (ata_dma_check_80pin && mode > ATA_UDMA2 && res) { 220183724Ssos ata_print_cable(dev, "controller"); 221183724Ssos mode = ATA_UDMA2; 222183724Ssos } 223183724Ssos return mode; 224183724Ssos} 225183724Ssos 226183724SsosATA_DECLARE_DRIVER(ata_highpoint); 227