1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_promise_chipinit(device_t dev); 56static int ata_promise_ch_attach(device_t dev); 57static int ata_promise_status(device_t dev); 58static int ata_promise_dmastart(struct ata_request *request); 59static int ata_promise_dmastop(struct ata_request *request); 60static void ata_promise_dmareset(device_t dev); 61static int ata_promise_setmode(device_t dev, int target, int mode); 62static int ata_promise_tx2_ch_attach(device_t dev); 63static int ata_promise_tx2_status(device_t dev); 64static int ata_promise_mio_ch_attach(device_t dev); 65static int ata_promise_mio_ch_detach(device_t dev); 66static void ata_promise_mio_intr(void *data); 67static int ata_promise_mio_status(device_t dev); 68static int ata_promise_mio_command(struct ata_request *request); 69static void ata_promise_mio_reset(device_t dev); 70static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result); 71static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result); 72static u_int32_t ata_promise_mio_softreset(device_t dev, int port); 73static void ata_promise_mio_dmainit(device_t dev); 74static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 75static int ata_promise_mio_setmode(device_t dev, int target, int mode); 76static int ata_promise_mio_getrev(device_t dev, int target); 77static void ata_promise_sx4_intr(void *data); 78static int ata_promise_sx4_command(struct ata_request *request); 79static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 80static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 81static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 82 83/* misc defines */ 84#define PR_OLD 0 85#define PR_NEW 1 86#define PR_TX 2 87#define PR_MIO 3 88#define PR_TX4 0x01 89#define PR_SX4X 0x02 90#define PR_SX6K 0x04 91#define PR_PATA 0x08 92#define PR_CMBO 0x10 93#define PR_CMBO2 0x20 94#define PR_SATA 0x40 95#define PR_SATA2 0x80 96 97/* 98 * Promise chipset support functions 99 */ 100#define ATA_PDC_APKT_OFFSET 0x00000010 101#define ATA_PDC_HPKT_OFFSET 0x00000040 102#define ATA_PDC_ASG_OFFSET 0x00000080 103#define ATA_PDC_LSG_OFFSET 0x000000c0 104#define ATA_PDC_HSG_OFFSET 0x00000100 105#define ATA_PDC_CHN_OFFSET 0x00000400 106#define ATA_PDC_BUF_BASE 0x00400000 107#define ATA_PDC_BUF_OFFSET 0x00100000 108#define ATA_PDC_MAX_HPKT 8 109#define ATA_PDC_WRITE_REG 0x00 110#define ATA_PDC_WRITE_CTL 0x0e 111#define ATA_PDC_WRITE_END 0x08 112#define ATA_PDC_WAIT_NBUSY 0x10 113#define ATA_PDC_WAIT_READY 0x18 114#define ATA_PDC_1B 0x20 115#define ATA_PDC_2B 0x40 116 117struct host_packet { 118 u_int32_t addr; 119 TAILQ_ENTRY(host_packet) chain; 120}; 121 122struct ata_promise_sx4 { 123 struct mtx mtx; 124 TAILQ_HEAD(, host_packet) queue; 125 int busy; 126}; 127 128static int 129ata_promise_probe(device_t dev) 130{ 131 struct ata_pci_controller *ctlr = device_get_softc(dev); 132 const struct ata_chip_id *idx; 133 static const struct ata_chip_id ids[] = 134 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" }, 135 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" }, 136 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" }, 137 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" }, 138 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" }, 139 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" }, 140 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" }, 141 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" }, 142 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" }, 143 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" }, 144 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" }, 145 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" }, 146 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" }, 147 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" }, 148 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" }, 149 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" }, 150 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" }, 151 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" }, 152 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" }, 153 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" }, 154 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" }, 155 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" }, 156 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" }, 157 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" }, 158 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" }, 159 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" }, 160 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" }, 161 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" }, 162 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" }, 163 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" }, 164 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" }, 165 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" }, 166 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" }, 167 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" }, 168 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" }, 169 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" }, 170 { 0, 0, 0, 0, 0, 0}}; 171 char buffer[64]; 172 uintptr_t devid = 0; 173 174 if (pci_get_vendor(dev) != ATA_PROMISE_ID) 175 return ENXIO; 176 177 if (!(idx = ata_match_chip(dev, ids))) 178 return ENXIO; 179 180 /* if we are on a SuperTrak SX6000 dont attach */ 181 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 182 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 183 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 184 devid == ATA_I960RM) 185 return ENXIO; 186 187 strcpy(buffer, "Promise "); 188 strcat(buffer, idx->text); 189 190 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 191 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 192 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 193 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 194 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 195 static long start = 0, end = 0; 196 197 if (pci_get_slot(dev) == 1) { 198 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 199 strcat(buffer, " (channel 0+1)"); 200 } 201 else if (pci_get_slot(dev) == 2 && start && end) { 202 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 203 strcat(buffer, " (channel 2+3)"); 204 } 205 else { 206 start = end = 0; 207 } 208 } 209 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 210 device_set_desc_copy(dev, buffer); 211 ctlr->chip = idx; 212 ctlr->chipinit = ata_promise_chipinit; 213 return (BUS_PROBE_DEFAULT); 214} 215 216static int 217ata_promise_chipinit(device_t dev) 218{ 219 struct ata_pci_controller *ctlr = device_get_softc(dev); 220 int stat_reg; 221 222 if (ata_setup_interrupt(dev, ata_generic_intr)) 223 return ENXIO; 224 225 switch (ctlr->chip->cfg1) { 226 case PR_NEW: 227 /* setup clocks */ 228 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 229 /* FALLTHROUGH */ 230 231 case PR_OLD: 232 /* enable burst mode */ 233 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 234 ctlr->ch_attach = ata_promise_ch_attach; 235 ctlr->ch_detach = ata_pci_ch_detach; 236 ctlr->setmode = ata_promise_setmode; 237 return 0; 238 239 case PR_TX: 240 ctlr->ch_attach = ata_promise_tx2_ch_attach; 241 ctlr->ch_detach = ata_pci_ch_detach; 242 ctlr->setmode = ata_promise_setmode; 243 return 0; 244 245 case PR_MIO: 246 ctlr->r_type1 = SYS_RES_MEMORY; 247 ctlr->r_rid1 = PCIR_BAR(4); 248 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 249 &ctlr->r_rid1, RF_ACTIVE))) 250 goto failnfree; 251 252#ifdef __sparc64__ 253 if (ctlr->chip->cfg2 == PR_SX4X && 254 !bus_space_map(rman_get_bustag(ctlr->r_res1), 255 rman_get_bushandle(ctlr->r_res1), rman_get_size(ctlr->r_res1), 256 BUS_SPACE_MAP_LINEAR, NULL)) 257 goto failnfree; 258#endif 259 260 ctlr->r_type2 = SYS_RES_MEMORY; 261 ctlr->r_rid2 = PCIR_BAR(3); 262 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 263 &ctlr->r_rid2, RF_ACTIVE))) 264 goto failnfree; 265 266 if (ctlr->chip->cfg2 == PR_SX4X) { 267 struct ata_promise_sx4 *hpkt; 268 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 269 270 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 271 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 272 ata_promise_sx4_intr, ctlr, &ctlr->handle)) { 273 device_printf(dev, "unable to setup interrupt\n"); 274 goto failnfree; 275 } 276 277 /* print info about cache memory */ 278 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 279 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 280 ((dimm >> 24) & 0xff), 281 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 282 " ECC enabled" : "" ); 283 284 /* adjust cache memory parameters */ 285 ATA_OUTL(ctlr->r_res2, 0x000c000c, 286 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 287 288 /* setup host packet controls */ 289 hpkt = malloc(sizeof(struct ata_promise_sx4), 290 M_ATAPCI, M_NOWAIT | M_ZERO); 291 if (hpkt == NULL) { 292 device_printf(dev, "Cannot allocate HPKT\n"); 293 goto failnfree; 294 } 295 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF); 296 TAILQ_INIT(&hpkt->queue); 297 hpkt->busy = 0; 298 ctlr->chipset_data = hpkt; 299 ctlr->ch_attach = ata_promise_mio_ch_attach; 300 ctlr->ch_detach = ata_promise_mio_ch_detach; 301 ctlr->reset = ata_promise_mio_reset; 302 ctlr->setmode = ata_promise_setmode; 303 ctlr->channels = 4; 304 return 0; 305 } 306 307 /* mio type controllers need an interrupt intercept */ 308 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 309 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 310 ata_promise_mio_intr, ctlr, &ctlr->handle)) { 311 device_printf(dev, "unable to setup interrupt\n"); 312 goto failnfree; 313 } 314 315 switch (ctlr->chip->cfg2) { 316 case PR_PATA: 317 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 318 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 319 goto sata150; 320 case PR_CMBO: 321 ctlr->channels = 3; 322 goto sata150; 323 case PR_SATA: 324 ctlr->channels = 4; 325sata150: 326 stat_reg = 0x6c; 327 break; 328 329 case PR_CMBO2: 330 ctlr->channels = 3; 331 goto sataii; 332 case PR_SATA2: 333 default: 334 ctlr->channels = 4; 335sataii: 336 stat_reg = 0x60; 337 break; 338 } 339 340 /* prime fake interrupt register */ 341 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 342 343 /* clear SATA status and unmask interrupts */ 344 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 345 346 /* enable "long burst length" on gen2 chips */ 347 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) 348 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000); 349 350 ctlr->ch_attach = ata_promise_mio_ch_attach; 351 ctlr->ch_detach = ata_promise_mio_ch_detach; 352 ctlr->reset = ata_promise_mio_reset; 353 ctlr->setmode = ata_promise_mio_setmode; 354 ctlr->getrev = ata_promise_mio_getrev; 355 356 return 0; 357 } 358 359failnfree: 360 if (ctlr->r_res2) 361 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 362 if (ctlr->r_res1) 363 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 364 return ENXIO; 365} 366 367static int 368ata_promise_ch_attach(device_t dev) 369{ 370 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 371 struct ata_channel *ch = device_get_softc(dev); 372 373 if (ata_pci_ch_attach(dev)) 374 return ENXIO; 375 376 if (ctlr->chip->cfg1 == PR_NEW) { 377 ch->dma.start = ata_promise_dmastart; 378 ch->dma.stop = ata_promise_dmastop; 379 ch->dma.reset = ata_promise_dmareset; 380 } 381 382 ch->hw.status = ata_promise_status; 383 ch->flags |= ATA_NO_ATAPI_DMA; 384 ch->flags |= ATA_CHECKS_CABLE; 385 return 0; 386} 387 388static int 389ata_promise_status(device_t dev) 390{ 391 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 392 struct ata_channel *ch = device_get_softc(dev); 393 394 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 395 return ata_pci_status(dev); 396 } 397 return 0; 398} 399 400static int 401ata_promise_dmastart(struct ata_request *request) 402{ 403 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 404 struct ata_channel *ch = device_get_softc(request->parent); 405 406 if (request->flags & ATA_R_48BIT) { 407 ATA_OUTB(ctlr->r_res1, 0x11, 408 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 409 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 410 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) | 411 (request->bytecount >> 1)); 412 } 413 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 414 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 415 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus); 416 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 417 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) | 418 ATA_BMCMD_START_STOP); 419 ch->dma.flags |= ATA_DMA_ACTIVE; 420 return 0; 421} 422 423static int 424ata_promise_dmastop(struct ata_request *request) 425{ 426 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 427 struct ata_channel *ch = device_get_softc(request->parent); 428 int error; 429 430 if (request->flags & ATA_R_48BIT) { 431 ATA_OUTB(ctlr->r_res1, 0x11, 432 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 433 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 434 } 435 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 436 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 437 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 438 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 439 ch->dma.flags &= ~ATA_DMA_ACTIVE; 440 return error; 441} 442 443static void 444ata_promise_dmareset(device_t dev) 445{ 446 struct ata_channel *ch = device_get_softc(dev); 447 448 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 449 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 450 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 451 ch->flags &= ~ATA_DMA_ACTIVE; 452} 453 454static int 455ata_promise_setmode(device_t dev, int target, int mode) 456{ 457 device_t parent = device_get_parent(dev); 458 struct ata_pci_controller *ctlr = device_get_softc(parent); 459 struct ata_channel *ch = device_get_softc(dev); 460 int devno = (ch->unit << 1) + target; 461 static const uint32_t timings[][2] = { 462 /* PR_OLD PR_NEW mode */ 463 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 464 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 465 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 466 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 467 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 468 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 469 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 470 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 471 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 472 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 473 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 474 { 0, 0x00424ef6 }, /* UDMA 3 */ 475 { 0, 0x004127f3 }, /* UDMA 4 */ 476 { 0, 0x004127f3 } /* UDMA 5 */ 477 }; 478 479 mode = min(mode, ctlr->chip->max_dma); 480 481 switch (ctlr->chip->cfg1) { 482 case PR_OLD: 483 case PR_NEW: 484 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 485 (pci_read_config(parent, 0x50, 2) & 486 (ch->unit ? 1 << 11 : 1 << 10))) { 487 ata_print_cable(dev, "controller"); 488 mode = ATA_UDMA2; 489 } 490 break; 491 492 case PR_TX: 493 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 494 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 495 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 496 ata_print_cable(dev, "controller"); 497 mode = ATA_UDMA2; 498 } 499 break; 500 501 case PR_MIO: 502 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 503 (ATA_INL(ctlr->r_res2, 504 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) + 505 (ch->unit << 7)) & 0x01000000)) { 506 ata_print_cable(dev, "controller"); 507 mode = ATA_UDMA2; 508 } 509 break; 510 } 511 512 if (ctlr->chip->cfg1 < PR_TX) 513 pci_write_config(parent, 0x60 + (devno << 2), 514 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 515 return (mode); 516} 517 518static int 519ata_promise_tx2_ch_attach(device_t dev) 520{ 521 struct ata_channel *ch = device_get_softc(dev); 522 523 if (ata_pci_ch_attach(dev)) 524 return ENXIO; 525 526 ch->hw.status = ata_promise_tx2_status; 527 ch->flags |= ATA_CHECKS_CABLE; 528 return 0; 529} 530 531static int 532ata_promise_tx2_status(device_t dev) 533{ 534 struct ata_channel *ch = device_get_softc(dev); 535 536 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 537 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 538 return ata_pci_status(dev); 539 } 540 return 0; 541} 542 543static int 544ata_promise_mio_ch_attach(device_t dev) 545{ 546 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 547 struct ata_channel *ch = device_get_softc(dev); 548 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0; 549 int i; 550 551 ata_promise_mio_dmainit(dev); 552 553 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 554 ch->r_io[i].res = ctlr->r_res2; 555 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 556 } 557 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 558 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 559 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 560 ata_default_registers(dev); 561 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) || 562 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) { 563 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 564 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 565 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 566 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 567 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 568 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 569 ch->flags |= ATA_NO_SLAVE; 570 ch->flags |= ATA_SATA; 571 } 572 ch->flags |= ATA_USE_16BIT; 573 ch->flags |= ATA_CHECKS_CABLE; 574 575 ata_generic_hw(dev); 576 if (ctlr->chip->cfg2 & PR_SX4X) { 577 ch->hw.command = ata_promise_sx4_command; 578 } 579 else { 580 ch->hw.command = ata_promise_mio_command; 581 ch->hw.status = ata_promise_mio_status; 582 ch->hw.softreset = ata_promise_mio_softreset; 583 ch->hw.pm_read = ata_promise_mio_pm_read; 584 ch->hw.pm_write = ata_promise_mio_pm_write; 585 } 586 return 0; 587} 588 589static int 590ata_promise_mio_ch_detach(device_t dev) 591{ 592 593 ata_dmafini(dev); 594 return (0); 595} 596 597static void 598ata_promise_mio_intr(void *data) 599{ 600 struct ata_pci_controller *ctlr = data; 601 struct ata_channel *ch; 602 u_int32_t vector; 603 int unit; 604 605 /* 606 * since reading interrupt status register on early "mio" chips 607 * clears the status bits we cannot read it for each channel later on 608 * in the generic interrupt routine. 609 */ 610 vector = ATA_INL(ctlr->r_res2, 0x040); 611 ATA_OUTL(ctlr->r_res2, 0x040, vector); 612 ctlr->chipset_data = (void *)(uintptr_t)vector; 613 614 for (unit = 0; unit < ctlr->channels; unit++) { 615 if ((ch = ctlr->interrupt[unit].argument)) 616 ctlr->interrupt[unit].function(ch); 617 } 618 619 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 620} 621 622static int 623ata_promise_mio_status(device_t dev) 624{ 625 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 626 struct ata_channel *ch = device_get_softc(dev); 627 u_int32_t stat_reg, vector, status; 628 629 switch (ctlr->chip->cfg2) { 630 case PR_PATA: 631 case PR_CMBO: 632 case PR_SATA: 633 stat_reg = 0x6c; 634 break; 635 case PR_CMBO2: 636 case PR_SATA2: 637 default: 638 stat_reg = 0x60; 639 break; 640 } 641 642 /* read and acknowledge interrupt */ 643 vector = (uint32_t)(uintptr_t)ctlr->chipset_data; 644 645 /* read and clear interface status */ 646 status = ATA_INL(ctlr->r_res2, stat_reg); 647 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 648 649 /* check for and handle disconnect events */ 650 if (status & (0x00000001 << ch->unit)) { 651 if (bootverbose) 652 device_printf(dev, "DISCONNECT requested\n"); 653 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 654 } 655 656 /* check for and handle connect events */ 657 if (status & (0x00000010 << ch->unit)) { 658 if (bootverbose) 659 device_printf(dev, "CONNECT requested\n"); 660 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 661 } 662 663 /* do we have any device action ? */ 664 return (vector & (1 << (ch->unit + 1))); 665} 666 667static int 668ata_promise_mio_command(struct ata_request *request) 669{ 670 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 671 struct ata_channel *ch = device_get_softc(request->parent); 672 673 u_int32_t *wordp = (u_int32_t *)ch->dma.work; 674 675 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 676 677 if ((ctlr->chip->cfg2 == PR_SATA2) || 678 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 679 /* set portmultiplier port */ 680 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), request->unit & 0x0f); 681 } 682 683 /* XXX SOS add ATAPI commands support later */ 684 switch (request->u.ata.command) { 685 default: 686 return ata_generic_command(request); 687 688 case ATA_READ_DMA: 689 case ATA_READ_DMA48: 690 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 691 break; 692 693 case ATA_WRITE_DMA: 694 case ATA_WRITE_DMA48: 695 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 696 break; 697 } 698 wordp[1] = htole32(request->dma->sg_bus); 699 wordp[2] = 0; 700 ata_promise_apkt((u_int8_t*)wordp, request); 701 702 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus); 703 return 0; 704} 705 706static void 707ata_promise_mio_reset(device_t dev) 708{ 709 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 710 struct ata_channel *ch = device_get_softc(dev); 711 struct ata_promise_sx4 *hpktp; 712 713 switch (ctlr->chip->cfg2) { 714 case PR_SX4X: 715 716 /* softreset channel ATA module */ 717 hpktp = ctlr->chipset_data; 718 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 719 ata_udelay(1000); 720 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 721 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 722 ~0x00003f9f) | (ch->unit + 1)); 723 724 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 725 mtx_lock(&hpktp->mtx); 726 ATA_OUTL(ctlr->r_res2, 0xc012c, 727 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 728 DELAY(10); 729 ATA_OUTL(ctlr->r_res2, 0xc012c, 730 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 731 hpktp->busy = 0; 732 mtx_unlock(&hpktp->mtx); 733 ata_generic_reset(dev); 734 break; 735 736 case PR_PATA: 737 case PR_CMBO: 738 case PR_SATA: 739 if ((ctlr->chip->cfg2 == PR_SATA) || 740 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 741 742 /* mask plug/unplug intr */ 743 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 744 } 745 746 /* softreset channels ATA module */ 747 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 748 ata_udelay(10000); 749 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 750 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 751 ~0x00003f9f) | (ch->unit + 1)); 752 753 if ((ctlr->chip->cfg2 == PR_SATA) || 754 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 755 756 if (ata_sata_phy_reset(dev, -1, 1)) 757 ata_generic_reset(dev); 758 else 759 ch->devices = 0; 760 761 /* reset and enable plug/unplug intr */ 762 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 763 } 764 else 765 ata_generic_reset(dev); 766 break; 767 768 case PR_CMBO2: 769 case PR_SATA2: 770 if ((ctlr->chip->cfg2 == PR_SATA2) || 771 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 772 /* set portmultiplier port */ 773 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 774 775 /* mask plug/unplug intr */ 776 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 777 } 778 779 /* softreset channels ATA module */ 780 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 781 ata_udelay(10000); 782 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 783 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 784 ~0x00003f9f) | (ch->unit + 1)); 785 786 if ((ctlr->chip->cfg2 == PR_SATA2) || 787 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 788 789 /* set PHY mode to "improved" */ 790 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 791 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 792 ~0x00000003) | 0x00000001); 793 794 if (ata_sata_phy_reset(dev, -1, 1)) { 795 u_int32_t signature = ch->hw.softreset(dev, ATA_PM); 796 797 if (1 | bootverbose) 798 device_printf(dev, "SIGNATURE: %08x\n", signature); 799 800 switch (signature >> 16) { 801 case 0x0000: 802 ch->devices = ATA_ATA_MASTER; 803 break; 804 case 0x9669: 805 ch->devices = ATA_PORTMULTIPLIER; 806 ata_pm_identify(dev); 807 break; 808 case 0xeb14: 809 ch->devices = ATA_ATAPI_MASTER; 810 break; 811 default: /* SOS XXX */ 812 if (bootverbose) 813 device_printf(dev, 814 "No signature, assuming disk device\n"); 815 ch->devices = ATA_ATA_MASTER; 816 } 817 if (bootverbose) 818 device_printf(dev, "promise_mio_reset devices=%08x\n", 819 ch->devices); 820 821 } else 822 ch->devices = 0; 823 824 /* reset and enable plug/unplug intr */ 825 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 826 827 ///* set portmultiplier port */ 828 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 829 } 830 else 831 ata_generic_reset(dev); 832 break; 833 834 } 835} 836 837static int 838ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result) 839{ 840 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 841 struct ata_channel *ch = device_get_softc(dev); 842 int timeout = 0; 843 844 if (port < 0) { 845 *result = ATA_IDX_INL(ch, reg); 846 return (0); 847 } 848 if (port < ATA_PM) { 849 switch (reg) { 850 case ATA_SSTATUS: 851 reg = 0; 852 break; 853 case ATA_SERROR: 854 reg = 1; 855 break; 856 case ATA_SCONTROL: 857 reg = 2; 858 break; 859 default: 860 return (EINVAL); 861 } 862 } 863 /* set portmultiplier port */ 864 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 865 866 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 867 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 868 869 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM); 870 871 while (timeout < 1000000) { 872 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 873 if (!(status & ATA_S_BUSY)) 874 break; 875 timeout += 1000; 876 DELAY(1000); 877 } 878 if (timeout >= 1000000) 879 return ATA_E_ABORT; 880 881 *result = ATA_IDX_INB(ch, ATA_COUNT) | 882 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 883 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 884 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 885 return 0; 886} 887 888static int 889ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value) 890{ 891 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 892 struct ata_channel *ch = device_get_softc(dev); 893 int timeout = 0; 894 895 if (port < 0) { 896 ATA_IDX_OUTL(ch, reg, value); 897 return (0); 898 } 899 if (port < ATA_PM) { 900 switch (reg) { 901 case ATA_SSTATUS: 902 reg = 0; 903 break; 904 case ATA_SERROR: 905 reg = 1; 906 break; 907 case ATA_SCONTROL: 908 reg = 2; 909 break; 910 default: 911 return (EINVAL); 912 } 913 } 914 /* set portmultiplier port */ 915 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 916 917 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 918 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 919 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff); 920 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff); 921 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); 922 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff); 923 924 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM); 925 926 while (timeout < 1000000) { 927 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 928 if (!(status & ATA_S_BUSY)) 929 break; 930 timeout += 1000; 931 DELAY(1000); 932 } 933 if (timeout >= 1000000) 934 return ATA_E_ABORT; 935 936 return ATA_IDX_INB(ch, ATA_ERROR); 937} 938 939/* must be called with ATA channel locked and state_mtx held */ 940static u_int32_t 941ata_promise_mio_softreset(device_t dev, int port) 942{ 943 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 944 struct ata_channel *ch = device_get_softc(dev); 945 int timeout; 946 947 /* set portmultiplier port */ 948 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f); 949 950 /* softreset device on this channel */ 951 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 952 DELAY(10); 953 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 954 ata_udelay(10000); 955 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 956 ata_udelay(150000); 957 ATA_IDX_INB(ch, ATA_ERROR); 958 959 /* wait for BUSY to go inactive */ 960 for (timeout = 0; timeout < 100; timeout++) { 961 u_int8_t err, stat; 962 963 err = ATA_IDX_INB(ch, ATA_ERROR); 964 stat = ATA_IDX_INB(ch, ATA_STATUS); 965 966 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10)) 967 //break; 968 969 if (!(stat & ATA_S_BUSY)) { 970 //if ((err & 0x7f) == ATA_E_ILI) { 971 return ATA_IDX_INB(ch, ATA_COUNT) | 972 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 973 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 974 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 975 //} 976 //else if (stat & 0x0f) { 977 //stat |= ATA_S_BUSY; 978 //} 979 } 980 981 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10)) 982 break; 983 ata_udelay(100000); 984 } 985 return -1; 986} 987 988static void 989ata_promise_mio_dmainit(device_t dev) 990{ 991 struct ata_channel *ch = device_get_softc(dev); 992 993 /* note start and stop are not used here */ 994 ch->dma.setprd = ata_promise_mio_setprd; 995 ch->dma.max_iosize = 65536; 996 ata_dmainit(dev); 997} 998 999#define MAXLASTSGSIZE (32 * sizeof(u_int32_t)) 1000static void 1001ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1002{ 1003 struct ata_dmasetprd_args *args = xsc; 1004 struct ata_dma_prdentry *prd = args->dmatab; 1005 int i; 1006 1007 if ((args->error = error)) 1008 return; 1009 1010 for (i = 0; i < nsegs; i++) { 1011 prd[i].addr = htole32(segs[i].ds_addr); 1012 prd[i].count = htole32(segs[i].ds_len); 1013 } 1014 if (segs[i - 1].ds_len > MAXLASTSGSIZE) { 1015 //printf("split last SG element of %u\n", segs[i - 1].ds_len); 1016 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE); 1017 prd[i].count = htole32(MAXLASTSGSIZE); 1018 prd[i].addr = htole32(segs[i - 1].ds_addr + 1019 (segs[i - 1].ds_len - MAXLASTSGSIZE)); 1020 nsegs++; 1021 i++; 1022 } 1023 prd[i - 1].count |= htole32(ATA_DMA_EOT); 1024 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 1025 args->nsegs = nsegs; 1026} 1027 1028static int 1029ata_promise_mio_setmode(device_t dev, int target, int mode) 1030{ 1031 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1032 struct ata_channel *ch = device_get_softc(dev); 1033 1034 if ( (ctlr->chip->cfg2 == PR_SATA) || 1035 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1036 (ctlr->chip->cfg2 == PR_SATA2) || 1037 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1038 mode = ata_sata_setmode(dev, target, mode); 1039 else 1040 mode = ata_promise_setmode(dev, target, mode); 1041 return (mode); 1042} 1043 1044static int 1045ata_promise_mio_getrev(device_t dev, int target) 1046{ 1047 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1048 struct ata_channel *ch = device_get_softc(dev); 1049 1050 if ( (ctlr->chip->cfg2 == PR_SATA) || 1051 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1052 (ctlr->chip->cfg2 == PR_SATA2) || 1053 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1054 return (ata_sata_getrev(dev, target)); 1055 else 1056 return (0); 1057} 1058 1059static void 1060ata_promise_sx4_intr(void *data) 1061{ 1062 struct ata_pci_controller *ctlr = data; 1063 struct ata_channel *ch; 1064 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 1065 int unit; 1066 1067 for (unit = 0; unit < ctlr->channels; unit++) { 1068 if (vector & (1 << (unit + 1))) 1069 if ((ch = ctlr->interrupt[unit].argument)) 1070 ctlr->interrupt[unit].function(ch); 1071 if (vector & (1 << (unit + 5))) 1072 if ((ch = ctlr->interrupt[unit].argument)) 1073 ata_promise_queue_hpkt(ctlr, 1074 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1075 ATA_PDC_HPKT_OFFSET)); 1076 if (vector & (1 << (unit + 9))) { 1077 ata_promise_next_hpkt(ctlr); 1078 if ((ch = ctlr->interrupt[unit].argument)) 1079 ctlr->interrupt[unit].function(ch); 1080 } 1081 if (vector & (1 << (unit + 13))) { 1082 ata_promise_next_hpkt(ctlr); 1083 if ((ch = ctlr->interrupt[unit].argument)) 1084 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1085 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1086 ATA_PDC_APKT_OFFSET)); 1087 } 1088 } 1089} 1090 1091static int 1092ata_promise_sx4_command(struct ata_request *request) 1093{ 1094 device_t gparent = device_get_parent(request->parent); 1095 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1096 struct ata_channel *ch = device_get_softc(request->parent); 1097 struct ata_dma_prdentry *prd; 1098 caddr_t window = rman_get_virtual(ctlr->r_res1); 1099 u_int32_t *wordp; 1100 int i, idx, length = 0; 1101 1102 /* XXX SOS add ATAPI commands support later */ 1103 switch (request->u.ata.command) { 1104 1105 default: 1106 return -1; 1107 1108 case ATA_ATA_IDENTIFY: 1109 case ATA_READ: 1110 case ATA_READ48: 1111 case ATA_READ_MUL: 1112 case ATA_READ_MUL48: 1113 case ATA_WRITE: 1114 case ATA_WRITE48: 1115 case ATA_WRITE_MUL: 1116 case ATA_WRITE_MUL48: 1117 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1118 return ata_generic_command(request); 1119 1120 case ATA_SETFEATURES: 1121 case ATA_FLUSHCACHE: 1122 case ATA_FLUSHCACHE48: 1123 case ATA_SLEEP: 1124 case ATA_SET_MULTI: 1125 wordp = (u_int32_t *) 1126 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1127 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 1128 wordp[1] = 0; 1129 wordp[2] = 0; 1130 ata_promise_apkt((u_int8_t *)wordp, request); 1131 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1132 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1133 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1134 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 1135 return 0; 1136 1137 case ATA_READ_DMA: 1138 case ATA_READ_DMA48: 1139 case ATA_WRITE_DMA: 1140 case ATA_WRITE_DMA48: 1141 prd = request->dma->sg; 1142 wordp = (u_int32_t *) 1143 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 1144 i = idx = 0; 1145 do { 1146 wordp[idx++] = prd[i].addr; 1147 wordp[idx++] = prd[i].count; 1148 length += (prd[i].count & ~ATA_DMA_EOT); 1149 } while (!(prd[i++].count & ATA_DMA_EOT)); 1150 1151 wordp = (u_int32_t *) 1152 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 1153 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1154 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1155 1156 wordp = (u_int32_t *) 1157 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 1158 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1159 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1160 1161 wordp = (u_int32_t *) 1162 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 1163 if (request->flags & ATA_R_READ) 1164 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 1165 if (request->flags & ATA_R_WRITE) 1166 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 1167 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 1168 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 1169 wordp[3] = 0; 1170 1171 wordp = (u_int32_t *) 1172 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1173 if (request->flags & ATA_R_READ) 1174 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 1175 if (request->flags & ATA_R_WRITE) 1176 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 1177 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 1178 wordp[2] = 0; 1179 ata_promise_apkt((u_int8_t *)wordp, request); 1180 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1181 1182 if (request->flags & ATA_R_READ) { 1183 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 1184 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 1185 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1186 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 1187 } 1188 if (request->flags & ATA_R_WRITE) { 1189 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 1190 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 1191 ata_promise_queue_hpkt(ctlr, 1192 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 1193 } 1194 return 0; 1195 } 1196} 1197 1198static int 1199ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 1200{ 1201 int i = 12; 1202 1203 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 1204 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit); 1205 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 1206 bytep[i++] = ATA_A_4BIT; 1207 1208 if (request->flags & ATA_R_48BIT) { 1209 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1210 bytep[i++] = request->u.ata.feature >> 8; 1211 bytep[i++] = request->u.ata.feature; 1212 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 1213 bytep[i++] = request->u.ata.count >> 8; 1214 bytep[i++] = request->u.ata.count; 1215 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1216 bytep[i++] = request->u.ata.lba >> 24; 1217 bytep[i++] = request->u.ata.lba; 1218 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1219 bytep[i++] = request->u.ata.lba >> 32; 1220 bytep[i++] = request->u.ata.lba >> 8; 1221 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1222 bytep[i++] = request->u.ata.lba >> 40; 1223 bytep[i++] = request->u.ata.lba >> 16; 1224 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1225 bytep[i++] = ATA_D_LBA | ATA_DEV(request->unit); 1226 } 1227 else { 1228 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1229 bytep[i++] = request->u.ata.feature; 1230 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 1231 bytep[i++] = request->u.ata.count; 1232 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1233 bytep[i++] = request->u.ata.lba; 1234 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1235 bytep[i++] = request->u.ata.lba >> 8; 1236 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1237 bytep[i++] = request->u.ata.lba >> 16; 1238 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1239 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ATA_DEV(request->unit) | 1240 ((request->u.ata.lba >> 24)&0xf); 1241 } 1242 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 1243 bytep[i++] = request->u.ata.command; 1244 return i; 1245} 1246 1247static void 1248ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 1249{ 1250 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1251 1252 mtx_lock(&hpktp->mtx); 1253 if (hpktp->busy) { 1254 struct host_packet *hp = 1255 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 1256 hp->addr = hpkt; 1257 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 1258 } 1259 else { 1260 hpktp->busy = 1; 1261 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 1262 } 1263 mtx_unlock(&hpktp->mtx); 1264} 1265 1266static void 1267ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 1268{ 1269 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1270 struct host_packet *hp; 1271 1272 mtx_lock(&hpktp->mtx); 1273 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 1274 TAILQ_REMOVE(&hpktp->queue, hp, chain); 1275 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 1276 free(hp, M_TEMP); 1277 } 1278 else 1279 hpktp->busy = 0; 1280 mtx_unlock(&hpktp->mtx); 1281} 1282 1283ATA_DECLARE_DRIVER(ata_promise); 1284