1183724Ssos/*- 2183724Ssos * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3183724Ssos * All rights reserved. 4183724Ssos * 5183724Ssos * Redistribution and use in source and binary forms, with or without 6183724Ssos * modification, are permitted provided that the following conditions 7183724Ssos * are met: 8183724Ssos * 1. Redistributions of source code must retain the above copyright 9183724Ssos * notice, this list of conditions and the following disclaimer, 10183724Ssos * without modification, immediately at the beginning of the file. 11183724Ssos * 2. Redistributions in binary form must reproduce the above copyright 12183724Ssos * notice, this list of conditions and the following disclaimer in the 13183724Ssos * documentation and/or other materials provided with the distribution. 14183724Ssos * 15183724Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183724Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17183724Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18183724Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19183724Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20183724Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21183724Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22183724Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23183724Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24183724Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25183724Ssos */ 26183724Ssos 27183724Ssos#include <sys/cdefs.h> 28183724Ssos__FBSDID("$FreeBSD$"); 29183724Ssos 30183724Ssos#include "opt_ata.h" 31183724Ssos#include <sys/param.h> 32183724Ssos#include <sys/module.h> 33183724Ssos#include <sys/systm.h> 34183724Ssos#include <sys/kernel.h> 35183724Ssos#include <sys/ata.h> 36183724Ssos#include <sys/bus.h> 37183724Ssos#include <sys/endian.h> 38183724Ssos#include <sys/malloc.h> 39183724Ssos#include <sys/lock.h> 40183724Ssos#include <sys/mutex.h> 41183724Ssos#include <sys/sema.h> 42183724Ssos#include <sys/taskqueue.h> 43183724Ssos#include <vm/uma.h> 44183724Ssos#include <machine/stdarg.h> 45183724Ssos#include <machine/resource.h> 46183724Ssos#include <machine/bus.h> 47183724Ssos#include <sys/rman.h> 48183724Ssos#include <dev/pci/pcivar.h> 49183724Ssos#include <dev/pci/pcireg.h> 50183724Ssos#include <dev/ata/ata-all.h> 51183724Ssos#include <dev/ata/ata-pci.h> 52183724Ssos#include <ata_if.h> 53183724Ssos 54183724Ssos/* local prototypes */ 55183724Ssosstatic int ata_ati_chipinit(device_t dev); 56229291Smavstatic int ata_ati_dumb_ch_attach(device_t dev); 57201993Smavstatic int ata_ati_ixp700_ch_attach(device_t dev); 58200171Smavstatic int ata_ati_setmode(device_t dev, int target, int mode); 59183724Ssos 60183724Ssos/* misc defines */ 61233717Smarius#define SII_MEMIO 1 /* must match ata_siliconimage.c's definition */ 62233717Smarius#define SII_BUG 0x04 /* must match ata_siliconimage.c's definition */ 63233717Smarius 64233717Smarius#define ATI_SATA SII_MEMIO 65233717Smarius#define ATI_PATA 0x02 66183724Ssos#define ATI_AHCI 0x04 67183724Ssos 68229291Smavstatic int force_ahci = 1; 69229291SmavTUNABLE_INT("hw.ahci.force", &force_ahci); 70183724Ssos 71183724Ssos/* 72183724Ssos * ATI chipset support functions 73183724Ssos */ 74183724Ssosstatic int 75183724Ssosata_ati_probe(device_t dev) 76183724Ssos{ 77183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 78242908Sdim static const struct ata_chip_id ids[] = 79183724Ssos {{ ATA_ATI_IXP200, 0x00, ATI_PATA, 0, ATA_UDMA5, "IXP200" }, 80183724Ssos { ATA_ATI_IXP300, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP300" }, 81233717Smarius { ATA_ATI_IXP300_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP300" }, 82183724Ssos { ATA_ATI_IXP400, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP400" }, 83233717Smarius { ATA_ATI_IXP400_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" }, 84233717Smarius { ATA_ATI_IXP400_S2, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" }, 85183724Ssos { ATA_ATI_IXP600, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP600" }, 86183724Ssos { ATA_ATI_IXP600_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP600" }, 87191568Sjkim { ATA_ATI_IXP700, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP700/800" }, 88191568Sjkim { ATA_ATI_IXP700_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 89191568Sjkim { ATA_ATI_IXP700_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 90191568Sjkim { ATA_ATI_IXP700_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 91191568Sjkim { ATA_ATI_IXP700_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 92191568Sjkim { ATA_ATI_IXP800_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" }, 93191568Sjkim { ATA_ATI_IXP800_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" }, 94245797Smav { ATA_AMD_HUDSON2, 0x00, ATI_PATA, 0, ATA_UDMA6, "Hudson-2" }, 95245797Smav { ATA_AMD_HUDSON2_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 96245797Smav { ATA_AMD_HUDSON2_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 97245797Smav { ATA_AMD_HUDSON2_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 98245797Smav { ATA_AMD_HUDSON2_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 99245797Smav { ATA_AMD_HUDSON2_S5, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 100183724Ssos { 0, 0, 0, 0, 0, 0}}; 101183724Ssos 102183724Ssos if (pci_get_vendor(dev) != ATA_ATI_ID) 103183724Ssos return ENXIO; 104183724Ssos 105183724Ssos if (!(ctlr->chip = ata_match_chip(dev, ids))) 106183724Ssos return ENXIO; 107183724Ssos 108183724Ssos ata_set_desc(dev); 109183724Ssos 110183724Ssos switch (ctlr->chip->cfg1) { 111183724Ssos case ATI_PATA: 112183724Ssos ctlr->chipinit = ata_ati_chipinit; 113183724Ssos break; 114183724Ssos case ATI_SATA: 115183724Ssos /* 116183724Ssos * the ATI SATA controller is actually a SiI 3112 controller 117183724Ssos */ 118183724Ssos ctlr->chipinit = ata_sii_chipinit; 119183724Ssos break; 120183724Ssos case ATI_AHCI: 121229291Smav if (force_ahci == 1 || pci_get_subclass(dev) != PCIS_STORAGE_IDE) 122229291Smav ctlr->chipinit = ata_ahci_chipinit; 123229291Smav else 124229291Smav ctlr->chipinit = ata_ati_chipinit; 125183724Ssos break; 126183724Ssos } 127194893Smav return (BUS_PROBE_DEFAULT); 128183724Ssos} 129183724Ssos 130183724Ssosstatic int 131183724Ssosata_ati_chipinit(device_t dev) 132183724Ssos{ 133183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 134197783Sjkim device_t smbdev; 135201993Smav uint8_t satacfg; 136183724Ssos 137183724Ssos if (ata_setup_interrupt(dev, ata_generic_intr)) 138183724Ssos return ENXIO; 139183724Ssos 140229291Smav if (ctlr->chip->cfg1 == ATI_AHCI) { 141229291Smav ctlr->ch_attach = ata_ati_dumb_ch_attach; 142229291Smav ctlr->setmode = ata_sata_setmode; 143229291Smav return (0); 144229291Smav } 145197783Sjkim switch (ctlr->chip->chipid) { 146197783Sjkim case ATA_ATI_IXP600: 147197783Sjkim /* IXP600 only has 1 PATA channel */ 148183724Ssos ctlr->channels = 1; 149197783Sjkim break; 150197783Sjkim case ATA_ATI_IXP700: 151197783Sjkim /* 152197783Sjkim * When "combined mode" is enabled, an additional PATA channel is 153197783Sjkim * emulated with two SATA ports and appears on this device. 154197783Sjkim * This mode can only be detected via SMB controller. 155197783Sjkim */ 156197783Sjkim smbdev = pci_find_device(ATA_ATI_ID, 0x4385); 157197783Sjkim if (smbdev != NULL) { 158197783Sjkim satacfg = pci_read_config(smbdev, 0xad, 1); 159197783Sjkim if (bootverbose) 160197783Sjkim device_printf(dev, "SATA controller %s (%s%s channel)\n", 161197783Sjkim (satacfg & 0x01) == 0 ? "disabled" : "enabled", 162197783Sjkim (satacfg & 0x08) == 0 ? "" : "combined mode, ", 163197783Sjkim (satacfg & 0x10) == 0 ? "primary" : "secondary"); 164201993Smav ctlr->chipset_data = (void *)(uintptr_t)satacfg; 165197783Sjkim /* 166197783Sjkim * If SATA controller is enabled but combined mode is disabled, 167197783Sjkim * we have only one PATA channel. Ignore a non-existent channel. 168197783Sjkim */ 169197783Sjkim if ((satacfg & 0x09) == 0x01) 170197783Sjkim ctlr->ichannels &= ~(1 << ((satacfg & 0x10) >> 4)); 171201993Smav else { 172201993Smav ctlr->ch_attach = ata_ati_ixp700_ch_attach; 173201993Smav } 174197783Sjkim } 175197783Sjkim break; 176197783Sjkim } 177197783Sjkim 178183724Ssos ctlr->setmode = ata_ati_setmode; 179183724Ssos return 0; 180183724Ssos} 181183724Ssos 182200171Smavstatic int 183229291Smavata_ati_dumb_ch_attach(device_t dev) 184229291Smav{ 185229291Smav struct ata_channel *ch = device_get_softc(dev); 186229291Smav 187229291Smav if (ata_pci_ch_attach(dev)) 188229291Smav return ENXIO; 189229291Smav ch->flags |= ATA_SATA; 190229291Smav return (0); 191229291Smav} 192229291Smav 193229291Smavstatic int 194201993Smavata_ati_ixp700_ch_attach(device_t dev) 195201993Smav{ 196201993Smav struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 197201993Smav struct ata_channel *ch = device_get_softc(dev); 198201993Smav uint8_t satacfg = (uint8_t)(uintptr_t)ctlr->chipset_data; 199201993Smav 200201993Smav /* Setup the usual register normal pci style. */ 201201993Smav if (ata_pci_ch_attach(dev)) 202201993Smav return ENXIO; 203201993Smav 204201993Smav /* One of channels is PATA, another is SATA. */ 205201993Smav if (ch->unit == ((satacfg & 0x10) >> 4)) 206201993Smav ch->flags |= ATA_SATA; 207201993Smav return (0); 208201993Smav} 209201993Smav 210201993Smavstatic int 211200171Smavata_ati_setmode(device_t dev, int target, int mode) 212183724Ssos{ 213200171Smav device_t parent = device_get_parent(dev); 214200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 215200171Smav struct ata_channel *ch = device_get_softc(dev); 216200171Smav int devno = (ch->unit << 1) + target; 217200171Smav int offset = (devno ^ 0x01) << 3; 218200171Smav int piomode; 219233717Smarius static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 220233717Smarius static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 221183724Ssos 222200171Smav mode = min(mode, ctlr->chip->max_dma); 223183724Ssos if (mode >= ATA_UDMA0) { 224200171Smav /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */ 225200171Smav pci_write_config(parent, 0x56, 226200171Smav (pci_read_config(parent, 0x56, 2) & 227183724Ssos ~(0xf << (devno << 2))) | 228183724Ssos ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 229200171Smav pci_write_config(parent, 0x54, 230200171Smav pci_read_config(parent, 0x54, 1) | 231183724Ssos (0x01 << devno), 1); 232200171Smav pci_write_config(parent, 0x44, 233200171Smav (pci_read_config(parent, 0x44, 4) & 234183724Ssos ~(0xff << offset)) | 235183724Ssos (dmatimings[2] << offset), 4); 236200171Smav piomode = ATA_PIO4; 237200171Smav } else if (mode >= ATA_WDMA0) { 238200171Smav /* Disable UDMA, set WDMA mode and timings, calculate PIO. */ 239200171Smav pci_write_config(parent, 0x54, 240200171Smav pci_read_config(parent, 0x54, 1) & 241183724Ssos ~(0x01 << devno), 1); 242200171Smav pci_write_config(parent, 0x44, 243200171Smav (pci_read_config(parent, 0x44, 4) & 244183724Ssos ~(0xff << offset)) | 245183724Ssos (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 246200171Smav piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 247200171Smav (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 248200171Smav } else { 249200171Smav /* Disable UDMA, set requested PIO. */ 250200171Smav pci_write_config(parent, 0x54, 251200171Smav pci_read_config(parent, 0x54, 1) & 252200171Smav ~(0x01 << devno), 1); 253200171Smav piomode = mode; 254183724Ssos } 255200171Smav /* Set PIO mode and timings, calculated above. */ 256200171Smav pci_write_config(parent, 0x4a, 257200171Smav (pci_read_config(parent, 0x4a, 2) & 258183724Ssos ~(0xf << (devno << 2))) | 259200171Smav ((piomode - ATA_PIO0) << (devno<<2)),2); 260200171Smav pci_write_config(parent, 0x40, 261200171Smav (pci_read_config(parent, 0x40, 4) & 262183724Ssos ~(0xff << offset)) | 263200171Smav (piotimings[ata_mode2idx(piomode)] << offset), 4); 264200171Smav return (mode); 265183724Ssos} 266183724Ssos 267183724SsosATA_DECLARE_DRIVER(ata_ati); 268183724SsosMODULE_DEPEND(ata_ati, ata_ahci, 1, 1, 1); 269183724SsosMODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1); 270