1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer,
10 *    without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD$");
29
30#include "opt_ata.h"
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/ata.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/malloc.h>
39#include <sys/lock.h>
40#include <sys/mutex.h>
41#include <sys/sema.h>
42#include <sys/taskqueue.h>
43#include <vm/uma.h>
44#include <machine/stdarg.h>
45#include <machine/resource.h>
46#include <machine/bus.h>
47#include <sys/rman.h>
48#include <dev/pci/pcivar.h>
49#include <dev/pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_ali_chipinit(device_t dev);
56static int ata_ali_chipdeinit(device_t dev);
57static int ata_ali_ch_attach(device_t dev);
58static int ata_ali_sata_ch_attach(device_t dev);
59static void ata_ali_reset(device_t dev);
60static int ata_ali_setmode(device_t dev, int target, int mode);
61
62/* misc defines */
63#define ALI_OLD		0x01
64#define ALI_NEW		0x02
65#define ALI_SATA	0x04
66
67struct ali_sata_resources {
68	struct resource *bars[4];
69};
70
71/*
72 * Acer Labs Inc (ALI) chipset support functions
73 */
74static int
75ata_ali_probe(device_t dev)
76{
77    struct ata_pci_controller *ctlr = device_get_softc(dev);
78    static const struct ata_chip_id ids[] =
79    {{ ATA_ALI_5289, 0x00, 2, ALI_SATA, ATA_SA150, "M5289" },
80     { ATA_ALI_5288, 0x00, 4, ALI_SATA, ATA_SA300, "M5288" },
81     { ATA_ALI_5287, 0x00, 4, ALI_SATA, ATA_SA150, "M5287" },
82     { ATA_ALI_5281, 0x00, 2, ALI_SATA, ATA_SA150, "M5281" },
83     { ATA_ALI_5228, 0xc5, 0, ALI_NEW,  ATA_UDMA6, "M5228" },
84     { ATA_ALI_5229, 0xc5, 0, ALI_NEW,  ATA_UDMA6, "M5229" },
85     { ATA_ALI_5229, 0xc4, 0, ALI_NEW,  ATA_UDMA5, "M5229" },
86     { ATA_ALI_5229, 0xc2, 0, ALI_NEW,  ATA_UDMA4, "M5229" },
87     { ATA_ALI_5229, 0x20, 0, ALI_OLD,  ATA_UDMA2, "M5229" },
88     { ATA_ALI_5229, 0x00, 0, ALI_OLD,  ATA_WDMA2, "M5229" },
89     { 0, 0, 0, 0, 0, 0}};
90
91    if (pci_get_vendor(dev) != ATA_ACER_LABS_ID)
92	return ENXIO;
93
94    if (!(ctlr->chip = ata_match_chip(dev, ids)))
95	return ENXIO;
96
97    ata_set_desc(dev);
98    ctlr->chipinit = ata_ali_chipinit;
99    ctlr->chipdeinit = ata_ali_chipdeinit;
100    return (BUS_PROBE_DEFAULT);
101}
102
103static int
104ata_ali_chipinit(device_t dev)
105{
106    struct ata_pci_controller *ctlr = device_get_softc(dev);
107    struct ali_sata_resources *res;
108    int i, rid;
109
110    if (ata_setup_interrupt(dev, ata_generic_intr))
111	return ENXIO;
112
113    switch (ctlr->chip->cfg2) {
114    case ALI_SATA:
115	ctlr->channels = ctlr->chip->cfg1;
116	ctlr->ch_attach = ata_ali_sata_ch_attach;
117	ctlr->ch_detach = ata_pci_ch_detach;
118	ctlr->setmode = ata_sata_setmode;
119	ctlr->getrev = ata_sata_getrev;
120
121	/* AHCI mode is correctly supported only on the ALi 5288. */
122	if ((ctlr->chip->chipid == ATA_ALI_5288) &&
123	    (ata_ahci_chipinit(dev) != ENXIO))
124            return 0;
125
126	/* Allocate resources for later use by channel attach routines. */
127	res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK);
128	for (i = 0; i < 4; i++) {
129		rid = PCIR_BAR(i);
130		res->bars[i] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
131		    RF_ACTIVE);
132		if (res->bars[i] == NULL) {
133			device_printf(dev, "Failed to allocate BAR %d\n", i);
134			for (i--; i >=0; i--)
135				bus_release_resource(dev, SYS_RES_IOPORT,
136				    PCIR_BAR(i), res->bars[i]);
137			free(res, M_ATAPCI);
138			return ENXIO;
139		}
140	}
141	ctlr->chipset_data = res;
142	break;
143
144    case ALI_NEW:
145	/* use device interrupt as byte count end */
146	pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
147
148	/* enable cable detection and UDMA support on revisions < 0xc7 */
149	if (ctlr->chip->chiprev < 0xc7)
150	    pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) |
151		0x09, 1);
152
153	/* enable ATAPI UDMA mode (even if we are going to do PIO) */
154	pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) |
155	    (ctlr->chip->chiprev >= 0xc7 ? 0x03 : 0x01), 1);
156
157	/* only chips with revision > 0xc4 can do 48bit DMA */
158	if (ctlr->chip->chiprev <= 0xc4)
159	    device_printf(dev,
160			  "using PIO transfers above 137GB as workaround for "
161			  "48bit DMA access bug, expect reduced performance\n");
162	ctlr->ch_attach = ata_ali_ch_attach;
163	ctlr->ch_detach = ata_pci_ch_detach;
164	ctlr->reset = ata_ali_reset;
165	ctlr->setmode = ata_ali_setmode;
166	break;
167
168    case ALI_OLD:
169	/* deactivate the ATAPI FIFO and enable ATAPI UDMA */
170	pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
171	ctlr->setmode = ata_ali_setmode;
172	break;
173    }
174    return 0;
175}
176
177static int
178ata_ali_chipdeinit(device_t dev)
179{
180	struct ata_pci_controller *ctlr = device_get_softc(dev);
181	struct ali_sata_resources *res;
182	int i;
183
184	if (ctlr->chip->cfg2 == ALI_SATA) {
185		res = ctlr->chipset_data;
186		for (i = 0; i < 4; i++) {
187			if (res->bars[i] != NULL) {
188				bus_release_resource(dev, SYS_RES_IOPORT,
189				    PCIR_BAR(i), res->bars[i]);
190			}
191		}
192		free(res, M_ATAPCI);
193		ctlr->chipset_data = NULL;
194	}
195	return (0);
196}
197
198static int
199ata_ali_ch_attach(device_t dev)
200{
201    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
202    struct ata_channel *ch = device_get_softc(dev);
203
204    /* setup the usual register normal pci style */
205    if (ata_pci_ch_attach(dev))
206	return ENXIO;
207
208    if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7)
209	ch->flags |= ATA_CHECKS_CABLE;
210    /* older chips can't do 48bit DMA transfers */
211    if (ctlr->chip->chiprev <= 0xc4) {
212	ch->flags |= ATA_NO_48BIT_DMA;
213	if (ch->dma.max_iosize > 256 * 512)
214		ch->dma.max_iosize = 256 * 512;
215    }
216#ifdef ATA_CAM
217	if (ctlr->chip->cfg2 & ALI_NEW)
218		ch->flags |= ATA_NO_ATAPI_DMA;
219#endif
220
221    return 0;
222}
223
224static int
225ata_ali_sata_ch_attach(device_t dev)
226{
227    device_t parent = device_get_parent(dev);
228    struct ata_pci_controller *ctlr = device_get_softc(parent);
229    struct ata_channel *ch = device_get_softc(dev);
230    struct ali_sata_resources *res;
231    struct resource *io = NULL, *ctlio = NULL;
232    int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
233    int i;
234
235    res = ctlr->chipset_data;
236    if (unit01) {
237	    io = res->bars[2];
238	    ctlio = res->bars[3];
239    } else {
240	    io = res->bars[0];
241	    ctlio = res->bars[1];
242    }
243    ata_pci_dmainit(dev);
244    for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
245	ch->r_io[i].res = io;
246	ch->r_io[i].offset = i + (unit10 ? 8 : 0);
247    }
248    ch->r_io[ATA_CONTROL].res = ctlio;
249    ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
250    ch->r_io[ATA_IDX_ADDR].res = io;
251    ata_default_registers(dev);
252    if (ctlr->r_res1) {
253	for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
254	    ch->r_io[i].res = ctlr->r_res1;
255	    ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
256	}
257    }
258    ch->flags |= ATA_NO_SLAVE;
259    ch->flags |= ATA_SATA;
260
261    /* XXX SOS PHY handling awkward in ALI chip not supported yet */
262    ata_pci_hw(dev);
263    return 0;
264}
265
266static void
267ata_ali_reset(device_t dev)
268{
269    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
270    struct ata_channel *ch = device_get_softc(dev);
271    device_t *children;
272    int nchildren, i;
273
274    ata_generic_reset(dev);
275
276    /*
277     * workaround for datacorruption bug found on at least SUN Blade-100
278     * find the ISA function on the southbridge and disable then enable
279     * the ATA channel tristate buffer
280     */
281    if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
282	if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
283	    for (i = 0; i < nchildren; i++) {
284		if (pci_get_devid(children[i]) == ATA_ALI_1533) {
285		    pci_write_config(children[i], 0x58,
286				     pci_read_config(children[i], 0x58, 1) &
287				     ~(0x04 << ch->unit), 1);
288		    pci_write_config(children[i], 0x58,
289				     pci_read_config(children[i], 0x58, 1) |
290				     (0x04 << ch->unit), 1);
291		    break;
292		}
293	    }
294	    free(children, M_TEMP);
295	}
296    }
297}
298
299static int
300ata_ali_setmode(device_t dev, int target, int mode)
301{
302	device_t parent = device_get_parent(dev);
303	struct ata_pci_controller *ctlr = device_get_softc(parent);
304	struct ata_channel *ch = device_get_softc(dev);
305	int devno = (ch->unit << 1) + target;
306	int piomode;
307	static const uint32_t piotimings[] =
308		{ 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
309		  0x00310001, 0x006d0003, 0x00330001, 0x00310001 };
310	static const uint8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f,
311	    0x0d};
312	uint32_t word54;
313
314        mode = min(mode, ctlr->chip->max_dma);
315
316	if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) {
317		if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
318		    pci_read_config(parent, 0x4a, 1) & (1 << ch->unit)) {
319			ata_print_cable(dev, "controller");
320			mode = ATA_UDMA2;
321		}
322	}
323	if (ctlr->chip->cfg2 & ALI_OLD) {
324		/* doesn't support ATAPI DMA on write */
325		ch->flags |= ATA_ATAPI_DMA_RO;
326		if (ch->devices & ATA_ATAPI_MASTER &&
327		    ch->devices & ATA_ATAPI_SLAVE) {
328		        /* doesn't support ATAPI DMA on two ATAPI devices */
329		        device_printf(dev, "two atapi devices on this channel,"
330			    " no DMA\n");
331		        mode = min(mode, ATA_PIO_MAX);
332		}
333	}
334	/* Set UDMA mode */
335	word54 = pci_read_config(parent, 0x54, 4);
336	if (mode >= ATA_UDMA0) {
337	    word54 &= ~(0x000f000f << (devno << 2));
338	    word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
339	    piomode = ATA_PIO4;
340	}
341	else {
342	    word54 &= ~(0x0008000f << (devno << 2));
343	    piomode = mode;
344	}
345	pci_write_config(parent, 0x54, word54, 4);
346	/* Set PIO/WDMA mode */
347	pci_write_config(parent, 0x58 + (ch->unit << 2),
348	    piotimings[ata_mode2idx(piomode)], 4);
349	return (mode);
350}
351
352ATA_DECLARE_DRIVER(ata_ali);
353MODULE_DEPEND(ata_ali, ata_ahci, 1, 1, 1);
354