1152909Sanholt/* savage_drv.h -- Private header for the savage driver */ 2152909Sanholt/*- 3145132Sanholt * Copyright 2004 Felix Kuehling 4145132Sanholt * All Rights Reserved. 5145132Sanholt * 6145132Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 7145132Sanholt * copy of this software and associated documentation files (the "Software"), 8145132Sanholt * to deal in the Software without restriction, including without limitation 9145132Sanholt * the rights to use, copy, modify, merge, publish, distribute, sub license, 10145132Sanholt * and/or sell copies of the Software, and to permit persons to whom the 11145132Sanholt * Software is furnished to do so, subject to the following conditions: 12145132Sanholt * 13145132Sanholt * The above copyright notice and this permission notice (including the 14145132Sanholt * next paragraph) shall be included in all copies or substantial portions 15145132Sanholt * of the Software. 16145132Sanholt * 17145132Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18145132Sanholt * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19145132Sanholt * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20145132Sanholt * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 21145132Sanholt * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 22145132Sanholt * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23145132Sanholt * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24145132Sanholt */ 25145132Sanholt 26152909Sanholt#include <sys/cdefs.h> 27152909Sanholt__FBSDID("$FreeBSD$"); 28152909Sanholt 29145132Sanholt#ifndef __SAVAGE_DRV_H__ 30145132Sanholt#define __SAVAGE_DRV_H__ 31145132Sanholt 32145132Sanholt#define DRIVER_AUTHOR "Felix Kuehling" 33145132Sanholt 34145132Sanholt#define DRIVER_NAME "savage" 35145132Sanholt#define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]" 36145132Sanholt#define DRIVER_DATE "20050313" 37145132Sanholt 38145132Sanholt#define DRIVER_MAJOR 2 39145132Sanholt#define DRIVER_MINOR 4 40145132Sanholt#define DRIVER_PATCHLEVEL 1 41145132Sanholt/* Interface history: 42145132Sanholt * 43145132Sanholt * 1.x The DRM driver from the VIA/S3 code drop, basically a dummy 44145132Sanholt * 2.0 The first real DRM 45145132Sanholt * 2.1 Scissors registers managed by the DRM, 3D operations clipped by 46145132Sanholt * cliprects of the cmdbuf ioctl 47145132Sanholt * 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX 48145132Sanholt * 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits 49145132Sanholt * wide and thus very long lived (unlikely to ever wrap). The size 50145132Sanholt * in the struct was 32 bits before, but only 16 bits were used 51145132Sanholt * 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is 52145132Sanholt * actually used 53145132Sanholt */ 54145132Sanholt 55145132Sanholttypedef struct drm_savage_age { 56145132Sanholt uint16_t event; 57145132Sanholt unsigned int wrap; 58145132Sanholt} drm_savage_age_t; 59145132Sanholt 60145132Sanholttypedef struct drm_savage_buf_priv { 61145132Sanholt struct drm_savage_buf_priv *next; 62145132Sanholt struct drm_savage_buf_priv *prev; 63145132Sanholt drm_savage_age_t age; 64182080Srnoland struct drm_buf *buf; 65145132Sanholt} drm_savage_buf_priv_t; 66145132Sanholt 67145132Sanholttypedef struct drm_savage_dma_page { 68145132Sanholt drm_savage_age_t age; 69145132Sanholt unsigned int used, flushed; 70145132Sanholt} drm_savage_dma_page_t; 71145132Sanholt#define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */ 72145132Sanholt/* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command 73145132Sanholt * size of 16kbytes or 4k entries. Minimum requirement would be 74145132Sanholt * 10kbytes for 255 40-byte vertices in one drawing command. */ 75145132Sanholt#define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4) 76145132Sanholt 77145132Sanholt/* interesting bits of hardware state that are saved in dev_priv */ 78145132Sanholttypedef union { 79145132Sanholt struct drm_savage_common_state { 80145132Sanholt uint32_t vbaddr; 81145132Sanholt } common; 82145132Sanholt struct { 83145132Sanholt unsigned char pad[sizeof(struct drm_savage_common_state)]; 84145132Sanholt uint32_t texctrl, texaddr; 85145132Sanholt uint32_t scstart, new_scstart; 86145132Sanholt uint32_t scend, new_scend; 87145132Sanholt } s3d; 88145132Sanholt struct { 89145132Sanholt unsigned char pad[sizeof(struct drm_savage_common_state)]; 90145132Sanholt uint32_t texdescr, texaddr0, texaddr1; 91145132Sanholt uint32_t drawctrl0, new_drawctrl0; 92145132Sanholt uint32_t drawctrl1, new_drawctrl1; 93145132Sanholt } s4; 94145132Sanholt} drm_savage_state_t; 95145132Sanholt 96145132Sanholt/* these chip tags should match the ones in the 2D driver in savage_regs.h. */ 97145132Sanholtenum savage_family { 98145132Sanholt S3_UNKNOWN = 0, 99145132Sanholt S3_SAVAGE3D, 100145132Sanholt S3_SAVAGE_MX, 101145132Sanholt S3_SAVAGE4, 102145132Sanholt S3_PROSAVAGE, 103145132Sanholt S3_TWISTER, 104145132Sanholt S3_PROSAVAGEDDR, 105145132Sanholt S3_SUPERSAVAGE, 106145132Sanholt S3_SAVAGE2000, 107145132Sanholt S3_LAST 108145132Sanholt}; 109145132Sanholt 110182080Srnolandextern struct drm_ioctl_desc savage_ioctls[]; 111152909Sanholtextern int savage_max_ioctl; 112152909Sanholt 113145132Sanholt#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) 114145132Sanholt 115145132Sanholt#define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \ 116145132Sanholt || (chip==S3_PROSAVAGE) \ 117145132Sanholt || (chip==S3_TWISTER) \ 118145132Sanholt || (chip==S3_PROSAVAGEDDR)) 119145132Sanholt 120145132Sanholt#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) 121145132Sanholt 122145132Sanholt#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) 123145132Sanholt 124145132Sanholt#define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \ 125145132Sanholt ||(chip==S3_PROSAVAGEDDR)) 126145132Sanholt 127145132Sanholt/* flags */ 128145132Sanholt#define SAVAGE_IS_AGP 1 129145132Sanholt 130145132Sanholttypedef struct drm_savage_private { 131145132Sanholt drm_savage_sarea_t *sarea_priv; 132145132Sanholt 133145132Sanholt drm_savage_buf_priv_t head, tail; 134145132Sanholt 135145132Sanholt /* who am I? */ 136145132Sanholt enum savage_family chipset; 137145132Sanholt 138145132Sanholt unsigned int cob_size; 139145132Sanholt unsigned int bci_threshold_lo, bci_threshold_hi; 140145132Sanholt unsigned int dma_type; 141145132Sanholt 142145132Sanholt /* frame buffer layout */ 143145132Sanholt unsigned int fb_bpp; 144145132Sanholt unsigned int front_offset, front_pitch; 145145132Sanholt unsigned int back_offset, back_pitch; 146145132Sanholt unsigned int depth_bpp; 147145132Sanholt unsigned int depth_offset, depth_pitch; 148145132Sanholt 149145132Sanholt /* bitmap descriptors for swap and clear */ 150145132Sanholt unsigned int front_bd, back_bd, depth_bd; 151145132Sanholt 152145132Sanholt /* local textures */ 153145132Sanholt unsigned int texture_offset; 154145132Sanholt unsigned int texture_size; 155145132Sanholt 156145132Sanholt /* memory regions in physical memory */ 157145132Sanholt drm_local_map_t *sarea; 158145132Sanholt drm_local_map_t *mmio; 159145132Sanholt drm_local_map_t *fb; 160145132Sanholt drm_local_map_t *aperture; 161145132Sanholt drm_local_map_t *status; 162145132Sanholt drm_local_map_t *agp_textures; 163145132Sanholt drm_local_map_t *cmd_dma; 164145132Sanholt drm_local_map_t fake_dma; 165145132Sanholt 166145132Sanholt struct { 167145132Sanholt int handle; 168145132Sanholt unsigned long base, size; 169145132Sanholt } mtrr[3]; 170145132Sanholt 171145132Sanholt /* BCI and status-related stuff */ 172145132Sanholt volatile uint32_t *status_ptr, *bci_ptr; 173145132Sanholt uint32_t status_used_mask; 174145132Sanholt uint16_t event_counter; 175145132Sanholt unsigned int event_wrap; 176145132Sanholt 177145132Sanholt /* Savage4 command DMA */ 178145132Sanholt drm_savage_dma_page_t *dma_pages; 179145132Sanholt unsigned int nr_dma_pages, first_dma_page, current_dma_page; 180145132Sanholt drm_savage_age_t last_dma_age; 181145132Sanholt 182145132Sanholt /* saved hw state for global/local check on S3D */ 183145132Sanholt uint32_t hw_draw_ctrl, hw_zbuf_ctrl; 184145132Sanholt /* and for scissors (global, so don't emit if not changed) */ 185145132Sanholt uint32_t hw_scissors_start, hw_scissors_end; 186145132Sanholt 187145132Sanholt drm_savage_state_t state; 188145132Sanholt 189145132Sanholt /* after emitting a wait cmd Savage3D needs 63 nops before next DMA */ 190145132Sanholt unsigned int waiting; 191145132Sanholt 192145132Sanholt /* config/hardware-dependent function pointers */ 193145132Sanholt int (*wait_fifo)(struct drm_savage_private *dev_priv, unsigned int n); 194145132Sanholt int (*wait_evnt)(struct drm_savage_private *dev_priv, uint16_t e); 195145132Sanholt /* Err, there is a macro wait_event in include/linux/wait.h. 196145132Sanholt * Avoid unwanted macro expansion. */ 197145132Sanholt void (*emit_clip_rect)(struct drm_savage_private *dev_priv, 198182080Srnoland const struct drm_clip_rect *pbox); 199145132Sanholt void (*dma_flush)(struct drm_savage_private *dev_priv); 200145132Sanholt} drm_savage_private_t; 201145132Sanholt 202145132Sanholt/* ioctls */ 203182080Srnolandextern int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv); 204182080Srnolandextern int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 205145132Sanholt 206145132Sanholt/* BCI functions */ 207145132Sanholtextern uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, 208145132Sanholt unsigned int flags); 209182080Srnolandextern void savage_freelist_put(struct drm_device *dev, struct drm_buf *buf); 210145132Sanholtextern void savage_dma_reset(drm_savage_private_t *dev_priv); 211145132Sanholtextern void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page); 212145132Sanholtextern uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, 213145132Sanholt unsigned int n); 214182080Srnolandextern int savage_driver_load(struct drm_device *dev, unsigned long chipset); 215182080Srnolandextern int savage_driver_firstopen(struct drm_device *dev); 216182080Srnolandextern void savage_driver_lastclose(struct drm_device *dev); 217182080Srnolandextern int savage_driver_unload(struct drm_device *dev); 218182080Srnolandextern void savage_reclaim_buffers(struct drm_device *dev, 219182080Srnoland struct drm_file *file_priv); 220145132Sanholt 221145132Sanholt/* state functions */ 222145132Sanholtextern void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv, 223182080Srnoland const struct drm_clip_rect *pbox); 224145132Sanholtextern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, 225182080Srnoland const struct drm_clip_rect *pbox); 226145132Sanholt 227145132Sanholt#define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ 228145132Sanholt#define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ 229145132Sanholt#define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */ 230145132Sanholt#define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ 231145132Sanholt#define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ 232145132Sanholt 233145132Sanholt#define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region 234145132Sanholt * inside the MMIO region */ 235145132Sanholt#define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip 236145132Sanholt * BCI FIFO */ 237145132Sanholt 238145132Sanholt/* 239145132Sanholt * MMIO registers 240145132Sanholt */ 241145132Sanholt#define SAVAGE_STATUS_WORD0 0x48C00 242145132Sanholt#define SAVAGE_STATUS_WORD1 0x48C04 243182080Srnoland#define SAVAGE_ALT_STATUS_WORD0 0x48C60 244145132Sanholt 245145132Sanholt#define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff 246145132Sanholt#define SAVAGE_FIFO_USED_MASK_S4 0x001fffff 247145132Sanholt 248145132Sanholt/* Copied from savage_bci.h in the 2D driver with some renaming. */ 249145132Sanholt 250145132Sanholt/* Bitmap descriptors */ 251145132Sanholt#define SAVAGE_BD_STRIDE_SHIFT 0 252145132Sanholt#define SAVAGE_BD_BPP_SHIFT 16 253145132Sanholt#define SAVAGE_BD_TILE_SHIFT 24 254145132Sanholt#define SAVAGE_BD_BW_DISABLE (1<<28) 255145132Sanholt/* common: */ 256145132Sanholt#define SAVAGE_BD_TILE_LINEAR 0 257145132Sanholt/* savage4, MX, IX, 3D */ 258145132Sanholt#define SAVAGE_BD_TILE_16BPP 2 259145132Sanholt#define SAVAGE_BD_TILE_32BPP 3 260145132Sanholt/* twister, prosavage, DDR, supersavage, 2000 */ 261145132Sanholt#define SAVAGE_BD_TILE_DEST 1 262145132Sanholt#define SAVAGE_BD_TILE_TEXTURE 2 263145132Sanholt/* GBD - BCI enable */ 264145132Sanholt/* savage4, MX, IX, 3D */ 265145132Sanholt#define SAVAGE_GBD_BCI_ENABLE 8 266145132Sanholt/* twister, prosavage, DDR, supersavage, 2000 */ 267145132Sanholt#define SAVAGE_GBD_BCI_ENABLE_TWISTER 0 268145132Sanholt 269145132Sanholt#define SAVAGE_GBD_BIG_ENDIAN 4 270145132Sanholt#define SAVAGE_GBD_LITTLE_ENDIAN 0 271145132Sanholt#define SAVAGE_GBD_64 1 272145132Sanholt 273145132Sanholt/* Global Bitmap Descriptor */ 274145132Sanholt#define SAVAGE_BCI_GLB_BD_LOW 0x8168 275145132Sanholt#define SAVAGE_BCI_GLB_BD_HIGH 0x816C 276145132Sanholt 277145132Sanholt/* 278145132Sanholt * BCI registers 279145132Sanholt */ 280145132Sanholt/* Savage4/Twister/ProSavage 3D registers */ 281145132Sanholt#define SAVAGE_DRAWLOCALCTRL_S4 0x1e 282145132Sanholt#define SAVAGE_TEXPALADDR_S4 0x1f 283145132Sanholt#define SAVAGE_TEXCTRL0_S4 0x20 284145132Sanholt#define SAVAGE_TEXCTRL1_S4 0x21 285145132Sanholt#define SAVAGE_TEXADDR0_S4 0x22 286145132Sanholt#define SAVAGE_TEXADDR1_S4 0x23 287145132Sanholt#define SAVAGE_TEXBLEND0_S4 0x24 288145132Sanholt#define SAVAGE_TEXBLEND1_S4 0x25 289145132Sanholt#define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */ 290145132Sanholt#define SAVAGE_TEXDESCR_S4 0x27 291145132Sanholt#define SAVAGE_FOGTABLE_S4 0x28 292145132Sanholt#define SAVAGE_FOGCTRL_S4 0x30 293145132Sanholt#define SAVAGE_STENCILCTRL_S4 0x31 294145132Sanholt#define SAVAGE_ZBUFCTRL_S4 0x32 295145132Sanholt#define SAVAGE_ZBUFOFF_S4 0x33 296145132Sanholt#define SAVAGE_DESTCTRL_S4 0x34 297145132Sanholt#define SAVAGE_DRAWCTRL0_S4 0x35 298145132Sanholt#define SAVAGE_DRAWCTRL1_S4 0x36 299145132Sanholt#define SAVAGE_ZWATERMARK_S4 0x37 300145132Sanholt#define SAVAGE_DESTTEXRWWATERMARK_S4 0x38 301145132Sanholt#define SAVAGE_TEXBLENDCOLOR_S4 0x39 302145132Sanholt/* Savage3D/MX/IX 3D registers */ 303145132Sanholt#define SAVAGE_TEXPALADDR_S3D 0x18 304145132Sanholt#define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */ 305145132Sanholt#define SAVAGE_TEXADDR_S3D 0x1A 306145132Sanholt#define SAVAGE_TEXDESCR_S3D 0x1B 307145132Sanholt#define SAVAGE_TEXCTRL_S3D 0x1C 308145132Sanholt#define SAVAGE_FOGTABLE_S3D 0x20 309145132Sanholt#define SAVAGE_FOGCTRL_S3D 0x30 310145132Sanholt#define SAVAGE_DRAWCTRL_S3D 0x31 311145132Sanholt#define SAVAGE_ZBUFCTRL_S3D 0x32 312145132Sanholt#define SAVAGE_ZBUFOFF_S3D 0x33 313145132Sanholt#define SAVAGE_DESTCTRL_S3D 0x34 314145132Sanholt#define SAVAGE_SCSTART_S3D 0x35 315145132Sanholt#define SAVAGE_SCEND_S3D 0x36 316182080Srnoland#define SAVAGE_ZWATERMARK_S3D 0x37 317145132Sanholt#define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38 318145132Sanholt/* common stuff */ 319145132Sanholt#define SAVAGE_VERTBUFADDR 0x3e 320145132Sanholt#define SAVAGE_BITPLANEWTMASK 0xd7 321145132Sanholt#define SAVAGE_DMABUFADDR 0x51 322145132Sanholt 323145132Sanholt/* texture enable bits (needed for tex addr checking) */ 324145132Sanholt#define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */ 325145132Sanholt#define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */ 326145132Sanholt#define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */ 327145132Sanholt 328145132Sanholt/* Global fields in Savage4/Twister/ProSavage 3D registers: 329145132Sanholt * 330145132Sanholt * All texture registers and DrawLocalCtrl are local. All other 331145132Sanholt * registers are global. */ 332145132Sanholt 333145132Sanholt/* Global fields in Savage3D/MX/IX 3D registers: 334145132Sanholt * 335145132Sanholt * All texture registers are local. DrawCtrl and ZBufCtrl are 336145132Sanholt * partially local. All other registers are global. 337145132Sanholt * 338145132Sanholt * DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal 339145132Sanholt * ZBufCtrl global fields: zCmpFunc, zBufEn 340145132Sanholt */ 341145132Sanholt#define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c 342145132Sanholt#define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027 343145132Sanholt 344145132Sanholt/* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d) 345145132Sanholt */ 346145132Sanholt#define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff 347145132Sanholt#define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff 348145132Sanholt 349145132Sanholt/* 350145132Sanholt * BCI commands 351145132Sanholt */ 352145132Sanholt#define BCI_CMD_NOP 0x40000000 353145132Sanholt#define BCI_CMD_RECT 0x48000000 354145132Sanholt#define BCI_CMD_RECT_XP 0x01000000 355145132Sanholt#define BCI_CMD_RECT_YP 0x02000000 356145132Sanholt#define BCI_CMD_SCANLINE 0x50000000 357145132Sanholt#define BCI_CMD_LINE 0x5C000000 358145132Sanholt#define BCI_CMD_LINE_LAST_PIXEL 0x58000000 359145132Sanholt#define BCI_CMD_BYTE_TEXT 0x63000000 360145132Sanholt#define BCI_CMD_NT_BYTE_TEXT 0x67000000 361145132Sanholt#define BCI_CMD_BIT_TEXT 0x6C000000 362145132Sanholt#define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) 363145132Sanholt#define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) 364145132Sanholt#define BCI_CMD_SEND_COLOR 0x00008000 365145132Sanholt 366145132Sanholt#define BCI_CMD_CLIP_NONE 0x00000000 367145132Sanholt#define BCI_CMD_CLIP_CURRENT 0x00002000 368145132Sanholt#define BCI_CMD_CLIP_LR 0x00004000 369145132Sanholt#define BCI_CMD_CLIP_NEW 0x00006000 370145132Sanholt 371145132Sanholt#define BCI_CMD_DEST_GBD 0x00000000 372145132Sanholt#define BCI_CMD_DEST_PBD 0x00000800 373145132Sanholt#define BCI_CMD_DEST_PBD_NEW 0x00000C00 374145132Sanholt#define BCI_CMD_DEST_SBD 0x00001000 375145132Sanholt#define BCI_CMD_DEST_SBD_NEW 0x00001400 376145132Sanholt 377145132Sanholt#define BCI_CMD_SRC_TRANSPARENT 0x00000200 378145132Sanholt#define BCI_CMD_SRC_SOLID 0x00000000 379145132Sanholt#define BCI_CMD_SRC_GBD 0x00000020 380145132Sanholt#define BCI_CMD_SRC_COLOR 0x00000040 381145132Sanholt#define BCI_CMD_SRC_MONO 0x00000060 382145132Sanholt#define BCI_CMD_SRC_PBD_COLOR 0x00000080 383145132Sanholt#define BCI_CMD_SRC_PBD_MONO 0x000000A0 384145132Sanholt#define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0 385145132Sanholt#define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0 386145132Sanholt#define BCI_CMD_SRC_SBD_COLOR 0x00000100 387145132Sanholt#define BCI_CMD_SRC_SBD_MONO 0x00000120 388145132Sanholt#define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140 389145132Sanholt#define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160 390145132Sanholt 391145132Sanholt#define BCI_CMD_PAT_TRANSPARENT 0x00000010 392145132Sanholt#define BCI_CMD_PAT_NONE 0x00000000 393145132Sanholt#define BCI_CMD_PAT_COLOR 0x00000002 394145132Sanholt#define BCI_CMD_PAT_MONO 0x00000003 395145132Sanholt#define BCI_CMD_PAT_PBD_COLOR 0x00000004 396145132Sanholt#define BCI_CMD_PAT_PBD_MONO 0x00000005 397145132Sanholt#define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006 398145132Sanholt#define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007 399145132Sanholt#define BCI_CMD_PAT_SBD_COLOR 0x00000008 400145132Sanholt#define BCI_CMD_PAT_SBD_MONO 0x00000009 401145132Sanholt#define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A 402145132Sanholt#define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B 403145132Sanholt 404145132Sanholt#define BCI_BD_BW_DISABLE 0x10000000 405145132Sanholt#define BCI_BD_TILE_MASK 0x03000000 406145132Sanholt#define BCI_BD_TILE_NONE 0x00000000 407145132Sanholt#define BCI_BD_TILE_16 0x02000000 408145132Sanholt#define BCI_BD_TILE_32 0x03000000 409145132Sanholt#define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF) 410145132Sanholt#define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16)) 411145132Sanholt#define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF) 412145132Sanholt#define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF)) 413145132Sanholt 414145132Sanholt#define BCI_CMD_SET_REGISTER 0x96000000 415145132Sanholt 416145132Sanholt#define BCI_CMD_WAIT 0xC0000000 417145132Sanholt#define BCI_CMD_WAIT_3D 0x00010000 418145132Sanholt#define BCI_CMD_WAIT_2D 0x00020000 419145132Sanholt 420145132Sanholt#define BCI_CMD_UPDATE_EVENT_TAG 0x98000000 421145132Sanholt 422145132Sanholt#define BCI_CMD_DRAW_PRIM 0x80000000 423145132Sanholt#define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000 424145132Sanholt#define BCI_CMD_DRAW_CONT 0x01000000 425145132Sanholt#define BCI_CMD_DRAW_TRILIST 0x00000000 426145132Sanholt#define BCI_CMD_DRAW_TRISTRIP 0x02000000 427145132Sanholt#define BCI_CMD_DRAW_TRIFAN 0x04000000 428145132Sanholt#define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff 429145132Sanholt#define BCI_CMD_DRAW_NO_Z 0x00000001 430145132Sanholt#define BCI_CMD_DRAW_NO_W 0x00000002 431145132Sanholt#define BCI_CMD_DRAW_NO_CD 0x00000004 432145132Sanholt#define BCI_CMD_DRAW_NO_CS 0x00000008 433145132Sanholt#define BCI_CMD_DRAW_NO_U0 0x00000010 434145132Sanholt#define BCI_CMD_DRAW_NO_V0 0x00000020 435145132Sanholt#define BCI_CMD_DRAW_NO_UV0 0x00000030 436145132Sanholt#define BCI_CMD_DRAW_NO_U1 0x00000040 437145132Sanholt#define BCI_CMD_DRAW_NO_V1 0x00000080 438145132Sanholt#define BCI_CMD_DRAW_NO_UV1 0x000000c0 439145132Sanholt 440145132Sanholt#define BCI_CMD_DMA 0xa8000000 441145132Sanholt 442145132Sanholt#define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF) 443145132Sanholt#define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF) 444145132Sanholt#define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF) 445145132Sanholt#define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF) 446145132Sanholt#define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF) 447145132Sanholt#define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF) 448145132Sanholt 449145132Sanholt#define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF)) 450145132Sanholt#define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF)) 451145132Sanholt#define BCI_LINE_MISC(maj, ym, xp, yp, err) \ 452145132Sanholt (((maj) & 0x1FFF) | \ 453145132Sanholt ((ym) ? 1<<13 : 0) | \ 454145132Sanholt ((xp) ? 1<<14 : 0) | \ 455145132Sanholt ((yp) ? 1<<15 : 0) | \ 456145132Sanholt ((err) << 16)) 457145132Sanholt 458145132Sanholt/* 459145132Sanholt * common commands 460145132Sanholt */ 461145132Sanholt#define BCI_SET_REGISTERS( first, n ) \ 462145132Sanholt BCI_WRITE(BCI_CMD_SET_REGISTER | \ 463145132Sanholt ((uint32_t)(n) & 0xff) << 16 | \ 464145132Sanholt ((uint32_t)(first) & 0xffff)) 465145132Sanholt#define DMA_SET_REGISTERS( first, n ) \ 466145132Sanholt DMA_WRITE(BCI_CMD_SET_REGISTER | \ 467145132Sanholt ((uint32_t)(n) & 0xff) << 16 | \ 468145132Sanholt ((uint32_t)(first) & 0xffff)) 469145132Sanholt 470145132Sanholt#define BCI_DRAW_PRIMITIVE(n, type, skip) \ 471145132Sanholt BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ 472145132Sanholt ((n) << 16)) 473145132Sanholt#define DMA_DRAW_PRIMITIVE(n, type, skip) \ 474145132Sanholt DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ 475145132Sanholt ((n) << 16)) 476145132Sanholt 477145132Sanholt#define BCI_DRAW_INDICES_S3D(n, type, i0) \ 478145132Sanholt BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ 479145132Sanholt ((n) << 16) | (i0)) 480145132Sanholt 481145132Sanholt#define BCI_DRAW_INDICES_S4(n, type, skip) \ 482145132Sanholt BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ 483145132Sanholt (skip) | ((n) << 16)) 484145132Sanholt 485145132Sanholt#define BCI_DMA(n) \ 486145132Sanholt BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1)) 487145132Sanholt 488145132Sanholt/* 489145132Sanholt * access to MMIO 490145132Sanholt */ 491145132Sanholt#define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 492145132Sanholt#define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) ) 493145132Sanholt 494145132Sanholt/* 495145132Sanholt * access to the burst command interface (BCI) 496145132Sanholt */ 497145132Sanholt#define SAVAGE_BCI_DEBUG 1 498145132Sanholt 499145132Sanholt#define BCI_LOCALS volatile uint32_t *bci_ptr; 500145132Sanholt 501145132Sanholt#define BEGIN_BCI( n ) do { \ 502145132Sanholt dev_priv->wait_fifo(dev_priv, (n)); \ 503145132Sanholt bci_ptr = dev_priv->bci_ptr; \ 504145132Sanholt} while(0) 505145132Sanholt 506145132Sanholt#define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val) 507145132Sanholt 508145132Sanholt/* 509145132Sanholt * command DMA support 510145132Sanholt */ 511145132Sanholt#define SAVAGE_DMA_DEBUG 1 512145132Sanholt 513145132Sanholt#define DMA_LOCALS uint32_t *dma_ptr; 514145132Sanholt 515145132Sanholt#define BEGIN_DMA( n ) do { \ 516145132Sanholt unsigned int cur = dev_priv->current_dma_page; \ 517145132Sanholt unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \ 518145132Sanholt dev_priv->dma_pages[cur].used; \ 519145132Sanholt if ((n) > rest) { \ 520145132Sanholt dma_ptr = savage_dma_alloc(dev_priv, (n)); \ 521145132Sanholt } else { /* fast path for small allocations */ \ 522145132Sanholt dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \ 523145132Sanholt cur * SAVAGE_DMA_PAGE_SIZE + \ 524145132Sanholt dev_priv->dma_pages[cur].used; \ 525145132Sanholt if (dev_priv->dma_pages[cur].used == 0) \ 526145132Sanholt savage_dma_wait(dev_priv, cur); \ 527145132Sanholt dev_priv->dma_pages[cur].used += (n); \ 528145132Sanholt } \ 529145132Sanholt} while(0) 530145132Sanholt 531145132Sanholt#define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val) 532145132Sanholt 533152909Sanholt#define DMA_COPY(src, n) do { \ 534152909Sanholt memcpy(dma_ptr, (src), (n)*4); \ 535145132Sanholt dma_ptr += n; \ 536145132Sanholt} while(0) 537145132Sanholt 538145132Sanholt#if SAVAGE_DMA_DEBUG 539145132Sanholt#define DMA_COMMIT() do { \ 540145132Sanholt unsigned int cur = dev_priv->current_dma_page; \ 541145132Sanholt uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \ 542145132Sanholt cur * SAVAGE_DMA_PAGE_SIZE + \ 543145132Sanholt dev_priv->dma_pages[cur].used; \ 544145132Sanholt if (dma_ptr != expected) { \ 545145132Sanholt DRM_ERROR("DMA allocation and use don't match: " \ 546145132Sanholt "%p != %p\n", expected, dma_ptr); \ 547145132Sanholt savage_dma_reset(dev_priv); \ 548145132Sanholt } \ 549145132Sanholt} while(0) 550145132Sanholt#else 551145132Sanholt#define DMA_COMMIT() do {/* nothing */} while(0) 552145132Sanholt#endif 553145132Sanholt 554145132Sanholt#define DMA_FLUSH() dev_priv->dma_flush(dev_priv) 555145132Sanholt 556145132Sanholt/* Buffer aging via event tag 557145132Sanholt */ 558145132Sanholt 559145132Sanholt#define UPDATE_EVENT_COUNTER( ) do { \ 560145132Sanholt if (dev_priv->status_ptr) { \ 561145132Sanholt uint16_t count; \ 562145132Sanholt /* coordinate with Xserver */ \ 563145132Sanholt count = dev_priv->status_ptr[1023]; \ 564145132Sanholt if (count < dev_priv->event_counter) \ 565145132Sanholt dev_priv->event_wrap++; \ 566145132Sanholt dev_priv->event_counter = count; \ 567145132Sanholt } \ 568145132Sanholt} while(0) 569145132Sanholt 570145132Sanholt#define SET_AGE( age, e, w ) do { \ 571145132Sanholt (age)->event = e; \ 572145132Sanholt (age)->wrap = w; \ 573145132Sanholt} while(0) 574145132Sanholt 575145132Sanholt#define TEST_AGE( age, e, w ) \ 576145132Sanholt ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) ) 577145132Sanholt 578145132Sanholt#endif /* __SAVAGE_DRV_H__ */ 579