1183724Ssos/*- 2183724Ssos * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3183724Ssos * All rights reserved. 4183724Ssos * 5183724Ssos * Redistribution and use in source and binary forms, with or without 6183724Ssos * modification, are permitted provided that the following conditions 7183724Ssos * are met: 8183724Ssos * 1. Redistributions of source code must retain the above copyright 9183724Ssos * notice, this list of conditions and the following disclaimer, 10183724Ssos * without modification, immediately at the beginning of the file. 11183724Ssos * 2. Redistributions in binary form must reproduce the above copyright 12183724Ssos * notice, this list of conditions and the following disclaimer in the 13183724Ssos * documentation and/or other materials provided with the distribution. 14183724Ssos * 15183724Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183724Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17183724Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18183724Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19183724Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20183724Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21183724Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22183724Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23183724Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24183724Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25183724Ssos */ 26183724Ssos 27183724Ssos#include <sys/cdefs.h> 28183724Ssos__FBSDID("$FreeBSD$"); 29183724Ssos 30183724Ssos#include "opt_ata.h" 31183724Ssos#include <sys/param.h> 32183724Ssos#include <sys/module.h> 33183724Ssos#include <sys/systm.h> 34183724Ssos#include <sys/kernel.h> 35183724Ssos#include <sys/ata.h> 36183724Ssos#include <sys/bus.h> 37183724Ssos#include <sys/endian.h> 38183724Ssos#include <sys/malloc.h> 39183724Ssos#include <sys/lock.h> 40183724Ssos#include <sys/mutex.h> 41183724Ssos#include <sys/sema.h> 42183724Ssos#include <sys/taskqueue.h> 43183724Ssos#include <vm/uma.h> 44183724Ssos#include <machine/stdarg.h> 45183724Ssos#include <machine/resource.h> 46183724Ssos#include <machine/bus.h> 47183724Ssos#include <sys/rman.h> 48183724Ssos#include <dev/pci/pcivar.h> 49183724Ssos#include <dev/pci/pcireg.h> 50183724Ssos#include <dev/ata/ata-all.h> 51183724Ssos#include <dev/ata/ata-pci.h> 52183724Ssos#include <ata_if.h> 53183724Ssos 54183724Ssos/* local prototypes */ 55183724Ssosstatic int ata_sis_chipinit(device_t dev); 56188765Smavstatic int ata_sis_ch_attach(device_t dev); 57183724Ssosstatic void ata_sis_reset(device_t dev); 58200171Smavstatic int ata_sis_setmode(device_t dev, int target, int mode); 59183724Ssos 60183724Ssos/* misc defines */ 61183724Ssos#define SIS_33 1 62183724Ssos#define SIS_66 2 63183724Ssos#define SIS_100NEW 3 64183724Ssos#define SIS_100OLD 4 65183724Ssos#define SIS_133NEW 5 66183724Ssos#define SIS_133OLD 6 67183724Ssos#define SIS_SATA 7 68183724Ssos 69183724Ssos/* 70183724Ssos * Silicon Integrated Systems Corp. (SiS) chipset support functions 71183724Ssos */ 72183724Ssosstatic int 73183724Ssosata_sis_probe(device_t dev) 74183724Ssos{ 75183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 76233717Smarius const struct ata_chip_id *idx; 77242908Sdim static const struct ata_chip_id ids[] = 78183724Ssos {{ ATA_SIS182, 0x00, SIS_SATA, 0, ATA_SA150, "182" }, /* south */ 79183724Ssos { ATA_SIS181, 0x00, SIS_SATA, 0, ATA_SA150, "181" }, /* south */ 80183724Ssos { ATA_SIS180, 0x00, SIS_SATA, 0, ATA_SA150, "180" }, /* south */ 81183724Ssos { ATA_SIS965, 0x00, SIS_133NEW, 0, ATA_UDMA6, "965" }, /* south */ 82183724Ssos { ATA_SIS964, 0x00, SIS_133NEW, 0, ATA_UDMA6, "964" }, /* south */ 83183724Ssos { ATA_SIS963, 0x00, SIS_133NEW, 0, ATA_UDMA6, "963" }, /* south */ 84183724Ssos { ATA_SIS962, 0x00, SIS_133NEW, 0, ATA_UDMA6, "962" }, /* south */ 85183724Ssos 86183724Ssos { ATA_SIS745, 0x00, SIS_100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 87183724Ssos { ATA_SIS735, 0x00, SIS_100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 88183724Ssos { ATA_SIS733, 0x00, SIS_100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 89183724Ssos { ATA_SIS730, 0x00, SIS_100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 90183724Ssos 91183724Ssos { ATA_SIS635, 0x00, SIS_100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 92183724Ssos { ATA_SIS633, 0x00, SIS_100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 93183724Ssos { ATA_SIS630, 0x30, SIS_100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 94183724Ssos { ATA_SIS630, 0x00, SIS_66, 0, ATA_UDMA4, "630" }, /* 1chip */ 95183724Ssos { ATA_SIS620, 0x00, SIS_66, 0, ATA_UDMA4, "620" }, /* 1chip */ 96183724Ssos 97183724Ssos { ATA_SIS550, 0x00, SIS_66, 0, ATA_UDMA5, "550" }, 98183724Ssos { ATA_SIS540, 0x00, SIS_66, 0, ATA_UDMA4, "540" }, 99183724Ssos { ATA_SIS530, 0x00, SIS_66, 0, ATA_UDMA4, "530" }, 100183724Ssos 101183724Ssos { ATA_SIS5513, 0xc2, SIS_33, 1, ATA_UDMA2, "5513" }, 102183724Ssos { ATA_SIS5513, 0x00, SIS_33, 1, ATA_WDMA2, "5513" }, 103183724Ssos { 0, 0, 0, 0, 0, 0 }}; 104233717Smarius static struct ata_chip_id id[] = 105233717Smarius {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 106183724Ssos char buffer[64]; 107183724Ssos int found = 0; 108183724Ssos 109186296Smav if (pci_get_class(dev) != PCIC_STORAGE) 110186296Smav return (ENXIO); 111186296Smav 112183724Ssos if (pci_get_vendor(dev) != ATA_SIS_ID) 113183724Ssos return ENXIO; 114183724Ssos 115183724Ssos if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 116183724Ssos return ENXIO; 117183724Ssos 118233717Smarius if (idx->cfg2) { 119183724Ssos u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 120183724Ssos 121183724Ssos pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 122183724Ssos if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 123183724Ssos found = 1; 124233717Smarius memcpy(&id[0], idx, sizeof(id[0])); 125233717Smarius id[0].cfg1 = SIS_133NEW; 126233717Smarius id[0].max_dma = ATA_UDMA6; 127183724Ssos sprintf(buffer, "SiS 962/963 %s controller", 128183724Ssos ata_mode2str(idx->max_dma)); 129183724Ssos } 130183724Ssos pci_write_config(dev, 0x57, reg57, 1); 131183724Ssos } 132183724Ssos if (idx->cfg2 && !found) { 133183724Ssos u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 134183724Ssos 135183724Ssos pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 136183724Ssos if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 137183724Ssos found = 1; 138183724Ssos if (ata_find_chip(dev, id, pci_get_slot(dev))) { 139233717Smarius id[0].cfg1 = SIS_133OLD; 140233717Smarius id[0].max_dma = ATA_UDMA6; 141233717Smarius } else { 142233717Smarius id[0].cfg1 = SIS_100NEW; 143233717Smarius id[0].max_dma = ATA_UDMA5; 144183724Ssos } 145183724Ssos sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 146183724Ssos } 147183724Ssos pci_write_config(dev, 0x4a, reg4a, 1); 148183724Ssos } 149183724Ssos if (!found) 150183724Ssos sprintf(buffer,"SiS %s %s controller", 151183724Ssos idx->text, ata_mode2str(idx->max_dma)); 152233717Smarius else 153233717Smarius idx = &id[0]; 154183724Ssos 155183724Ssos device_set_desc_copy(dev, buffer); 156183724Ssos ctlr->chip = idx; 157183724Ssos ctlr->chipinit = ata_sis_chipinit; 158194893Smav return (BUS_PROBE_DEFAULT); 159183724Ssos} 160183724Ssos 161183724Ssosstatic int 162183724Ssosata_sis_chipinit(device_t dev) 163183724Ssos{ 164183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 165183724Ssos 166183724Ssos if (ata_setup_interrupt(dev, ata_generic_intr)) 167183724Ssos return ENXIO; 168183724Ssos 169183724Ssos switch (ctlr->chip->cfg1) { 170183724Ssos case SIS_33: 171183724Ssos break; 172183724Ssos case SIS_66: 173183724Ssos case SIS_100OLD: 174183724Ssos pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 175183724Ssos break; 176183724Ssos case SIS_100NEW: 177183724Ssos case SIS_133OLD: 178183724Ssos pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 179183724Ssos break; 180183724Ssos case SIS_133NEW: 181183724Ssos pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 182183724Ssos pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 183183724Ssos break; 184183724Ssos case SIS_SATA: 185183724Ssos ctlr->r_type2 = SYS_RES_IOPORT; 186183724Ssos ctlr->r_rid2 = PCIR_BAR(5); 187183724Ssos if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 188183724Ssos &ctlr->r_rid2, RF_ACTIVE))) { 189188765Smav ctlr->ch_attach = ata_sis_ch_attach; 190188769Smav ctlr->ch_detach = ata_pci_ch_detach; 191183724Ssos ctlr->reset = ata_sis_reset; 192183724Ssos } 193183724Ssos ctlr->setmode = ata_sata_setmode; 194200171Smav ctlr->getrev = ata_sata_getrev; 195183724Ssos return 0; 196183724Ssos default: 197183724Ssos return ENXIO; 198183724Ssos } 199183724Ssos ctlr->setmode = ata_sis_setmode; 200183724Ssos return 0; 201183724Ssos} 202183724Ssos 203183724Ssosstatic int 204188765Smavata_sis_ch_attach(device_t dev) 205183724Ssos{ 206183724Ssos struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 207183724Ssos struct ata_channel *ch = device_get_softc(dev); 208183724Ssos int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 209183724Ssos 210183724Ssos /* setup the usual register normal pci style */ 211188765Smav if (ata_pci_ch_attach(dev)) 212183724Ssos return ENXIO; 213183724Ssos 214183724Ssos ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 215183724Ssos ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 216183724Ssos ch->r_io[ATA_SERROR].res = ctlr->r_res2; 217183724Ssos ch->r_io[ATA_SERROR].offset = 0x04 + offset; 218183724Ssos ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 219183724Ssos ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 220183724Ssos ch->flags |= ATA_NO_SLAVE; 221200171Smav ch->flags |= ATA_SATA; 222183724Ssos 223183724Ssos /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 224183724Ssos /* XXX SOS unknown how to enable PHY state change interrupt */ 225183724Ssos return 0; 226183724Ssos} 227183724Ssos 228183724Ssosstatic void 229183724Ssosata_sis_reset(device_t dev) 230183724Ssos{ 231209884Smav struct ata_channel *ch = device_get_softc(dev); 232209884Smav 233190581Smav if (ata_sata_phy_reset(dev, -1, 1)) 234183724Ssos ata_generic_reset(dev); 235209884Smav else 236209884Smav ch->devices = 0; 237183724Ssos} 238183724Ssos 239200171Smavstatic int 240200171Smavata_sis_setmode(device_t dev, int target, int mode) 241183724Ssos{ 242200171Smav device_t parent = device_get_parent(dev); 243200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 244200171Smav struct ata_channel *ch = device_get_softc(dev); 245200171Smav int devno = (ch->unit << 1) + target; 246183724Ssos 247200171Smav mode = min(mode, ctlr->chip->max_dma); 248183724Ssos 249200171Smav if (ctlr->chip->cfg1 == SIS_133NEW) { 250209872Smav if (ata_dma_check_80pin && mode > ATA_UDMA2 && 251200171Smav pci_read_config(parent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 252200171Smav ata_print_cable(dev, "controller"); 253200171Smav mode = ATA_UDMA2; 254200171Smav } 255200171Smav } else { 256209872Smav if (ata_dma_check_80pin && mode > ATA_UDMA2 && 257200171Smav pci_read_config(parent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 258200171Smav ata_print_cable(dev, "controller"); 259200171Smav mode = ATA_UDMA2; 260200171Smav } 261200171Smav } 262183724Ssos 263183724Ssos switch (ctlr->chip->cfg1) { 264183724Ssos case SIS_133NEW: { 265233717Smarius static const uint32_t timings[] = 266183724Ssos { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 267183724Ssos 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 268183724Ssos 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 269183724Ssos u_int32_t reg; 270183724Ssos 271200171Smav reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 272200171Smav pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4); 273183724Ssos break; 274183724Ssos } 275183724Ssos case SIS_133OLD: { 276233717Smarius static const uint16_t timings[] = 277183724Ssos { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 278183724Ssos 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 279183724Ssos 280183724Ssos u_int16_t reg = 0x40 + (devno << 1); 281183724Ssos 282200171Smav pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); 283183724Ssos break; 284183724Ssos } 285183724Ssos case SIS_100NEW: { 286233717Smarius static const uint16_t timings[] = 287183724Ssos { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 288183724Ssos 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 289183724Ssos u_int16_t reg = 0x40 + (devno << 1); 290183724Ssos 291200171Smav pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); 292183724Ssos break; 293183724Ssos } 294183724Ssos case SIS_100OLD: 295183724Ssos case SIS_66: 296183724Ssos case SIS_33: { 297233717Smarius static const uint16_t timings[] = 298183724Ssos { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 299183724Ssos 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 300183724Ssos u_int16_t reg = 0x40 + (devno << 1); 301183724Ssos 302200171Smav pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); 303183724Ssos break; 304183724Ssos } 305183724Ssos } 306200171Smav return (mode); 307183724Ssos} 308183724Ssos 309183724SsosATA_DECLARE_DRIVER(ata_sis); 310