1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_sis_chipinit(device_t dev); 56static int ata_sis_ch_attach(device_t dev); 57static void ata_sis_reset(device_t dev); 58static int ata_sis_setmode(device_t dev, int target, int mode); 59 60/* misc defines */ 61#define SIS_33 1 62#define SIS_66 2 63#define SIS_100NEW 3 64#define SIS_100OLD 4 65#define SIS_133NEW 5 66#define SIS_133OLD 6 67#define SIS_SATA 7 68 69/* 70 * Silicon Integrated Systems Corp. (SiS) chipset support functions 71 */ 72static int 73ata_sis_probe(device_t dev) 74{ 75 struct ata_pci_controller *ctlr = device_get_softc(dev); 76 const struct ata_chip_id *idx; 77 static const struct ata_chip_id ids[] = 78 {{ ATA_SIS182, 0x00, SIS_SATA, 0, ATA_SA150, "182" }, /* south */ 79 { ATA_SIS181, 0x00, SIS_SATA, 0, ATA_SA150, "181" }, /* south */ 80 { ATA_SIS180, 0x00, SIS_SATA, 0, ATA_SA150, "180" }, /* south */ 81 { ATA_SIS965, 0x00, SIS_133NEW, 0, ATA_UDMA6, "965" }, /* south */ 82 { ATA_SIS964, 0x00, SIS_133NEW, 0, ATA_UDMA6, "964" }, /* south */ 83 { ATA_SIS963, 0x00, SIS_133NEW, 0, ATA_UDMA6, "963" }, /* south */ 84 { ATA_SIS962, 0x00, SIS_133NEW, 0, ATA_UDMA6, "962" }, /* south */ 85 86 { ATA_SIS745, 0x00, SIS_100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 87 { ATA_SIS735, 0x00, SIS_100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 88 { ATA_SIS733, 0x00, SIS_100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 89 { ATA_SIS730, 0x00, SIS_100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 90 91 { ATA_SIS635, 0x00, SIS_100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 92 { ATA_SIS633, 0x00, SIS_100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 93 { ATA_SIS630, 0x30, SIS_100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 94 { ATA_SIS630, 0x00, SIS_66, 0, ATA_UDMA4, "630" }, /* 1chip */ 95 { ATA_SIS620, 0x00, SIS_66, 0, ATA_UDMA4, "620" }, /* 1chip */ 96 97 { ATA_SIS550, 0x00, SIS_66, 0, ATA_UDMA5, "550" }, 98 { ATA_SIS540, 0x00, SIS_66, 0, ATA_UDMA4, "540" }, 99 { ATA_SIS530, 0x00, SIS_66, 0, ATA_UDMA4, "530" }, 100 101 { ATA_SIS5513, 0xc2, SIS_33, 1, ATA_UDMA2, "5513" }, 102 { ATA_SIS5513, 0x00, SIS_33, 1, ATA_WDMA2, "5513" }, 103 { 0, 0, 0, 0, 0, 0 }}; 104 static struct ata_chip_id id[] = 105 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 106 char buffer[64]; 107 int found = 0; 108 109 if (pci_get_class(dev) != PCIC_STORAGE) 110 return (ENXIO); 111 112 if (pci_get_vendor(dev) != ATA_SIS_ID) 113 return ENXIO; 114 115 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 116 return ENXIO; 117 118 if (idx->cfg2) { 119 u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 120 121 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 122 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 123 found = 1; 124 memcpy(&id[0], idx, sizeof(id[0])); 125 id[0].cfg1 = SIS_133NEW; 126 id[0].max_dma = ATA_UDMA6; 127 sprintf(buffer, "SiS 962/963 %s controller", 128 ata_mode2str(idx->max_dma)); 129 } 130 pci_write_config(dev, 0x57, reg57, 1); 131 } 132 if (idx->cfg2 && !found) { 133 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 134 135 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 136 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 137 found = 1; 138 if (ata_find_chip(dev, id, pci_get_slot(dev))) { 139 id[0].cfg1 = SIS_133OLD; 140 id[0].max_dma = ATA_UDMA6; 141 } else { 142 id[0].cfg1 = SIS_100NEW; 143 id[0].max_dma = ATA_UDMA5; 144 } 145 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 146 } 147 pci_write_config(dev, 0x4a, reg4a, 1); 148 } 149 if (!found) 150 sprintf(buffer,"SiS %s %s controller", 151 idx->text, ata_mode2str(idx->max_dma)); 152 else 153 idx = &id[0]; 154 155 device_set_desc_copy(dev, buffer); 156 ctlr->chip = idx; 157 ctlr->chipinit = ata_sis_chipinit; 158 return (BUS_PROBE_DEFAULT); 159} 160 161static int 162ata_sis_chipinit(device_t dev) 163{ 164 struct ata_pci_controller *ctlr = device_get_softc(dev); 165 166 if (ata_setup_interrupt(dev, ata_generic_intr)) 167 return ENXIO; 168 169 switch (ctlr->chip->cfg1) { 170 case SIS_33: 171 break; 172 case SIS_66: 173 case SIS_100OLD: 174 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 175 break; 176 case SIS_100NEW: 177 case SIS_133OLD: 178 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 179 break; 180 case SIS_133NEW: 181 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 182 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 183 break; 184 case SIS_SATA: 185 ctlr->r_type2 = SYS_RES_IOPORT; 186 ctlr->r_rid2 = PCIR_BAR(5); 187 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 188 &ctlr->r_rid2, RF_ACTIVE))) { 189 ctlr->ch_attach = ata_sis_ch_attach; 190 ctlr->ch_detach = ata_pci_ch_detach; 191 ctlr->reset = ata_sis_reset; 192 } 193 ctlr->setmode = ata_sata_setmode; 194 ctlr->getrev = ata_sata_getrev; 195 return 0; 196 default: 197 return ENXIO; 198 } 199 ctlr->setmode = ata_sis_setmode; 200 return 0; 201} 202 203static int 204ata_sis_ch_attach(device_t dev) 205{ 206 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 207 struct ata_channel *ch = device_get_softc(dev); 208 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 209 210 /* setup the usual register normal pci style */ 211 if (ata_pci_ch_attach(dev)) 212 return ENXIO; 213 214 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 215 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 216 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 217 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 218 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 219 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 220 ch->flags |= ATA_NO_SLAVE; 221 ch->flags |= ATA_SATA; 222 223 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 224 /* XXX SOS unknown how to enable PHY state change interrupt */ 225 return 0; 226} 227 228static void 229ata_sis_reset(device_t dev) 230{ 231 struct ata_channel *ch = device_get_softc(dev); 232 233 if (ata_sata_phy_reset(dev, -1, 1)) 234 ata_generic_reset(dev); 235 else 236 ch->devices = 0; 237} 238 239static int 240ata_sis_setmode(device_t dev, int target, int mode) 241{ 242 device_t parent = device_get_parent(dev); 243 struct ata_pci_controller *ctlr = device_get_softc(parent); 244 struct ata_channel *ch = device_get_softc(dev); 245 int devno = (ch->unit << 1) + target; 246 247 mode = min(mode, ctlr->chip->max_dma); 248 249 if (ctlr->chip->cfg1 == SIS_133NEW) { 250 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 251 pci_read_config(parent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 252 ata_print_cable(dev, "controller"); 253 mode = ATA_UDMA2; 254 } 255 } else { 256 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 257 pci_read_config(parent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 258 ata_print_cable(dev, "controller"); 259 mode = ATA_UDMA2; 260 } 261 } 262 263 switch (ctlr->chip->cfg1) { 264 case SIS_133NEW: { 265 static const uint32_t timings[] = 266 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 267 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 268 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 269 u_int32_t reg; 270 271 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 272 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4); 273 break; 274 } 275 case SIS_133OLD: { 276 static const uint16_t timings[] = 277 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 278 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 279 280 u_int16_t reg = 0x40 + (devno << 1); 281 282 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); 283 break; 284 } 285 case SIS_100NEW: { 286 static const uint16_t timings[] = 287 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 288 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 289 u_int16_t reg = 0x40 + (devno << 1); 290 291 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); 292 break; 293 } 294 case SIS_100OLD: 295 case SIS_66: 296 case SIS_33: { 297 static const uint16_t timings[] = 298 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 299 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 300 u_int16_t reg = 0x40 + (devno << 1); 301 302 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); 303 break; 304 } 305 } 306 return (mode); 307} 308 309ATA_DECLARE_DRIVER(ata_sis); 310