Searched refs:pll (Results 1 - 25 of 30) sorted by relevance

12

/freebsd-11-stable/sys/dev/ath/ath_hal/ar9001/
H A Dar9130_phy.c34 uint32_t pll; local
40 pll = 0x1450;
42 pll = 0x1458;
44 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
H A Dar9160_attach.c92 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); local
95 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
97 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
100 pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV);
102 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
104 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
106 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
/freebsd-11-stable/sys/mips/atheros/
H A Dar934x_chip.c92 uint32_t pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; local
103 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL2_REG);
104 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
105 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
107 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL1_REG);
108 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
110 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
111 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
115 pll = ATH_READ_REG(AR934X_PLL_CPU_CONFIG_REG);
116 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIF
244 ar934x_chip_set_pll_ge(int unit, int speed, uint32_t pll) argument
291 uint32_t pll; local
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H A Dar91xx_chip.c68 uint32_t pll; local
74 pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
76 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
80 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
83 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
117 ar91xx_chip_set_pll_ge(int unit, int speed, uint32_t pll) argument
123 AR91XX_PLL_REG_ETH0_INT_CLOCK, pll,
128 AR91XX_PLL_REG_ETH1_INT_CLOCK, pll,
164 uint32_t pll; local
168 pll
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H A Dqca955x_chip.c77 uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; local
87 pll = ATH_READ_REG(QCA955X_PLL_CPU_CONFIG_REG);
88 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
90 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
92 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
94 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
101 pll = ATH_READ_REG(QCA955X_PLL_DDR_CONFIG_REG);
102 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
104 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
106 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIF
193 qca955x_chip_set_pll_ge(int unit, int speed, uint32_t pll) argument
243 uint32_t pll; local
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H A Dqca953x_chip.c76 uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; local
86 pll = ATH_READ_REG(QCA953X_PLL_CPU_CONFIG_REG);
87 out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
89 ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
91 nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
93 frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
100 pll = ATH_READ_REG(QCA953X_PLL_DDR_CONFIG_REG);
101 out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
103 ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
105 nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIF
192 qca953x_chip_set_pll_ge(int unit, int speed, uint32_t pll) argument
236 uint32_t pll; local
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H A Dar71xx_chip.c92 uint32_t pll; local
98 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
100 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
103 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
106 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
109 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
233 ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll) argument
239 AR71XX_PLL_ETH_INT0_CLK, pll,
244 AR71XX_PLL_ETH_INT1_CLK, pll,
280 uint32_t pll; local
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H A Dar724x_chip.c70 uint32_t pll; local
76 pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
78 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
81 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
86 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
89 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
144 ar724x_chip_set_pll_ge(int unit, int speed, uint32_t pll) argument
H A Dar933x_chip.c176 ar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll) argument
220 uint32_t pll; local
224 pll = AR933X_PLL_VAL_10;
227 pll = AR933X_PLL_VAL_100;
230 pll = AR933X_PLL_VAL_1000;
234 pll = 0;
236 return (pll);
H A Dar71xx_cpudef.h103 static inline void ar71xx_device_set_pll_ge(int unit, int speed, uint32_t pll) argument
105 ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed, pll);
H A Dar71xxreg.h544 ar71xx_write_pll(uint32_t cfg_reg, uint32_t pll_reg, uint32_t pll, uint32_t pll_reg_shift) argument
556 ATH_WRITE_REG(pll_reg, pll);
H A Dif_arge.c1246 uint32_t fifo_tx, pll; local
1326 pll = ar71xx_device_get_eth_pll(sc->arge_mac_unit, if_speed);
1327 ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: pll=0x%x\n", __func__, pll);
1331 pll = sc->arge_pllcfg.pll_10;
1333 pll = sc->arge_pllcfg.pll_100;
1335 pll = sc->arge_pllcfg.pll_1000;
1336 ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: final pll=0x%x\n", __func__, pll);
1338 /* XXX ensure pll !
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/freebsd-11-stable/sys/dev/drm2/radeon/
H A Dradeon_display.c748 static void avivo_get_fb_div(struct radeon_pll *pll, argument
758 *fb_div = tmp / pll->reference_freq;
759 *frac_fb_div = tmp % pll->reference_freq;
761 if (*fb_div > pll->max_feedback_div)
762 *fb_div = pll->max_feedback_div;
763 else if (*fb_div < pll->min_feedback_div)
764 *fb_div = pll->min_feedback_div;
767 static u32 avivo_get_post_div(struct radeon_pll *pll, argument
772 if (pll->flags & RADEON_PLL_USE_POST_DIV)
773 return pll
808 radeon_compute_pll_avivo(struct radeon_pll *pll, u32 freq, u32 *dot_clock_p, u32 *fb_div_p, u32 *frac_fb_div_p, u32 *ref_div_p, u32 *post_div_p) argument
876 radeon_compute_pll_legacy(struct radeon_pll *pll, uint64_t freq, uint32_t *dot_clock_p, uint32_t *fb_div_p, uint32_t *frac_fb_div_p, uint32_t *ref_div_p, uint32_t *post_div_p) argument
[all...]
H A Dradeon_legacy_crtc.c727 struct radeon_pll *pll; local
750 pll = &rdev->clock.p2pll;
752 pll = &rdev->clock.p1pll;
754 pll->flags = RADEON_PLL_LEGACY;
757 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
759 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
786 pll->flags |= RADEON_PLL_USE_REF_DIV;
794 radeon_compute_pll_legacy(pll, mode->clock,
825 pll_gain = radeon_compute_pll_gain(pll
[all...]
H A Datombios_crtc.c436 /* one other crtc is using this pll don't turn
544 /* reset the pll flags */
1001 struct radeon_pll *pll; local
1006 pll = &rdev->clock.p1pll;
1009 pll = &rdev->clock.p2pll;
1014 pll = &rdev->clock.dcpll;
1018 /* update pll params */
1019 pll->flags = radeon_crtc->pll_flags;
1020 pll->reference_div = radeon_crtc->pll_reference_div;
1021 pll
1628 int pll; local
[all...]
H A Dradeon_legacy_tv.c49 /* tv pll setting for 27 mhz ref clk */
58 /* tv pll setting for 14 mhz ref clk */
245 struct radeon_pll *pll; local
249 pll = &rdev->clock.p2pll;
251 pll = &rdev->clock.p1pll;
254 *pll_ref_freq = pll->reference_freq;
259 if (pll->reference_freq == 2700)
264 if (pll->reference_freq == 2700)
437 struct radeon_pll *pll; local
441 pll
[all...]
H A Dradeon_mode.h137 /* pll flags */
162 /* pll in/out limits */
184 /* pll id */
322 /* pll sharing */
573 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
581 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
/freebsd-11-stable/sys/arm/at91/
H A Dat91_pmcvar.h41 unsigned pll:1; member in struct:at91_pmc_clock
H A Dat91_pmc.c104 .pll = 1,
114 .pll = 1,
126 .pll = 1,
412 printf("pll = (%d / %d) * %d = %d\n",
/freebsd-11-stable/sys/dev/ath/ath_hal/ar9002/
H A Dar9280_attach.c107 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); local
116 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850;
118 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
120 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
122 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
125 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
127 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
129 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV);
131 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
133 pll |
[all...]
/freebsd-11-stable/sys/dev/siba/
H A Dsiba_core.c1157 uint32_t bufsth = 0, pll, pmu; local
1201 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0);
1202 pll &= ~(SIBA_CC_PMU1_PLL0_P1DIV | SIBA_CC_PMU1_PLL0_P2DIV);
1203 pll |= ((uint32_t)e->p1div << 20) & SIBA_CC_PMU1_PLL0_P1DIV;
1204 pll |= ((uint32_t)e->p2div << 24) & SIBA_CC_PMU1_PLL0_P2DIV;
1205 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll);
1207 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2);
1208 pll &= ~(SIBA_CC_PMU1_PLL2_NDIVINT | SIBA_CC_PMU1_PLL2_NDIVMODE);
1209 pll |= ((uint32_t)e->ndiv_int << 20) & SIBA_CC_PMU1_PLL2_NDIVINT;
1210 pll |
1239 uint32_t pmu, tmp, pll; local
[all...]
/freebsd-11-stable/sys/dev/drm2/i915/
H A Dintel_display.c1067 struct intel_pch_pll *pll,
1079 if (WARN (!pll,
1083 val = I915_READ(pll->pll_reg);
1087 pll->pll_reg, state_string(state), state_string(cur_state), val);
1094 cur_state = pll->pll_reg == _PCH_DPLL_B;
1101 pll->pll_reg == _PCH_DPLL_B,
1575 struct intel_pch_pll *pll; local
1581 pll = intel_crtc->pch_pll;
1582 if (pll == NULL)
1585 if (WARN_ON(pll
1066 assert_pch_pll(struct drm_i915_private *dev_priv, struct intel_pch_pll *pll, struct intel_crtc *crtc, bool state) argument
1615 struct intel_pch_pll *pll = intel_crtc->pch_pll; local
3221 struct intel_pch_pll *pll = intel_crtc->pch_pll; local
3238 struct intel_pch_pll *pll; local
5656 struct intel_pch_pll *pll; local
5862 struct intel_pch_pll *pll; local
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/freebsd-11-stable/sys/arm/freescale/imx/
H A Dimx51_ccm.c156 pll_read_4(struct imxccm_softc *sc, int pll, int reg) argument
159 return (bus_space_read_4(sc->pllbst, sc->pllbsh[pll - 1], reg));
515 printf("pll: %d\n", (uint32_t)freq);
/freebsd-11-stable/sys/x86/cpufreq/
H A Dpowernow.c224 u_int pll; member in struct:pn_softc
404 sc->pll * (uint64_t) sc->fsb,
417 sc->pll * (uint64_t) sc->fsb,
847 sc->pll = ACPI_PN8_CTRL_TO_PLL(ctrl),
/freebsd-11-stable/sys/dev/hifn/
H A Dhifn7751.c301 * non-PCI-compliant spread-spectrum clocks, which can confuse the pll.
304 hifn_getpllconfig(device_t dev, u_int *pll) argument
346 *pll = pllconfig;
555 printf(", pll=0x%x<%s clk, %ux mult>",
1176 u_int32_t pll; local
1183 pll = READ_REG_1(sc, HIFN_1_PLL);
1184 pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL))
1186 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1190 pll
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