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331722 |
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29-Mar-2018 |
eadler |
Revert r330897:
This was intended to be a non-functional change. It wasn't. The commit message was thus wrong. In addition it broke arm, and merged crypto related code.
Revert with prejudice.
This revert skips files touched in r316370 since that commit was since MFCed. This revert also skips files that require $FreeBSD$ property changes.
Thank you to those who helped me get out of this mess including but not limited to gonzo, kevans, rgrimes.
Requested by: gjb (re)
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285121 |
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04-Jul-2015 |
adrian |
Reshuffle all of the DDR flush operations into a single switch/mux, and start teaching subsystems about it.
The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler.
There are new ones for the QCA934x and QCA955x, so do a few things:
* Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation.
Tested:
* QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2)
TODO:
* PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
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276610 |
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03-Jan-2015 |
adrian |
Add a GPIO output mux configuration method.
The AR934x and later (which will turn up eventually) have a new GPIO output configuration option - a real MUX rather than a "GPIO or this function."
For now I'm squirreling it away in the CPU code just so it's done - I may move this to the GPIO layer later.
Specifically, this is required for setting up some boards that have external receive side LNA (low noise amplifier) that gets switched on/off by the on-chip wireless MAC. If we don't add this support for those boards then we'll end up with really poor performance.
(I don't yet have one of those APs, but it'll likely show up in a week.)
Obtained from: Linux OpenWRT
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256491 |
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15-Oct-2013 |
adrian |
Update the AR934x SoC support.
* Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method.
Tested:
* AR9344 SoC (DB120)
.. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
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