Lines Matching refs:pll
76 uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
86 pll = ATH_READ_REG(QCA953X_PLL_CPU_CONFIG_REG);
87 out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
89 ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
91 nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
93 frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
100 pll = ATH_READ_REG(QCA953X_PLL_DDR_CONFIG_REG);
101 out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
103 ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
105 nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
107 frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
192 qca953x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
196 ATH_WRITE_REG(QCA953X_PLL_ETH_XMII_CONTROL_REG, pll);
236 uint32_t pll;
240 pll = QCA953X_PLL_VAL_10;
243 pll = QCA953X_PLL_VAL_100;
246 pll = QCA953X_PLL_VAL_1000;
250 pll = 0;
252 return (pll);