Lines Matching refs:pll
92 uint32_t pll;
98 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
100 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
103 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
106 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
109 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
233 ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
239 AR71XX_PLL_ETH_INT0_CLK, pll,
244 AR71XX_PLL_ETH_INT1_CLK, pll,
280 uint32_t pll;
284 pll = PLL_ETH_INT_CLK_10;
287 pll = PLL_ETH_INT_CLK_100;
290 pll = PLL_ETH_INT_CLK_1000;
294 pll = 0;
297 return (pll);