1/*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD$");
29
30#include "opt_ddb.h"
31
32#include <sys/param.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/cons.h>
38#include <sys/kdb.h>
39#include <sys/reboot.h>
40
41#include <vm/vm.h>
42#include <vm/vm_page.h>
43
44#include <net/ethernet.h>
45
46#include <machine/clock.h>
47#include <machine/cpu.h>
48#include <machine/cpuregs.h>
49#include <machine/hwfunc.h>
50#include <machine/md_var.h>
51#include <machine/trap.h>
52#include <machine/vmparam.h>
53
54#include <mips/atheros/ar71xxreg.h>
55#include <mips/atheros/ar724xreg.h>
56
57#include <mips/atheros/ar71xx_cpudef.h>
58#include <mips/atheros/ar71xx_setup.h>
59#include <mips/atheros/ar71xx_chip.h>
60#include <mips/atheros/ar724x_chip.h>
61
62static void
63ar724x_chip_detect_mem_size(void)
64{
65}
66
67static void
68ar724x_chip_detect_sys_frequency(void)
69{
70	uint32_t pll;
71	uint32_t freq;
72	uint32_t div;
73
74	u_ar71xx_mdio_freq = u_ar71xx_refclk = AR724X_BASE_FREQ;
75
76	pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG);
77
78	div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
79	freq = div * AR724X_BASE_FREQ;
80
81	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
82	freq *= div;
83
84	u_ar71xx_cpu_freq = freq;
85
86	div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
87	u_ar71xx_ddr_freq = freq / div;
88
89	div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
90	u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
91	u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
92	u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
93}
94
95static void
96ar724x_chip_device_stop(uint32_t mask)
97{
98	uint32_t mask_inv, reg;
99
100	mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
101	reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
102	reg |= mask;
103	reg &= ~mask_inv;
104	ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
105}
106
107static void
108ar724x_chip_device_start(uint32_t mask)
109{
110	uint32_t mask_inv, reg;
111
112	mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL;
113	reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
114	reg &= ~mask;
115	reg |= mask_inv;
116	ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg);
117}
118
119static int
120ar724x_chip_device_stopped(uint32_t mask)
121{
122	uint32_t reg;
123
124	reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE);
125	return ((reg & mask) == mask);
126}
127
128static void
129ar724x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
130{
131
132	/* XXX TODO */
133	return;
134}
135
136/*
137 * XXX TODO: set the PLL for arge0 only on AR7242.
138 * The PLL/clock requirements are different.
139 *
140 * Otherwise, it's a NULL function for AR7240, AR7241 and
141 * AR7242 arge1.
142 */
143static void
144ar724x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
145{
146
147	switch (unit) {
148	case 0:
149		/* XXX TODO */
150		break;
151	case 1:
152		/* XXX TODO */
153		break;
154	default:
155		printf("%s: invalid PLL set for arge unit: %d\n",
156		    __func__, unit);
157		return;
158	}
159}
160
161static void
162ar724x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
163{
164
165	switch (id) {
166	case AR71XX_CPU_DDR_FLUSH_GE0:
167		ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
168		break;
169	case AR71XX_CPU_DDR_FLUSH_GE1:
170		ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
171		break;
172	case AR71XX_CPU_DDR_FLUSH_USB:
173		ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_USB);
174		break;
175	case AR71XX_CPU_DDR_FLUSH_PCIE:
176		ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE);
177		break;
178	default:
179		printf("%s: invalid DDR flush id (%d)\n", __func__, id);
180		break;
181	}
182}
183
184static uint32_t
185ar724x_chip_get_eth_pll(unsigned int mac, int speed)
186{
187
188	return (0);
189}
190
191static void
192ar724x_chip_init_usb_peripheral(void)
193{
194
195	switch (ar71xx_soc) {
196	case AR71XX_SOC_AR7240:
197		ar71xx_device_stop(AR724X_RESET_MODULE_USB_OHCI_DLL |
198		    AR724X_RESET_USB_HOST);
199		DELAY(1000);
200
201		ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL |
202		    AR724X_RESET_USB_HOST);
203		DELAY(1000);
204
205		/*
206		 * WAR for HW bug. Here it adjusts the duration
207		 * between two SOFS.
208		 */
209		ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
210		    (3 << USB_CTRL_FLADJ_A0_SHIFT));
211
212		break;
213
214	case AR71XX_SOC_AR7241:
215	case AR71XX_SOC_AR7242:
216		ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL);
217		DELAY(100);
218
219		ar71xx_device_start(AR724X_RESET_USB_HOST);
220		DELAY(100);
221
222		ar71xx_device_start(AR724X_RESET_USB_PHY);
223		DELAY(100);
224
225		break;
226
227	default:
228		break;
229	}
230}
231
232struct ar71xx_cpu_def ar724x_chip_def = {
233	&ar724x_chip_detect_mem_size,
234	&ar724x_chip_detect_sys_frequency,
235	&ar724x_chip_device_stop,
236	&ar724x_chip_device_start,
237	&ar724x_chip_device_stopped,
238	&ar724x_chip_set_pll_ge,
239	&ar724x_chip_set_mii_speed,
240	&ar71xx_chip_set_mii_if,
241	&ar724x_chip_get_eth_pll,
242	&ar724x_chip_ddr_flush,
243	&ar724x_chip_init_usb_peripheral
244};
245