1211503Sadrian/*- 2211503Sadrian * Copyright (c) 2010 Adrian Chadd 3211503Sadrian * All rights reserved. 4211503Sadrian * 5211503Sadrian * Redistribution and use in source and binary forms, with or without 6211503Sadrian * modification, are permitted provided that the following conditions 7211503Sadrian * are met: 8211503Sadrian * 1. Redistributions of source code must retain the above copyright 9211503Sadrian * notice, this list of conditions and the following disclaimer. 10211503Sadrian * 2. Redistributions in binary form must reproduce the above copyright 11211503Sadrian * notice, this list of conditions and the following disclaimer in the 12211503Sadrian * documentation and/or other materials provided with the distribution. 13211503Sadrian * 14211503Sadrian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15211503Sadrian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16211503Sadrian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17211503Sadrian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18211503Sadrian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19211503Sadrian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20211503Sadrian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21211503Sadrian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22211503Sadrian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23211503Sadrian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24211503Sadrian * SUCH DAMAGE. 25211503Sadrian */ 26211503Sadrian 27211503Sadrian#include <sys/cdefs.h> 28211503Sadrian__FBSDID("$FreeBSD$"); 29211503Sadrian 30211503Sadrian#include "opt_ddb.h" 31211503Sadrian 32211503Sadrian#include <sys/param.h> 33211503Sadrian#include <sys/conf.h> 34211503Sadrian#include <sys/kernel.h> 35211503Sadrian#include <sys/systm.h> 36211503Sadrian#include <sys/bus.h> 37211503Sadrian#include <sys/cons.h> 38211503Sadrian#include <sys/kdb.h> 39211503Sadrian#include <sys/reboot.h> 40228450Sadrian 41211503Sadrian#include <vm/vm.h> 42211503Sadrian#include <vm/vm_page.h> 43228450Sadrian 44211503Sadrian#include <net/ethernet.h> 45228450Sadrian 46211503Sadrian#include <machine/clock.h> 47211503Sadrian#include <machine/cpu.h> 48223562Skevlo#include <machine/cpuregs.h> 49211503Sadrian#include <machine/hwfunc.h> 50211503Sadrian#include <machine/md_var.h> 51211503Sadrian#include <machine/trap.h> 52211503Sadrian#include <machine/vmparam.h> 53228450Sadrian 54211503Sadrian#include <mips/atheros/ar71xxreg.h> 55211503Sadrian#include <mips/atheros/ar724xreg.h> 56211503Sadrian 57211503Sadrian#include <mips/atheros/ar71xx_cpudef.h> 58220180Sadrian#include <mips/atheros/ar71xx_setup.h> 59234906Sadrian#include <mips/atheros/ar71xx_chip.h> 60211503Sadrian#include <mips/atheros/ar724x_chip.h> 61211503Sadrian 62211503Sadrianstatic void 63211503Sadrianar724x_chip_detect_mem_size(void) 64211503Sadrian{ 65211503Sadrian} 66211503Sadrian 67211503Sadrianstatic void 68211503Sadrianar724x_chip_detect_sys_frequency(void) 69211503Sadrian{ 70211503Sadrian uint32_t pll; 71211503Sadrian uint32_t freq; 72211503Sadrian uint32_t div; 73228450Sadrian 74256487Sadrian u_ar71xx_mdio_freq = u_ar71xx_refclk = AR724X_BASE_FREQ; 75248781Sadrian 76211503Sadrian pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG); 77228450Sadrian 78211503Sadrian div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); 79211503Sadrian freq = div * AR724X_BASE_FREQ; 80211503Sadrian 81211503Sadrian div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); 82211503Sadrian freq *= div; 83228450Sadrian 84211503Sadrian u_ar71xx_cpu_freq = freq; 85228450Sadrian 86211503Sadrian div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; 87211503Sadrian u_ar71xx_ddr_freq = freq / div; 88228450Sadrian 89211503Sadrian div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; 90211503Sadrian u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; 91253508Sadrian u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div; 92253508Sadrian u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div; 93211503Sadrian} 94211503Sadrian 95211503Sadrianstatic void 96211503Sadrianar724x_chip_device_stop(uint32_t mask) 97211503Sadrian{ 98211503Sadrian uint32_t mask_inv, reg; 99211503Sadrian 100211503Sadrian mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL; 101211503Sadrian reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE); 102211503Sadrian reg |= mask; 103211503Sadrian reg &= ~mask_inv; 104211503Sadrian ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg); 105211503Sadrian} 106211503Sadrian 107211503Sadrianstatic void 108211503Sadrianar724x_chip_device_start(uint32_t mask) 109211503Sadrian{ 110211503Sadrian uint32_t mask_inv, reg; 111211503Sadrian 112211503Sadrian mask_inv = mask & AR724X_RESET_MODULE_USB_OHCI_DLL; 113211503Sadrian reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE); 114211503Sadrian reg &= ~mask; 115211503Sadrian reg |= mask_inv; 116211503Sadrian ATH_WRITE_REG(AR724X_RESET_REG_RESET_MODULE, reg); 117211503Sadrian} 118211503Sadrian 119211503Sadrianstatic int 120211503Sadrianar724x_chip_device_stopped(uint32_t mask) 121211503Sadrian{ 122211503Sadrian uint32_t reg; 123211503Sadrian 124211503Sadrian reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE); 125211503Sadrian return ((reg & mask) == mask); 126211503Sadrian} 127211503Sadrian 128211503Sadrianstatic void 129233081Sadrianar724x_chip_set_mii_speed(uint32_t unit, uint32_t speed) 130233081Sadrian{ 131233082Sadrian 132233081Sadrian /* XXX TODO */ 133233081Sadrian return; 134233081Sadrian} 135233081Sadrian 136234906Sadrian/* 137234906Sadrian * XXX TODO: set the PLL for arge0 only on AR7242. 138234906Sadrian * The PLL/clock requirements are different. 139234906Sadrian * 140234906Sadrian * Otherwise, it's a NULL function for AR7240, AR7241 and 141234906Sadrian * AR7242 arge1. 142234906Sadrian */ 143233081Sadrianstatic void 144234907Sadrianar724x_chip_set_pll_ge(int unit, int speed, uint32_t pll) 145211503Sadrian{ 146228450Sadrian 147228018Sray switch (unit) { 148228018Sray case 0: 149228450Sadrian /* XXX TODO */ 150228018Sray break; 151228018Sray case 1: 152228450Sadrian /* XXX TODO */ 153228018Sray break; 154228018Sray default: 155228018Sray printf("%s: invalid PLL set for arge unit: %d\n", 156228018Sray __func__, unit); 157228018Sray return; 158228018Sray } 159211503Sadrian} 160211503Sadrian 161211503Sadrianstatic void 162285121Sadrianar724x_chip_ddr_flush(ar71xx_flush_ddr_id_t id) 163211503Sadrian{ 164228450Sadrian 165285121Sadrian switch (id) { 166285121Sadrian case AR71XX_CPU_DDR_FLUSH_GE0: 167228018Sray ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); 168228018Sray break; 169285121Sadrian case AR71XX_CPU_DDR_FLUSH_GE1: 170228018Sray ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); 171228018Sray break; 172285121Sadrian case AR71XX_CPU_DDR_FLUSH_USB: 173285121Sadrian ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_USB); 174285121Sadrian break; 175285121Sadrian case AR71XX_CPU_DDR_FLUSH_PCIE: 176285121Sadrian ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE); 177285121Sadrian break; 178228018Sray default: 179285121Sadrian printf("%s: invalid DDR flush id (%d)\n", __func__, id); 180285121Sadrian break; 181228018Sray } 182211503Sadrian} 183211503Sadrian 184211503Sadrianstatic uint32_t 185211503Sadrianar724x_chip_get_eth_pll(unsigned int mac, int speed) 186211503Sadrian{ 187228450Sadrian 188234907Sadrian return (0); 189211503Sadrian} 190211503Sadrian 191220180Sadrianstatic void 192220180Sadrianar724x_chip_init_usb_peripheral(void) 193220180Sadrian{ 194220180Sadrian 195220180Sadrian switch (ar71xx_soc) { 196228450Sadrian case AR71XX_SOC_AR7240: 197228450Sadrian ar71xx_device_stop(AR724X_RESET_MODULE_USB_OHCI_DLL | 198228450Sadrian AR724X_RESET_USB_HOST); 199228450Sadrian DELAY(1000); 200220180Sadrian 201228450Sadrian ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL | 202228450Sadrian AR724X_RESET_USB_HOST); 203228450Sadrian DELAY(1000); 204220180Sadrian 205228450Sadrian /* 206228450Sadrian * WAR for HW bug. Here it adjusts the duration 207228450Sadrian * between two SOFS. 208228450Sadrian */ 209228450Sadrian ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ, 210228450Sadrian (3 << USB_CTRL_FLADJ_A0_SHIFT)); 211220180Sadrian 212228450Sadrian break; 213220180Sadrian 214228450Sadrian case AR71XX_SOC_AR7241: 215228450Sadrian case AR71XX_SOC_AR7242: 216228450Sadrian ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL); 217228450Sadrian DELAY(100); 218220180Sadrian 219228450Sadrian ar71xx_device_start(AR724X_RESET_USB_HOST); 220228450Sadrian DELAY(100); 221220180Sadrian 222228450Sadrian ar71xx_device_start(AR724X_RESET_USB_PHY); 223228450Sadrian DELAY(100); 224220180Sadrian 225228450Sadrian break; 226220180Sadrian 227228450Sadrian default: 228228450Sadrian break; 229220180Sadrian } 230220180Sadrian} 231220180Sadrian 232211503Sadrianstruct ar71xx_cpu_def ar724x_chip_def = { 233233082Sadrian &ar724x_chip_detect_mem_size, 234233082Sadrian &ar724x_chip_detect_sys_frequency, 235233082Sadrian &ar724x_chip_device_stop, 236233082Sadrian &ar724x_chip_device_start, 237233082Sadrian &ar724x_chip_device_stopped, 238233082Sadrian &ar724x_chip_set_pll_ge, 239233081Sadrian &ar724x_chip_set_mii_speed, 240234906Sadrian &ar71xx_chip_set_mii_if, 241233082Sadrian &ar724x_chip_get_eth_pll, 242285121Sadrian &ar724x_chip_ddr_flush, 243220180Sadrian &ar724x_chip_init_usb_peripheral 244211503Sadrian}; 245