Lines Matching refs:pll
68 uint32_t pll;
74 pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
76 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
80 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
83 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
117 ar91xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
123 AR91XX_PLL_REG_ETH0_INT_CLOCK, pll,
128 AR91XX_PLL_REG_ETH1_INT_CLOCK, pll,
164 uint32_t pll;
168 pll = AR91XX_PLL_VAL_10;
171 pll = AR91XX_PLL_VAL_100;
174 pll = AR91XX_PLL_VAL_1000;
178 pll = 0;
181 return (pll);