Lines Matching refs:pll
77 uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
87 pll = ATH_READ_REG(QCA955X_PLL_CPU_CONFIG_REG);
88 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
90 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
92 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
94 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
101 pll = ATH_READ_REG(QCA955X_PLL_DDR_CONFIG_REG);
102 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
104 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
106 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
108 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
193 qca955x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
197 ATH_WRITE_REG(QCA955X_PLL_ETH_XMII_CONTROL_REG, pll);
200 ATH_WRITE_REG(QCA955X_PLL_ETH_SGMII_CONTROL_REG, pll);
243 uint32_t pll;
247 pll = QCA955X_PLL_VAL_10;
250 pll = QCA955X_PLL_VAL_100;
253 pll = QCA955X_PLL_VAL_1000;
257 pll = 0;
259 return (pll);