Lines Matching refs:pll
107 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
116 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850;
118 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
120 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
122 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
125 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
127 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
129 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV);
131 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
133 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
136 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);