1/* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <dev/drm2/drmP.h> 31#include <dev/drm2/drm_crtc_helper.h> 32#include <dev/drm2/radeon/radeon_drm.h> 33#include <dev/drm2/drm_fixed.h> 34#include "radeon.h" 35#include "atom.h" 36 37static void radeon_overscan_setup(struct drm_crtc *crtc, 38 struct drm_display_mode *mode) 39{ 40 struct drm_device *dev = crtc->dev; 41 struct radeon_device *rdev = dev->dev_private; 42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 43 44 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); 45 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); 46 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); 47} 48 49static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 50 struct drm_display_mode *mode) 51{ 52 struct drm_device *dev = crtc->dev; 53 struct radeon_device *rdev = dev->dev_private; 54 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 55 int xres = mode->hdisplay; 56 int yres = mode->vdisplay; 57 bool hscale = true, vscale = true; 58 int hsync_wid; 59 int vsync_wid; 60 int hsync_start; 61 int blank_width; 62 u32 scale, inc, crtc_more_cntl; 63 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; 64 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; 65 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; 66 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; 67 68 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & 69 (RADEON_VERT_STRETCH_RESERVED | 70 RADEON_VERT_AUTO_RATIO_INC); 71 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & 72 (RADEON_HORZ_FP_LOOP_STRETCH | 73 RADEON_HORZ_AUTO_RATIO_INC); 74 75 crtc_more_cntl = 0; 76 if ((rdev->family == CHIP_RS100) || 77 (rdev->family == CHIP_RS200)) { 78 /* This is to workaround the asic bug for RMX, some versions 79 of BIOS doesn't have this register initialized correctly. */ 80 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; 81 } 82 83 84 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 85 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 86 87 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 88 if (!hsync_wid) 89 hsync_wid = 1; 90 hsync_start = mode->crtc_hsync_start - 8; 91 92 fp_h_sync_strt_wid = ((hsync_start & 0x1fff) 93 | ((hsync_wid & 0x3f) << 16) 94 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 95 ? RADEON_CRTC_H_SYNC_POL 96 : 0)); 97 98 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 99 | ((mode->crtc_vdisplay - 1) << 16)); 100 101 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 102 if (!vsync_wid) 103 vsync_wid = 1; 104 105 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 106 | ((vsync_wid & 0x1f) << 16) 107 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 108 ? RADEON_CRTC_V_SYNC_POL 109 : 0)); 110 111 fp_horz_vert_active = 0; 112 113 if (native_mode->hdisplay == 0 || 114 native_mode->vdisplay == 0) { 115 hscale = false; 116 vscale = false; 117 } else { 118 if (xres > native_mode->hdisplay) 119 xres = native_mode->hdisplay; 120 if (yres > native_mode->vdisplay) 121 yres = native_mode->vdisplay; 122 123 if (xres == native_mode->hdisplay) 124 hscale = false; 125 if (yres == native_mode->vdisplay) 126 vscale = false; 127 } 128 129 switch (radeon_crtc->rmx_type) { 130 case RMX_FULL: 131 case RMX_ASPECT: 132 if (!hscale) 133 fp_horz_stretch |= ((xres/8-1) << 16); 134 else { 135 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; 136 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) 137 / native_mode->hdisplay + 1; 138 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | 139 RADEON_HORZ_STRETCH_BLEND | 140 RADEON_HORZ_STRETCH_ENABLE | 141 ((native_mode->hdisplay/8-1) << 16)); 142 } 143 144 if (!vscale) 145 fp_vert_stretch |= ((yres-1) << 12); 146 else { 147 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; 148 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) 149 / native_mode->vdisplay + 1; 150 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | 151 RADEON_VERT_STRETCH_ENABLE | 152 RADEON_VERT_STRETCH_BLEND | 153 ((native_mode->vdisplay-1) << 12)); 154 } 155 break; 156 case RMX_CENTER: 157 fp_horz_stretch |= ((xres/8-1) << 16); 158 fp_vert_stretch |= ((yres-1) << 12); 159 160 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | 161 RADEON_CRTC_AUTO_VERT_CENTER_EN); 162 163 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; 164 if (blank_width > 110) 165 blank_width = 110; 166 167 fp_crtc_h_total_disp = (((blank_width) & 0x3ff) 168 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 169 170 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 171 if (!hsync_wid) 172 hsync_wid = 1; 173 174 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) 175 | ((hsync_wid & 0x3f) << 16) 176 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 177 ? RADEON_CRTC_H_SYNC_POL 178 : 0)); 179 180 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) 181 | ((mode->crtc_vdisplay - 1) << 16)); 182 183 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 184 if (!vsync_wid) 185 vsync_wid = 1; 186 187 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) 188 | ((vsync_wid & 0x1f) << 16) 189 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 190 ? RADEON_CRTC_V_SYNC_POL 191 : 0))); 192 193 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | 194 (((native_mode->hdisplay / 8) & 0x1ff) << 16)); 195 break; 196 case RMX_OFF: 197 default: 198 fp_horz_stretch |= ((xres/8-1) << 16); 199 fp_vert_stretch |= ((yres-1) << 12); 200 break; 201 } 202 203 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); 204 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); 205 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); 206 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); 207 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); 208 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); 209 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); 210 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); 211} 212 213static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) 214{ 215 struct radeon_device *rdev = dev->dev_private; 216 int i = 0; 217 218 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 219 the cause yet, but this workaround will mask the problem for now. 220 Other chips usually will pass at the very first test, so the 221 workaround shouldn't have any effect on them. */ 222 for (i = 0; 223 (i < 10000 && 224 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 225 i++); 226} 227 228static void radeon_pll_write_update(struct drm_device *dev) 229{ 230 struct radeon_device *rdev = dev->dev_private; 231 232 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 233 234 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 235 RADEON_PPLL_ATOMIC_UPDATE_W, 236 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 237} 238 239static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) 240{ 241 struct radeon_device *rdev = dev->dev_private; 242 int i = 0; 243 244 245 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 246 the cause yet, but this workaround will mask the problem for now. 247 Other chips usually will pass at the very first test, so the 248 workaround shouldn't have any effect on them. */ 249 for (i = 0; 250 (i < 10000 && 251 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 252 i++); 253} 254 255static void radeon_pll2_write_update(struct drm_device *dev) 256{ 257 struct radeon_device *rdev = dev->dev_private; 258 259 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 260 261 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 262 RADEON_P2PLL_ATOMIC_UPDATE_W, 263 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 264} 265 266static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, 267 uint16_t fb_div) 268{ 269 unsigned int vcoFreq; 270 271 if (!ref_div) 272 return 1; 273 274 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; 275 276 /* 277 * This is horribly crude: the VCO frequency range is divided into 278 * 3 parts, each part having a fixed PLL gain value. 279 */ 280 if (vcoFreq >= 30000) 281 /* 282 * [300..max] MHz : 7 283 */ 284 return 7; 285 else if (vcoFreq >= 18000) 286 /* 287 * [180..300) MHz : 4 288 */ 289 return 4; 290 else 291 /* 292 * [0..180) MHz : 1 293 */ 294 return 1; 295} 296 297static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) 298{ 299 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 300 struct drm_device *dev = crtc->dev; 301 struct radeon_device *rdev = dev->dev_private; 302 uint32_t crtc_ext_cntl = 0; 303 uint32_t mask; 304 305 if (radeon_crtc->crtc_id) 306 mask = (RADEON_CRTC2_DISP_DIS | 307 RADEON_CRTC2_VSYNC_DIS | 308 RADEON_CRTC2_HSYNC_DIS | 309 RADEON_CRTC2_DISP_REQ_EN_B); 310 else 311 mask = (RADEON_CRTC_DISPLAY_DIS | 312 RADEON_CRTC_VSYNC_DIS | 313 RADEON_CRTC_HSYNC_DIS); 314 315 /* 316 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC. 317 * Therefore it is set in the DAC DMPS function. 318 * This is different for GPU's with a single CRTC but a primary and a 319 * TV DAC: here it controls the single CRTC no matter where it is 320 * routed. Therefore we set it here. 321 */ 322 if (rdev->flags & RADEON_SINGLE_CRTC) 323 crtc_ext_cntl = RADEON_CRTC_CRT_ON; 324 325 switch (mode) { 326 case DRM_MODE_DPMS_ON: 327 radeon_crtc->enabled = true; 328 /* adjust pm to dpms changes BEFORE enabling crtcs */ 329 radeon_pm_compute_clocks(rdev); 330 if (radeon_crtc->crtc_id) 331 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); 332 else { 333 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | 334 RADEON_CRTC_DISP_REQ_EN_B)); 335 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); 336 } 337 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 338 radeon_crtc_load_lut(crtc); 339 break; 340 case DRM_MODE_DPMS_STANDBY: 341 case DRM_MODE_DPMS_SUSPEND: 342 case DRM_MODE_DPMS_OFF: 343 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 344 if (radeon_crtc->crtc_id) 345 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 346 else { 347 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | 348 RADEON_CRTC_DISP_REQ_EN_B)); 349 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); 350 } 351 radeon_crtc->enabled = false; 352 /* adjust pm to dpms changes AFTER disabling crtcs */ 353 radeon_pm_compute_clocks(rdev); 354 break; 355 } 356} 357 358int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 359 struct drm_framebuffer *old_fb) 360{ 361 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 362} 363 364int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 365 struct drm_framebuffer *fb, 366 int x, int y, enum mode_set_atomic state) 367{ 368 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 369} 370 371int radeon_crtc_do_set_base(struct drm_crtc *crtc, 372 struct drm_framebuffer *fb, 373 int x, int y, int atomic) 374{ 375 struct drm_device *dev = crtc->dev; 376 struct radeon_device *rdev = dev->dev_private; 377 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 378 struct radeon_framebuffer *radeon_fb; 379 struct drm_framebuffer *target_fb; 380 struct drm_gem_object *obj; 381 struct radeon_bo *rbo; 382 uint64_t base; 383 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; 384 uint32_t crtc_pitch, pitch_pixels; 385 uint32_t tiling_flags; 386 int format; 387 uint32_t gen_cntl_reg, gen_cntl_val; 388 int r; 389 390 DRM_DEBUG_KMS("\n"); 391 /* no fb bound */ 392 if (!atomic && !crtc->fb) { 393 DRM_DEBUG_KMS("No FB bound\n"); 394 return 0; 395 } 396 397 if (atomic) { 398 radeon_fb = to_radeon_framebuffer(fb); 399 target_fb = fb; 400 } 401 else { 402 radeon_fb = to_radeon_framebuffer(crtc->fb); 403 target_fb = crtc->fb; 404 } 405 406 switch (target_fb->bits_per_pixel) { 407 case 8: 408 format = 2; 409 break; 410 case 15: /* 555 */ 411 format = 3; 412 break; 413 case 16: /* 565 */ 414 format = 4; 415 break; 416 case 24: /* RGB */ 417 format = 5; 418 break; 419 case 32: /* xRGB */ 420 format = 6; 421 break; 422 default: 423 return false; 424 } 425 426 /* Pin framebuffer & get tilling informations */ 427 obj = radeon_fb->obj; 428 rbo = gem_to_radeon_bo(obj); 429 r = radeon_bo_reserve(rbo, false); 430 if (unlikely(r != 0)) 431 return r; 432 /* Only 27 bit offset for legacy CRTC */ 433 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27, 434 &base); 435 if (unlikely(r != 0)) { 436 radeon_bo_unreserve(rbo); 437 return -EINVAL; 438 } 439 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 440 radeon_bo_unreserve(rbo); 441 if (tiling_flags & RADEON_TILING_MICRO) 442 DRM_ERROR("trying to scanout microtiled buffer\n"); 443 444 /* if scanout was in GTT this really wouldn't work */ 445 /* crtc offset is from display base addr not FB location */ 446 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; 447 448 base -= radeon_crtc->legacy_display_base_addr; 449 450 crtc_offset_cntl = 0; 451 452 pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 453 crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) + 454 ((target_fb->bits_per_pixel * 8) - 1)) / 455 (target_fb->bits_per_pixel * 8)); 456 crtc_pitch |= crtc_pitch << 16; 457 458 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; 459 if (tiling_flags & RADEON_TILING_MACRO) { 460 if (ASIC_IS_R300(rdev)) 461 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 462 R300_CRTC_MICRO_TILE_BUFFER_DIS | 463 R300_CRTC_MACRO_TILE_EN); 464 else 465 crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 466 } else { 467 if (ASIC_IS_R300(rdev)) 468 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 469 R300_CRTC_MICRO_TILE_BUFFER_DIS | 470 R300_CRTC_MACRO_TILE_EN); 471 else 472 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 473 } 474 475 if (tiling_flags & RADEON_TILING_MACRO) { 476 if (ASIC_IS_R300(rdev)) { 477 crtc_tile_x0_y0 = x | (y << 16); 478 base &= ~0x7ff; 479 } else { 480 int byteshift = target_fb->bits_per_pixel >> 4; 481 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; 482 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 483 crtc_offset_cntl |= (y % 16); 484 } 485 } else { 486 int offset = y * pitch_pixels + x; 487 switch (target_fb->bits_per_pixel) { 488 case 8: 489 offset *= 1; 490 break; 491 case 15: 492 case 16: 493 offset *= 2; 494 break; 495 case 24: 496 offset *= 3; 497 break; 498 case 32: 499 offset *= 4; 500 break; 501 default: 502 return false; 503 } 504 base += offset; 505 } 506 507 base &= ~7; 508 509 if (radeon_crtc->crtc_id == 1) 510 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; 511 else 512 gen_cntl_reg = RADEON_CRTC_GEN_CNTL; 513 514 gen_cntl_val = RREG32(gen_cntl_reg); 515 gen_cntl_val &= ~(0xf << 8); 516 gen_cntl_val |= (format << 8); 517 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; 518 WREG32(gen_cntl_reg, gen_cntl_val); 519 520 crtc_offset = (u32)base; 521 522 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); 523 524 if (ASIC_IS_R300(rdev)) { 525 if (radeon_crtc->crtc_id) 526 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); 527 else 528 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); 529 } 530 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); 531 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); 532 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 533 534 if (!atomic && fb && fb != crtc->fb) { 535 radeon_fb = to_radeon_framebuffer(fb); 536 rbo = gem_to_radeon_bo(radeon_fb->obj); 537 r = radeon_bo_reserve(rbo, false); 538 if (unlikely(r != 0)) 539 return r; 540 radeon_bo_unpin(rbo); 541 radeon_bo_unreserve(rbo); 542 } 543 544 /* Bytes per pixel may have changed */ 545 radeon_bandwidth_update(rdev); 546 547 return 0; 548} 549 550static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) 551{ 552 struct drm_device *dev = crtc->dev; 553 struct radeon_device *rdev = dev->dev_private; 554 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 555 struct drm_encoder *encoder; 556 int format; 557 int hsync_start; 558 int hsync_wid; 559 int vsync_wid; 560 uint32_t crtc_h_total_disp; 561 uint32_t crtc_h_sync_strt_wid; 562 uint32_t crtc_v_total_disp; 563 uint32_t crtc_v_sync_strt_wid; 564 bool is_tv = false; 565 566 DRM_DEBUG_KMS("\n"); 567 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 568 if (encoder->crtc == crtc) { 569 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 570 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 571 is_tv = true; 572 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); 573 break; 574 } 575 } 576 } 577 578 switch (crtc->fb->bits_per_pixel) { 579 case 8: 580 format = 2; 581 break; 582 case 15: /* 555 */ 583 format = 3; 584 break; 585 case 16: /* 565 */ 586 format = 4; 587 break; 588 case 24: /* RGB */ 589 format = 5; 590 break; 591 case 32: /* xRGB */ 592 format = 6; 593 break; 594 default: 595 return false; 596 } 597 598 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 599 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 600 601 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 602 if (!hsync_wid) 603 hsync_wid = 1; 604 hsync_start = mode->crtc_hsync_start - 8; 605 606 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 607 | ((hsync_wid & 0x3f) << 16) 608 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 609 ? RADEON_CRTC_H_SYNC_POL 610 : 0)); 611 612 /* This works for double scan mode. */ 613 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 614 | ((mode->crtc_vdisplay - 1) << 16)); 615 616 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 617 if (!vsync_wid) 618 vsync_wid = 1; 619 620 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 621 | ((vsync_wid & 0x1f) << 16) 622 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 623 ? RADEON_CRTC_V_SYNC_POL 624 : 0)); 625 626 if (radeon_crtc->crtc_id) { 627 uint32_t crtc2_gen_cntl; 628 uint32_t disp2_merge_cntl; 629 630 /* if TV DAC is enabled for another crtc and keep it enabled */ 631 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; 632 crtc2_gen_cntl |= ((format << 8) 633 | RADEON_CRTC2_VSYNC_DIS 634 | RADEON_CRTC2_HSYNC_DIS 635 | RADEON_CRTC2_DISP_DIS 636 | RADEON_CRTC2_DISP_REQ_EN_B 637 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 638 ? RADEON_CRTC2_DBL_SCAN_EN 639 : 0) 640 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 641 ? RADEON_CRTC2_CSYNC_EN 642 : 0) 643 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 644 ? RADEON_CRTC2_INTERLACE_EN 645 : 0)); 646 647 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 648 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 649 crtc2_gen_cntl |= RADEON_CRTC2_EN; 650 651 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 652 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 653 654 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); 655 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 656 657 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); 658 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); 659 } else { 660 uint32_t crtc_gen_cntl; 661 uint32_t crtc_ext_cntl; 662 uint32_t disp_merge_cntl; 663 664 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; 665 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN 666 | (format << 8) 667 | RADEON_CRTC_DISP_REQ_EN_B 668 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 669 ? RADEON_CRTC_DBL_SCAN_EN 670 : 0) 671 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 672 ? RADEON_CRTC_CSYNC_EN 673 : 0) 674 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 675 ? RADEON_CRTC_INTERLACE_EN 676 : 0)); 677 678 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 679 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 680 crtc_gen_cntl |= RADEON_CRTC_EN; 681 682 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 683 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | 684 RADEON_CRTC_VSYNC_DIS | 685 RADEON_CRTC_HSYNC_DIS | 686 RADEON_CRTC_DISPLAY_DIS); 687 688 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 689 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 690 691 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 692 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 693 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 694 } 695 696 if (is_tv) 697 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, 698 &crtc_h_sync_strt_wid, &crtc_v_total_disp, 699 &crtc_v_sync_strt_wid); 700 701 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); 702 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); 703 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); 704 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); 705 706 return true; 707} 708 709static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 710{ 711 struct drm_device *dev = crtc->dev; 712 struct radeon_device *rdev = dev->dev_private; 713 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 714 struct drm_encoder *encoder; 715 uint32_t feedback_div = 0; 716 uint32_t frac_fb_div = 0; 717 uint32_t reference_div = 0; 718 uint32_t post_divider = 0; 719 uint32_t freq = 0; 720 uint8_t pll_gain; 721 bool use_bios_divs = false; 722 /* PLL registers */ 723 uint32_t pll_ref_div = 0; 724 uint32_t pll_fb_post_div = 0; 725 uint32_t htotal_cntl = 0; 726 bool is_tv = false; 727 struct radeon_pll *pll; 728 729 struct { 730 int divider; 731 int bitvalue; 732 } *post_div, post_divs[] = { 733 /* From RAGE 128 VR/RAGE 128 GL Register 734 * Reference Manual (Technical Reference 735 * Manual P/N RRG-G04100-C Rev. 0.04), page 736 * 3-17 (PLL_DIV_[3:0]). 737 */ 738 { 1, 0 }, /* VCLK_SRC */ 739 { 2, 1 }, /* VCLK_SRC/2 */ 740 { 4, 2 }, /* VCLK_SRC/4 */ 741 { 8, 3 }, /* VCLK_SRC/8 */ 742 { 3, 4 }, /* VCLK_SRC/3 */ 743 { 16, 5 }, /* VCLK_SRC/16 */ 744 { 6, 6 }, /* VCLK_SRC/6 */ 745 { 12, 7 }, /* VCLK_SRC/12 */ 746 { 0, 0 } 747 }; 748 749 if (radeon_crtc->crtc_id) 750 pll = &rdev->clock.p2pll; 751 else 752 pll = &rdev->clock.p1pll; 753 754 pll->flags = RADEON_PLL_LEGACY; 755 756 if (mode->clock > 200000) /* range limits??? */ 757 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 758 else 759 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 760 761 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 762 if (encoder->crtc == crtc) { 763 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 764 765 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 766 is_tv = true; 767 break; 768 } 769 770 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 771 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 772 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 773 if (!rdev->is_atom_bios) { 774 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 775 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 776 if (lvds) { 777 if (lvds->use_bios_dividers) { 778 pll_ref_div = lvds->panel_ref_divider; 779 pll_fb_post_div = (lvds->panel_fb_divider | 780 (lvds->panel_post_divider << 16)); 781 htotal_cntl = 0; 782 use_bios_divs = true; 783 } 784 } 785 } 786 pll->flags |= RADEON_PLL_USE_REF_DIV; 787 } 788 } 789 } 790 791 DRM_DEBUG_KMS("\n"); 792 793 if (!use_bios_divs) { 794 radeon_compute_pll_legacy(pll, mode->clock, 795 &freq, &feedback_div, &frac_fb_div, 796 &reference_div, &post_divider); 797 798 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 799 if (post_div->divider == post_divider) 800 break; 801 } 802 803 if (!post_div->divider) 804 post_div = &post_divs[0]; 805 806 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n", 807 (unsigned)freq, 808 feedback_div, 809 reference_div, 810 post_divider); 811 812 pll_ref_div = reference_div; 813#if defined(__powerpc__) && (0) /* TODO */ 814 /* apparently programming this otherwise causes a hang??? */ 815 if (info->MacModel == RADEON_MAC_IBOOK) 816 pll_fb_post_div = 0x000600ad; 817 else 818#endif 819 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); 820 821 htotal_cntl = mode->htotal & 0x7; 822 823 } 824 825 pll_gain = radeon_compute_pll_gain(pll->reference_freq, 826 pll_ref_div & 0x3ff, 827 pll_fb_post_div & 0x7ff); 828 829 if (radeon_crtc->crtc_id) { 830 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & 831 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 832 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 833 834 if (is_tv) { 835 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, 836 &pll_ref_div, &pll_fb_post_div, 837 &pixclks_cntl); 838 } 839 840 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 841 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 842 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 843 844 WREG32_PLL_P(RADEON_P2PLL_CNTL, 845 RADEON_P2PLL_RESET 846 | RADEON_P2PLL_ATOMIC_UPDATE_EN 847 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), 848 ~(RADEON_P2PLL_RESET 849 | RADEON_P2PLL_ATOMIC_UPDATE_EN 850 | RADEON_P2PLL_PVG_MASK)); 851 852 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 853 pll_ref_div, 854 ~RADEON_P2PLL_REF_DIV_MASK); 855 856 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 857 pll_fb_post_div, 858 ~RADEON_P2PLL_FB0_DIV_MASK); 859 860 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 861 pll_fb_post_div, 862 ~RADEON_P2PLL_POST0_DIV_MASK); 863 864 radeon_pll2_write_update(dev); 865 radeon_pll2_wait_for_read_update_complete(dev); 866 867 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); 868 869 WREG32_PLL_P(RADEON_P2PLL_CNTL, 870 0, 871 ~(RADEON_P2PLL_RESET 872 | RADEON_P2PLL_SLEEP 873 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 874 875 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 876 (unsigned)pll_ref_div, 877 (unsigned)pll_fb_post_div, 878 (unsigned)htotal_cntl, 879 RREG32_PLL(RADEON_P2PLL_CNTL)); 880 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n", 881 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 882 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, 883 (unsigned)((pll_fb_post_div & 884 RADEON_P2PLL_POST0_DIV_MASK) >> 16)); 885 886 mdelay(50); /* Let the clock to lock */ 887 888 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 889 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 890 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 891 892 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 893 } else { 894 uint32_t pixclks_cntl; 895 896 897 if (is_tv) { 898 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 899 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, 900 &pll_fb_post_div, &pixclks_cntl); 901 } 902 903 if (rdev->flags & RADEON_IS_MOBILITY) { 904 /* A temporal workaround for the occasional blanking on certain laptop panels. 905 This appears to related to the PLL divider registers (fail to lock?). 906 It occurs even when all dividers are the same with their old settings. 907 In this case we really don't need to fiddle with PLL registers. 908 By doing this we can avoid the blanking problem with some panels. 909 */ 910 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 911 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & 912 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 913 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 914 RADEON_PLL_DIV_SEL, 915 ~(RADEON_PLL_DIV_SEL)); 916 r100_pll_errata_after_index(rdev); 917 return; 918 } 919 } 920 921 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 922 RADEON_VCLK_SRC_SEL_CPUCLK, 923 ~(RADEON_VCLK_SRC_SEL_MASK)); 924 WREG32_PLL_P(RADEON_PPLL_CNTL, 925 RADEON_PPLL_RESET 926 | RADEON_PPLL_ATOMIC_UPDATE_EN 927 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 928 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), 929 ~(RADEON_PPLL_RESET 930 | RADEON_PPLL_ATOMIC_UPDATE_EN 931 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 932 | RADEON_PPLL_PVG_MASK)); 933 934 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 935 RADEON_PLL_DIV_SEL, 936 ~(RADEON_PLL_DIV_SEL)); 937 r100_pll_errata_after_index(rdev); 938 939 if (ASIC_IS_R300(rdev) || 940 (rdev->family == CHIP_RS300) || 941 (rdev->family == CHIP_RS400) || 942 (rdev->family == CHIP_RS480)) { 943 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 944 /* When restoring console mode, use saved PPLL_REF_DIV 945 * setting. 946 */ 947 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 948 pll_ref_div, 949 0); 950 } else { 951 /* R300 uses ref_div_acc field as real ref divider */ 952 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 953 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 954 ~R300_PPLL_REF_DIV_ACC_MASK); 955 } 956 } else 957 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 958 pll_ref_div, 959 ~RADEON_PPLL_REF_DIV_MASK); 960 961 WREG32_PLL_P(RADEON_PPLL_DIV_3, 962 pll_fb_post_div, 963 ~RADEON_PPLL_FB3_DIV_MASK); 964 965 WREG32_PLL_P(RADEON_PPLL_DIV_3, 966 pll_fb_post_div, 967 ~RADEON_PPLL_POST3_DIV_MASK); 968 969 radeon_pll_write_update(dev); 970 radeon_pll_wait_for_read_update_complete(dev); 971 972 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); 973 974 WREG32_PLL_P(RADEON_PPLL_CNTL, 975 0, 976 ~(RADEON_PPLL_RESET 977 | RADEON_PPLL_SLEEP 978 | RADEON_PPLL_ATOMIC_UPDATE_EN 979 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 980 981 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 982 pll_ref_div, 983 pll_fb_post_div, 984 (unsigned)htotal_cntl, 985 RREG32_PLL(RADEON_PPLL_CNTL)); 986 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n", 987 pll_ref_div & RADEON_PPLL_REF_DIV_MASK, 988 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, 989 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); 990 991 mdelay(50); /* Let the clock to lock */ 992 993 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 994 RADEON_VCLK_SRC_SEL_PPLLCLK, 995 ~(RADEON_VCLK_SRC_SEL_MASK)); 996 997 if (is_tv) 998 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 999 } 1000} 1001 1002static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, 1003 const struct drm_display_mode *mode, 1004 struct drm_display_mode *adjusted_mode) 1005{ 1006 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1007 return false; 1008 return true; 1009} 1010 1011static int radeon_crtc_mode_set(struct drm_crtc *crtc, 1012 struct drm_display_mode *mode, 1013 struct drm_display_mode *adjusted_mode, 1014 int x, int y, struct drm_framebuffer *old_fb) 1015{ 1016 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1017 1018 /* TODO TV */ 1019 radeon_crtc_set_base(crtc, x, y, old_fb); 1020 radeon_set_crtc_timing(crtc, adjusted_mode); 1021 radeon_set_pll(crtc, adjusted_mode); 1022 radeon_overscan_setup(crtc, adjusted_mode); 1023 if (radeon_crtc->crtc_id == 0) { 1024 radeon_legacy_rmx_mode_set(crtc, adjusted_mode); 1025 } else { 1026 if (radeon_crtc->rmx_type != RMX_OFF) { 1027 /* FIXME: only first crtc has rmx what should we 1028 * do ? 1029 */ 1030 DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); 1031 } 1032 } 1033 return 0; 1034} 1035 1036static void radeon_crtc_prepare(struct drm_crtc *crtc) 1037{ 1038 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1039 struct drm_device *dev = crtc->dev; 1040 struct drm_crtc *crtci; 1041 1042 radeon_crtc->in_mode_set = true; 1043 /* 1044 * The hardware wedges sometimes if you reconfigure one CRTC 1045 * whilst another is running (see fdo bug #24611). 1046 */ 1047 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) 1048 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF); 1049} 1050 1051static void radeon_crtc_commit(struct drm_crtc *crtc) 1052{ 1053 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1054 struct drm_device *dev = crtc->dev; 1055 struct drm_crtc *crtci; 1056 1057 /* 1058 * Reenable the CRTCs that should be running. 1059 */ 1060 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { 1061 if (crtci->enabled) 1062 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); 1063 } 1064 radeon_crtc->in_mode_set = false; 1065} 1066 1067static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1068 .dpms = radeon_crtc_dpms, 1069 .mode_fixup = radeon_crtc_mode_fixup, 1070 .mode_set = radeon_crtc_mode_set, 1071 .mode_set_base = radeon_crtc_set_base, 1072 .mode_set_base_atomic = radeon_crtc_set_base_atomic, 1073 .prepare = radeon_crtc_prepare, 1074 .commit = radeon_crtc_commit, 1075 .load_lut = radeon_crtc_load_lut, 1076}; 1077 1078 1079void radeon_legacy_init_crtc(struct drm_device *dev, 1080 struct radeon_crtc *radeon_crtc) 1081{ 1082 if (radeon_crtc->crtc_id == 1) 1083 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; 1084 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); 1085} 1086