mips/atheros/ar934x_chip.c

92 	uint32_t pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
103 	pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL2_REG);
104 	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
105 		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
107 		pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL1_REG);
108 		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
110 		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
111 		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
115 		pll = ATH_READ_REG(AR934X_PLL_CPU_CONFIG_REG);
116 		out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
118 		ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
120 		nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
122 		nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
130 	pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL2_REG);
131 	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
132 		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
134 		pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL1_REG);
135 		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
137 		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
138 		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
142 		pll = ATH_READ_REG(AR934X_PLL_DDR_CONFIG_REG);
143 		out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
145 		ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
147 		nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
149 		nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
244 ar934x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
249 		ATH_WRITE_REG(AR934X_PLL_ETH_XMII_CONTROL_REG, pll);
291 	uint32_t pll;
295 		pll = AR934X_PLL_VAL_10;
298 		pll = AR934X_PLL_VAL_100;
301 		pll = AR934X_PLL_VAL_1000;
305 		pll = 0;
307 	return (pll);