1104477Ssam/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 2104477Ssam 3139749Simp/*- 4104477Ssam * Invertex AEON / Hifn 7751 driver 5104477Ssam * Copyright (c) 1999 Invertex Inc. All rights reserved. 6104477Ssam * Copyright (c) 1999 Theo de Raadt 7104477Ssam * Copyright (c) 2000-2001 Network Security Technologies, Inc. 8104477Ssam * http://www.netsec.net 9120915Ssam * Copyright (c) 2003 Hifn Inc. 10104477Ssam * 11104477Ssam * This driver is based on a previous driver by Invertex, for which they 12104477Ssam * requested: Please send any comments, feedback, bug-fixes, or feature 13104477Ssam * requests to software@invertex.com. 14104477Ssam * 15104477Ssam * Redistribution and use in source and binary forms, with or without 16104477Ssam * modification, are permitted provided that the following conditions 17104477Ssam * are met: 18104477Ssam * 19104477Ssam * 1. Redistributions of source code must retain the above copyright 20104477Ssam * notice, this list of conditions and the following disclaimer. 21104477Ssam * 2. Redistributions in binary form must reproduce the above copyright 22104477Ssam * notice, this list of conditions and the following disclaimer in the 23104477Ssam * documentation and/or other materials provided with the distribution. 24104477Ssam * 3. The name of the author may not be used to endorse or promote products 25104477Ssam * derived from this software without specific prior written permission. 26104477Ssam * 27104477Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28104477Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29104477Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30104477Ssam * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31104477Ssam * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32104477Ssam * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33104477Ssam * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34104477Ssam * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35104477Ssam * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36104477Ssam * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37104477Ssam * 38104477Ssam * Effort sponsored in part by the Defense Advanced Research Projects 39104477Ssam * Agency (DARPA) and Air Force Research Laboratory, Air Force 40104477Ssam * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41104477Ssam */ 42104477Ssam 43119418Sobrien#include <sys/cdefs.h> 44119418Sobrien__FBSDID("$FreeBSD$"); 45119418Sobrien 46104477Ssam/* 47120915Ssam * Driver for various Hifn encryption processors. 48104477Ssam */ 49112124Ssam#include "opt_hifn.h" 50104477Ssam 51104477Ssam#include <sys/param.h> 52104477Ssam#include <sys/systm.h> 53104477Ssam#include <sys/proc.h> 54104477Ssam#include <sys/errno.h> 55104477Ssam#include <sys/malloc.h> 56104477Ssam#include <sys/kernel.h> 57129879Sphk#include <sys/module.h> 58104477Ssam#include <sys/mbuf.h> 59104477Ssam#include <sys/lock.h> 60104477Ssam#include <sys/mutex.h> 61104477Ssam#include <sys/sysctl.h> 62104477Ssam 63104477Ssam#include <vm/vm.h> 64104477Ssam#include <vm/pmap.h> 65104477Ssam 66104477Ssam#include <machine/bus.h> 67104477Ssam#include <machine/resource.h> 68104477Ssam#include <sys/bus.h> 69104477Ssam#include <sys/rman.h> 70104477Ssam 71104477Ssam#include <opencrypto/cryptodev.h> 72104477Ssam#include <sys/random.h> 73167755Ssam#include <sys/kobj.h> 74104477Ssam 75167755Ssam#include "cryptodev_if.h" 76167755Ssam 77119280Simp#include <dev/pci/pcivar.h> 78119280Simp#include <dev/pci/pcireg.h> 79112124Ssam 80112124Ssam#ifdef HIFN_RNDTEST 81112124Ssam#include <dev/rndtest/rndtest.h> 82112124Ssam#endif 83104477Ssam#include <dev/hifn/hifn7751reg.h> 84104477Ssam#include <dev/hifn/hifn7751var.h> 85104477Ssam 86167755Ssam#ifdef HIFN_VULCANDEV 87167755Ssam#include <sys/conf.h> 88167755Ssam#include <sys/uio.h> 89167755Ssam 90167755Ssamstatic struct cdevsw vulcanpk_cdevsw; /* forward declaration */ 91167755Ssam#endif 92167755Ssam 93104477Ssam/* 94104477Ssam * Prototypes and count for the pci_device structure 95104477Ssam */ 96104477Ssamstatic int hifn_probe(device_t); 97104477Ssamstatic int hifn_attach(device_t); 98104477Ssamstatic int hifn_detach(device_t); 99104477Ssamstatic int hifn_suspend(device_t); 100104477Ssamstatic int hifn_resume(device_t); 101188178Simpstatic int hifn_shutdown(device_t); 102104477Ssam 103167755Ssamstatic int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); 104167755Ssamstatic int hifn_freesession(device_t, u_int64_t); 105167755Ssamstatic int hifn_process(device_t, struct cryptop *, int); 106167755Ssam 107104477Ssamstatic device_method_t hifn_methods[] = { 108104477Ssam /* Device interface */ 109104477Ssam DEVMETHOD(device_probe, hifn_probe), 110104477Ssam DEVMETHOD(device_attach, hifn_attach), 111104477Ssam DEVMETHOD(device_detach, hifn_detach), 112104477Ssam DEVMETHOD(device_suspend, hifn_suspend), 113104477Ssam DEVMETHOD(device_resume, hifn_resume), 114104477Ssam DEVMETHOD(device_shutdown, hifn_shutdown), 115104477Ssam 116167755Ssam /* crypto device methods */ 117167755Ssam DEVMETHOD(cryptodev_newsession, hifn_newsession), 118167755Ssam DEVMETHOD(cryptodev_freesession,hifn_freesession), 119167755Ssam DEVMETHOD(cryptodev_process, hifn_process), 120167755Ssam 121227843Smarius DEVMETHOD_END 122104477Ssam}; 123104477Ssamstatic driver_t hifn_driver = { 124104477Ssam "hifn", 125104477Ssam hifn_methods, 126104477Ssam sizeof (struct hifn_softc) 127104477Ssam}; 128104477Ssamstatic devclass_t hifn_devclass; 129104477Ssam 130104477SsamDRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 131105251SmarkmMODULE_DEPEND(hifn, crypto, 1, 1, 1); 132112124Ssam#ifdef HIFN_RNDTEST 133112124SsamMODULE_DEPEND(hifn, rndtest, 1, 1, 1); 134112124Ssam#endif 135104477Ssam 136104477Ssamstatic void hifn_reset_board(struct hifn_softc *, int); 137104477Ssamstatic void hifn_reset_puc(struct hifn_softc *); 138104477Ssamstatic void hifn_puc_wait(struct hifn_softc *); 139104477Ssamstatic int hifn_enable_crypto(struct hifn_softc *); 140104477Ssamstatic void hifn_set_retry(struct hifn_softc *sc); 141104477Ssamstatic void hifn_init_dma(struct hifn_softc *); 142104477Ssamstatic void hifn_init_pci_registers(struct hifn_softc *); 143104477Ssamstatic int hifn_sramsize(struct hifn_softc *); 144104477Ssamstatic int hifn_dramsize(struct hifn_softc *); 145104477Ssamstatic int hifn_ramtype(struct hifn_softc *); 146104477Ssamstatic void hifn_sessions(struct hifn_softc *); 147104477Ssamstatic void hifn_intr(void *); 148104477Ssamstatic u_int hifn_write_command(struct hifn_command *, u_int8_t *); 149104477Ssamstatic u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 150104477Ssamstatic void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 151104477Ssamstatic int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 152104477Ssamstatic int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 153104477Ssamstatic int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 154104477Ssamstatic int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 155104477Ssamstatic int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 156104477Ssamstatic int hifn_init_pubrng(struct hifn_softc *); 157104477Ssamstatic void hifn_rng(void *); 158104477Ssamstatic void hifn_tick(void *); 159104477Ssamstatic void hifn_abort(struct hifn_softc *); 160104477Ssamstatic void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 161104477Ssam 162104477Ssamstatic void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 163104477Ssamstatic void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 164104477Ssam 165131575Sstefanfstatic __inline u_int32_t 166104477SsamREAD_REG_0(struct hifn_softc *sc, bus_size_t reg) 167104477Ssam{ 168104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 169104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 170104477Ssam return (v); 171104477Ssam} 172104477Ssam#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 173104477Ssam 174131575Sstefanfstatic __inline u_int32_t 175104477SsamREAD_REG_1(struct hifn_softc *sc, bus_size_t reg) 176104477Ssam{ 177104477Ssam u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 178104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 179104477Ssam return (v); 180104477Ssam} 181104477Ssam#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 182104477Ssam 183227309Sedstatic SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, 184227309Sed "Hifn driver parameters"); 185109596Ssam 186104477Ssam#ifdef HIFN_DEBUG 187104477Ssamstatic int hifn_debug = 0; 188109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 189109596Ssam 0, "control debugging msgs"); 190104477Ssam#endif 191104477Ssam 192104477Ssamstatic struct hifn_stats hifnstats; 193109596SsamSYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 194109596Ssam hifn_stats, "driver statistics"); 195112121Ssamstatic int hifn_maxbatch = 1; 196109596SsamSYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 197109596Ssam 0, "max ops to batch w/o interrupt"); 198104477Ssam 199104477Ssam/* 200104477Ssam * Probe for a supported device. The PCI vendor and device 201104477Ssam * IDs are used to detect devices we know how to handle. 202104477Ssam */ 203104477Ssamstatic int 204104477Ssamhifn_probe(device_t dev) 205104477Ssam{ 206104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 207104477Ssam pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 208143161Simp return (BUS_PROBE_DEFAULT); 209104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 210104477Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 211104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 212120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 213120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 || 214104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 215143161Simp return (BUS_PROBE_DEFAULT); 216104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 217104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 218143161Simp return (BUS_PROBE_DEFAULT); 219104477Ssam return (ENXIO); 220104477Ssam} 221104477Ssam 222104477Ssamstatic void 223104477Ssamhifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 224104477Ssam{ 225104477Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 226104477Ssam *paddr = segs->ds_addr; 227104477Ssam} 228104477Ssam 229104477Ssamstatic const char* 230104477Ssamhifn_partname(struct hifn_softc *sc) 231104477Ssam{ 232104477Ssam /* XXX sprintf numbers when not decoded */ 233104477Ssam switch (pci_get_vendor(sc->sc_dev)) { 234104477Ssam case PCI_VENDOR_HIFN: 235104477Ssam switch (pci_get_device(sc->sc_dev)) { 236104477Ssam case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 237104477Ssam case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 238104477Ssam case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 239104477Ssam case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 240120915Ssam case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; 241120915Ssam case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; 242104477Ssam } 243104477Ssam return "Hifn unknown-part"; 244104477Ssam case PCI_VENDOR_INVERTEX: 245104477Ssam switch (pci_get_device(sc->sc_dev)) { 246104477Ssam case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 247104477Ssam } 248104477Ssam return "Invertex unknown-part"; 249104477Ssam case PCI_VENDOR_NETSEC: 250104477Ssam switch (pci_get_device(sc->sc_dev)) { 251104477Ssam case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 252104477Ssam } 253104477Ssam return "NetSec unknown-part"; 254104477Ssam } 255104477Ssam return "Unknown-vendor unknown-part"; 256104477Ssam} 257104477Ssam 258112124Ssamstatic void 259112124Ssamdefault_harvest(struct rndtest_state *rsp, void *buf, u_int count) 260112124Ssam{ 261284959Smarkm /* MarkM: FIX!! Check that this does not swamp the harvester! */ 262284959Smarkm random_harvest_queue(buf, count, count*NBBY/2, RANDOM_PURE_HIFN); 263112124Ssam} 264112124Ssam 265140480Ssamstatic u_int 266140480Ssamcheckmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max) 267140480Ssam{ 268140480Ssam if (v > max) { 269140480Ssam device_printf(dev, "Warning, %s %u out of range, " 270140480Ssam "using max %u\n", what, v, max); 271140480Ssam v = max; 272140480Ssam } else if (v < min) { 273140480Ssam device_printf(dev, "Warning, %s %u out of range, " 274140480Ssam "using min %u\n", what, v, min); 275140480Ssam v = min; 276140480Ssam } 277140480Ssam return v; 278140480Ssam} 279140480Ssam 280104477Ssam/* 281140480Ssam * Select PLL configuration for 795x parts. This is complicated in 282140480Ssam * that we cannot determine the optimal parameters without user input. 283140480Ssam * The reference clock is derived from an external clock through a 284140480Ssam * multiplier. The external clock is either the host bus (i.e. PCI) 285140480Ssam * or an external clock generator. When using the PCI bus we assume 286140480Ssam * the clock is either 33 or 66 MHz; for an external source we cannot 287140480Ssam * tell the speed. 288140480Ssam * 289140480Ssam * PLL configuration is done with a string: "pci" for PCI bus, or "ext" 290140480Ssam * for an external source, followed by the frequency. We calculate 291140480Ssam * the appropriate multiplier and PLL register contents accordingly. 292140480Ssam * When no configuration is given we default to "pci66" since that 293140480Ssam * always will allow the card to work. If a card is using the PCI 294140480Ssam * bus clock and in a 33MHz slot then it will be operating at half 295140480Ssam * speed until the correct information is provided. 296167755Ssam * 297167755Ssam * We use a default setting of "ext66" because according to Mike Ham 298167755Ssam * of HiFn, almost every board in existence has an external crystal 299167755Ssam * populated at 66Mhz. Using PCI can be a problem on modern motherboards, 300167755Ssam * because PCI33 can have clocks from 0 to 33Mhz, and some have 301167755Ssam * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. 302140480Ssam */ 303140480Ssamstatic void 304140480Ssamhifn_getpllconfig(device_t dev, u_int *pll) 305140480Ssam{ 306140480Ssam const char *pllspec; 307140480Ssam u_int freq, mul, fl, fh; 308140480Ssam u_int32_t pllconfig; 309140480Ssam char *nxt; 310140480Ssam 311140480Ssam if (resource_string_value("hifn", device_get_unit(dev), 312140480Ssam "pllconfig", &pllspec)) 313167755Ssam pllspec = "ext66"; 314140480Ssam fl = 33, fh = 66; 315140480Ssam pllconfig = 0; 316140480Ssam if (strncmp(pllspec, "ext", 3) == 0) { 317140480Ssam pllspec += 3; 318140480Ssam pllconfig |= HIFN_PLL_REF_SEL; 319140480Ssam switch (pci_get_device(dev)) { 320140480Ssam case PCI_PRODUCT_HIFN_7955: 321140480Ssam case PCI_PRODUCT_HIFN_7956: 322140480Ssam fl = 20, fh = 100; 323140480Ssam break; 324140480Ssam#ifdef notyet 325140480Ssam case PCI_PRODUCT_HIFN_7954: 326140480Ssam fl = 20, fh = 66; 327140480Ssam break; 328140480Ssam#endif 329140480Ssam } 330140480Ssam } else if (strncmp(pllspec, "pci", 3) == 0) 331140480Ssam pllspec += 3; 332140480Ssam freq = strtoul(pllspec, &nxt, 10); 333140480Ssam if (nxt == pllspec) 334140480Ssam freq = 66; 335140480Ssam else 336140480Ssam freq = checkmaxmin(dev, "frequency", freq, fl, fh); 337140480Ssam /* 338140480Ssam * Calculate multiplier. We target a Fck of 266 MHz, 339140480Ssam * allowing only even values, possibly rounded down. 340140480Ssam * Multipliers > 8 must set the charge pump current. 341140480Ssam */ 342140480Ssam mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); 343140480Ssam pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; 344140480Ssam if (mul > 8) 345140480Ssam pllconfig |= HIFN_PLL_IS; 346140480Ssam *pll = pllconfig; 347140480Ssam} 348140480Ssam 349140480Ssam/* 350104477Ssam * Attach an interface that successfully probed. 351104477Ssam */ 352104477Ssamstatic int 353104477Ssamhifn_attach(device_t dev) 354104477Ssam{ 355104477Ssam struct hifn_softc *sc = device_get_softc(dev); 356104477Ssam caddr_t kva; 357104477Ssam int rseg, rid; 358104477Ssam char rbase; 359104477Ssam u_int16_t ena, rev; 360104477Ssam 361104477Ssam sc->sc_dev = dev; 362104477Ssam 363115748Ssam mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF); 364104477Ssam 365104477Ssam /* XXX handle power management */ 366104477Ssam 367104477Ssam /* 368120915Ssam * The 7951 and 795x have a random number generator and 369104477Ssam * public key support; note this. 370104477Ssam */ 371104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 372120915Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 373120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 374120915Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) 375104477Ssam sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 376104477Ssam /* 377104477Ssam * The 7811 has a random number generator and 378104477Ssam * we also note it's identity 'cuz of some quirks. 379104477Ssam */ 380104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 381104477Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 382104477Ssam sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 383104477Ssam 384104477Ssam /* 385120915Ssam * The 795x parts support AES. 386120915Ssam */ 387120915Ssam if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 388120915Ssam (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 389140480Ssam pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { 390120915Ssam sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; 391140480Ssam /* 392140480Ssam * Select PLL configuration. This depends on the 393140480Ssam * bus and board design and must be manually configured 394140480Ssam * if the default setting is unacceptable. 395140480Ssam */ 396140480Ssam hifn_getpllconfig(dev, &sc->sc_pllconfig); 397140480Ssam } 398120915Ssam 399120915Ssam /* 400104477Ssam * Setup PCI resources. Note that we record the bus 401104477Ssam * tag and handle for each register mapping, this is 402104477Ssam * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 403104477Ssam * and WRITE_REG_1 macros throughout the driver. 404104477Ssam */ 405216519Stijl pci_enable_busmaster(dev); 406216519Stijl 407104477Ssam rid = HIFN_BAR0; 408127135Snjl sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 409127135Snjl RF_ACTIVE); 410104477Ssam if (sc->sc_bar0res == NULL) { 411104477Ssam device_printf(dev, "cannot map bar%d register space\n", 0); 412104477Ssam goto fail_pci; 413104477Ssam } 414104477Ssam sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 415104477Ssam sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 416104477Ssam sc->sc_bar0_lastreg = (bus_size_t) -1; 417104477Ssam 418104477Ssam rid = HIFN_BAR1; 419127135Snjl sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 420127135Snjl RF_ACTIVE); 421104477Ssam if (sc->sc_bar1res == NULL) { 422104477Ssam device_printf(dev, "cannot map bar%d register space\n", 1); 423104477Ssam goto fail_io0; 424104477Ssam } 425104477Ssam sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 426104477Ssam sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 427104477Ssam sc->sc_bar1_lastreg = (bus_size_t) -1; 428104477Ssam 429104477Ssam hifn_set_retry(sc); 430104477Ssam 431104477Ssam /* 432104477Ssam * Setup the area where the Hifn DMA's descriptors 433104477Ssam * and associated data structures. 434104477Ssam */ 435232854Sscottl if (bus_dma_tag_create(bus_get_dma_tag(dev), /* PCI parent */ 436104477Ssam 1, 0, /* alignment,boundary */ 437104477Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 438104477Ssam BUS_SPACE_MAXADDR, /* highaddr */ 439104477Ssam NULL, NULL, /* filter, filterarg */ 440104477Ssam HIFN_MAX_DMALEN, /* maxsize */ 441104477Ssam MAX_SCATTER, /* nsegments */ 442104477Ssam HIFN_MAX_SEGLEN, /* maxsegsize */ 443104477Ssam BUS_DMA_ALLOCNOW, /* flags */ 444117126Sscottl NULL, /* lockfunc */ 445117126Sscottl NULL, /* lockarg */ 446104477Ssam &sc->sc_dmat)) { 447104477Ssam device_printf(dev, "cannot allocate DMA tag\n"); 448104477Ssam goto fail_io1; 449104477Ssam } 450104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 451104477Ssam device_printf(dev, "cannot create dma map\n"); 452104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 453104477Ssam goto fail_io1; 454104477Ssam } 455104477Ssam if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 456104477Ssam device_printf(dev, "cannot alloc dma buffer\n"); 457104477Ssam bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 458104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 459104477Ssam goto fail_io1; 460104477Ssam } 461104477Ssam if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 462104477Ssam sizeof (*sc->sc_dma), 463104477Ssam hifn_dmamap_cb, &sc->sc_dma_physaddr, 464104477Ssam BUS_DMA_NOWAIT)) { 465104477Ssam device_printf(dev, "cannot load dma map\n"); 466104477Ssam bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 467104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 468104477Ssam goto fail_io1; 469104477Ssam } 470104477Ssam sc->sc_dma = (struct hifn_dma *)kva; 471104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 472104477Ssam 473123824Ssam KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!")); 474123824Ssam KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!")); 475123824Ssam KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!")); 476123824Ssam KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!")); 477104477Ssam 478104477Ssam /* 479104477Ssam * Reset the board and do the ``secret handshake'' 480104477Ssam * to enable the crypto support. Then complete the 481104477Ssam * initialization procedure by setting up the interrupt 482104477Ssam * and hooking in to the system crypto support so we'll 483104477Ssam * get used for system services like the crypto device, 484104477Ssam * IPsec, RNG device, etc. 485104477Ssam */ 486104477Ssam hifn_reset_board(sc, 0); 487104477Ssam 488104477Ssam if (hifn_enable_crypto(sc) != 0) { 489104477Ssam device_printf(dev, "crypto enabling failed\n"); 490104477Ssam goto fail_mem; 491104477Ssam } 492104477Ssam hifn_reset_puc(sc); 493104477Ssam 494104477Ssam hifn_init_dma(sc); 495104477Ssam hifn_init_pci_registers(sc); 496104477Ssam 497120915Ssam /* XXX can't dynamically determine ram type for 795x; force dram */ 498120915Ssam if (sc->sc_flags & HIFN_IS_7956) 499120915Ssam sc->sc_drammodel = 1; 500120915Ssam else if (hifn_ramtype(sc)) 501104477Ssam goto fail_mem; 502104477Ssam 503104477Ssam if (sc->sc_drammodel == 0) 504104477Ssam hifn_sramsize(sc); 505104477Ssam else 506104477Ssam hifn_dramsize(sc); 507104477Ssam 508104477Ssam /* 509104477Ssam * Workaround for NetSec 7751 rev A: half ram size because two 510104477Ssam * of the address lines were left floating 511104477Ssam */ 512104477Ssam if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 513104477Ssam pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 514104477Ssam pci_get_revid(dev) == 0x61) /*XXX???*/ 515104477Ssam sc->sc_ramsize >>= 1; 516104477Ssam 517104477Ssam /* 518104477Ssam * Arrange the interrupt line. 519104477Ssam */ 520104477Ssam rid = 0; 521127135Snjl sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 522127135Snjl RF_SHAREABLE|RF_ACTIVE); 523104477Ssam if (sc->sc_irq == NULL) { 524104477Ssam device_printf(dev, "could not map interrupt\n"); 525104477Ssam goto fail_mem; 526104477Ssam } 527104477Ssam /* 528104477Ssam * NB: Network code assumes we are blocked with splimp() 529104477Ssam * so make sure the IRQ is marked appropriately. 530104477Ssam */ 531115748Ssam if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 532166901Spiso NULL, hifn_intr, sc, &sc->sc_intrhand)) { 533104477Ssam device_printf(dev, "could not setup interrupt\n"); 534104477Ssam goto fail_intr2; 535104477Ssam } 536104477Ssam 537104477Ssam hifn_sessions(sc); 538104477Ssam 539104477Ssam /* 540104477Ssam * NB: Keep only the low 16 bits; this masks the chip id 541104477Ssam * from the 7951. 542104477Ssam */ 543104477Ssam rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 544104477Ssam 545104477Ssam rseg = sc->sc_ramsize / 1024; 546104477Ssam rbase = 'K'; 547104477Ssam if (sc->sc_ramsize >= (1024 * 1024)) { 548104477Ssam rbase = 'M'; 549104477Ssam rseg /= 1024; 550104477Ssam } 551140480Ssam device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", 552104477Ssam hifn_partname(sc), rev, 553136526Ssam rseg, rbase, sc->sc_drammodel ? 'd' : 's'); 554140480Ssam if (sc->sc_flags & HIFN_IS_7956) 555140480Ssam printf(", pll=0x%x<%s clk, %ux mult>", 556140480Ssam sc->sc_pllconfig, 557140480Ssam sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", 558140480Ssam 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); 559140480Ssam printf("\n"); 560104477Ssam 561167755Ssam sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 562104477Ssam if (sc->sc_cid < 0) { 563104477Ssam device_printf(dev, "could not get crypto driver id\n"); 564104477Ssam goto fail_intr; 565104477Ssam } 566104477Ssam 567104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, 568104477Ssam READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 569104477Ssam ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 570104477Ssam 571104477Ssam switch (ena) { 572104477Ssam case HIFN_PUSTAT_ENA_2: 573167755Ssam crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 574167755Ssam crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); 575120915Ssam if (sc->sc_flags & HIFN_HAS_AES) 576167755Ssam crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); 577104477Ssam /*FALLTHROUGH*/ 578104477Ssam case HIFN_PUSTAT_ENA_1: 579167755Ssam crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); 580167755Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); 581167755Ssam crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 582167755Ssam crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 583167755Ssam crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 584104477Ssam break; 585104477Ssam } 586104477Ssam 587104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 588104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 589104477Ssam 590104477Ssam if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 591104477Ssam hifn_init_pubrng(sc); 592104477Ssam 593283291Sjkim callout_init(&sc->sc_tickto, 1); 594104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 595104477Ssam 596104477Ssam return (0); 597104477Ssam 598104477Ssamfail_intr: 599104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 600104477Ssamfail_intr2: 601104477Ssam /* XXX don't store rid */ 602104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 603104477Ssamfail_mem: 604104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 605104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 606104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 607104477Ssam 608104477Ssam /* Turn off DMA polling */ 609104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 610104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 611104477Ssamfail_io1: 612104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 613104477Ssamfail_io0: 614104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 615104477Ssamfail_pci: 616104477Ssam mtx_destroy(&sc->sc_mtx); 617104477Ssam return (ENXIO); 618104477Ssam} 619104477Ssam 620104477Ssam/* 621104477Ssam * Detach an interface that successfully probed. 622104477Ssam */ 623104477Ssamstatic int 624104477Ssamhifn_detach(device_t dev) 625104477Ssam{ 626104477Ssam struct hifn_softc *sc = device_get_softc(dev); 627104477Ssam 628104477Ssam KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 629104477Ssam 630115748Ssam /* disable interrupts */ 631115748Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); 632104477Ssam 633104477Ssam /*XXX other resources */ 634104477Ssam callout_stop(&sc->sc_tickto); 635104477Ssam callout_stop(&sc->sc_rngto); 636115848Ssam#ifdef HIFN_RNDTEST 637115848Ssam if (sc->sc_rndtest) 638115862Ssam rndtest_detach(sc->sc_rndtest); 639115848Ssam#endif 640104477Ssam 641104477Ssam /* Turn off DMA polling */ 642104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 643104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 644104477Ssam 645104477Ssam crypto_unregister_all(sc->sc_cid); 646104477Ssam 647104477Ssam bus_generic_detach(dev); /*XXX should be no children, right? */ 648104477Ssam 649104477Ssam bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 650104477Ssam /* XXX don't store rid */ 651104477Ssam bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 652104477Ssam 653104477Ssam bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 654104477Ssam bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 655104477Ssam bus_dma_tag_destroy(sc->sc_dmat); 656104477Ssam 657104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 658104477Ssam bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 659104477Ssam 660104477Ssam mtx_destroy(&sc->sc_mtx); 661104477Ssam 662104477Ssam return (0); 663104477Ssam} 664104477Ssam 665104477Ssam/* 666104477Ssam * Stop all chip I/O so that the kernel's probe routines don't 667104477Ssam * get confused by errant DMAs when rebooting. 668104477Ssam */ 669188178Simpstatic int 670104477Ssamhifn_shutdown(device_t dev) 671104477Ssam{ 672104477Ssam#ifdef notyet 673104477Ssam hifn_stop(device_get_softc(dev)); 674104477Ssam#endif 675188178Simp return (0); 676104477Ssam} 677104477Ssam 678104477Ssam/* 679104477Ssam * Device suspend routine. Stop the interface and save some PCI 680104477Ssam * settings in case the BIOS doesn't restore them properly on 681104477Ssam * resume. 682104477Ssam */ 683104477Ssamstatic int 684104477Ssamhifn_suspend(device_t dev) 685104477Ssam{ 686104477Ssam struct hifn_softc *sc = device_get_softc(dev); 687104477Ssam#ifdef notyet 688104477Ssam hifn_stop(sc); 689104477Ssam#endif 690104477Ssam sc->sc_suspended = 1; 691104477Ssam 692104477Ssam return (0); 693104477Ssam} 694104477Ssam 695104477Ssam/* 696104477Ssam * Device resume routine. Restore some PCI settings in case the BIOS 697104477Ssam * doesn't, re-enable busmastering, and restart the interface if 698104477Ssam * appropriate. 699104477Ssam */ 700104477Ssamstatic int 701104477Ssamhifn_resume(device_t dev) 702104477Ssam{ 703104477Ssam struct hifn_softc *sc = device_get_softc(dev); 704104477Ssam#ifdef notyet 705104477Ssam /* reinitialize interface if necessary */ 706104477Ssam if (ifp->if_flags & IFF_UP) 707104477Ssam rl_init(sc); 708104477Ssam#endif 709104477Ssam sc->sc_suspended = 0; 710104477Ssam 711104477Ssam return (0); 712104477Ssam} 713104477Ssam 714104477Ssamstatic int 715104477Ssamhifn_init_pubrng(struct hifn_softc *sc) 716104477Ssam{ 717104477Ssam u_int32_t r; 718104477Ssam int i; 719104477Ssam 720112124Ssam#ifdef HIFN_RNDTEST 721112124Ssam sc->sc_rndtest = rndtest_attach(sc->sc_dev); 722112124Ssam if (sc->sc_rndtest) 723112124Ssam sc->sc_harvest = rndtest_harvest; 724112124Ssam else 725112124Ssam sc->sc_harvest = default_harvest; 726112124Ssam#else 727112124Ssam sc->sc_harvest = default_harvest; 728112124Ssam#endif 729104477Ssam if ((sc->sc_flags & HIFN_IS_7811) == 0) { 730104477Ssam /* Reset 7951 public key/rng engine */ 731104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_RESET, 732104477Ssam READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 733104477Ssam 734104477Ssam for (i = 0; i < 100; i++) { 735104477Ssam DELAY(1000); 736104477Ssam if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 737104477Ssam HIFN_PUBRST_RESET) == 0) 738104477Ssam break; 739104477Ssam } 740104477Ssam 741104477Ssam if (i == 100) { 742104477Ssam device_printf(sc->sc_dev, "public key init failed\n"); 743104477Ssam return (1); 744104477Ssam } 745104477Ssam } 746104477Ssam 747104477Ssam /* Enable the rng, if available */ 748104477Ssam if (sc->sc_flags & HIFN_HAS_RNG) { 749104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 750104477Ssam r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 751104477Ssam if (r & HIFN_7811_RNGENA_ENA) { 752104477Ssam r &= ~HIFN_7811_RNGENA_ENA; 753104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 754104477Ssam } 755104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 756104477Ssam HIFN_7811_RNGCFG_DEFL); 757104477Ssam r |= HIFN_7811_RNGENA_ENA; 758104477Ssam WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 759104477Ssam } else 760104477Ssam WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 761104477Ssam READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 762104477Ssam HIFN_RNGCFG_ENA); 763104477Ssam 764104477Ssam sc->sc_rngfirst = 1; 765104477Ssam if (hz >= 100) 766104477Ssam sc->sc_rnghz = hz / 100; 767104477Ssam else 768104477Ssam sc->sc_rnghz = 1; 769283291Sjkim callout_init(&sc->sc_rngto, 1); 770104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 771104477Ssam } 772104477Ssam 773104477Ssam /* Enable public key engine, if available */ 774104477Ssam if (sc->sc_flags & HIFN_HAS_PUBLIC) { 775104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 776104477Ssam sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 777104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 778167755Ssam#ifdef HIFN_VULCANDEV 779167755Ssam sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, 780167755Ssam UID_ROOT, GID_WHEEL, 0666, 781167755Ssam "vulcanpk"); 782167755Ssam sc->sc_pkdev->si_drv1 = sc; 783167755Ssam#endif 784104477Ssam } 785104477Ssam 786104477Ssam return (0); 787104477Ssam} 788104477Ssam 789104477Ssamstatic void 790104477Ssamhifn_rng(void *vsc) 791104477Ssam{ 792104477Ssam#define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 793104477Ssam struct hifn_softc *sc = vsc; 794104477Ssam u_int32_t sts, num[2]; 795104477Ssam int i; 796104477Ssam 797104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 798167755Ssam /* ONLY VALID ON 7811!!!! */ 799104477Ssam for (i = 0; i < 5; i++) { 800104477Ssam sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 801104477Ssam if (sts & HIFN_7811_RNGSTS_UFL) { 802104477Ssam device_printf(sc->sc_dev, 803104477Ssam "RNG underflow: disabling\n"); 804104477Ssam return; 805104477Ssam } 806104477Ssam if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 807104477Ssam break; 808104477Ssam 809104477Ssam /* 810104477Ssam * There are at least two words in the RNG FIFO 811104477Ssam * at this point. 812104477Ssam */ 813104477Ssam num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 814104477Ssam num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 815104477Ssam /* NB: discard first data read */ 816104477Ssam if (sc->sc_rngfirst) 817104477Ssam sc->sc_rngfirst = 0; 818104477Ssam else 819112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 820112124Ssam num, sizeof (num)); 821104477Ssam } 822104477Ssam } else { 823104477Ssam num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 824104477Ssam 825104477Ssam /* NB: discard first data read */ 826104477Ssam if (sc->sc_rngfirst) 827104477Ssam sc->sc_rngfirst = 0; 828104477Ssam else 829112124Ssam (*sc->sc_harvest)(sc->sc_rndtest, 830112124Ssam num, sizeof (num[0])); 831104477Ssam } 832104477Ssam 833104477Ssam callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 834104477Ssam#undef RANDOM_BITS 835104477Ssam} 836104477Ssam 837104477Ssamstatic void 838104477Ssamhifn_puc_wait(struct hifn_softc *sc) 839104477Ssam{ 840104477Ssam int i; 841167755Ssam int reg = HIFN_0_PUCTRL; 842104477Ssam 843167755Ssam if (sc->sc_flags & HIFN_IS_7956) { 844167755Ssam reg = HIFN_0_PUCTRL2; 845167755Ssam } 846167755Ssam 847104477Ssam for (i = 5000; i > 0; i--) { 848104477Ssam DELAY(1); 849167755Ssam if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) 850104477Ssam break; 851104477Ssam } 852104477Ssam if (!i) 853104477Ssam device_printf(sc->sc_dev, "proc unit did not reset\n"); 854104477Ssam} 855104477Ssam 856104477Ssam/* 857104477Ssam * Reset the processing unit. 858104477Ssam */ 859104477Ssamstatic void 860104477Ssamhifn_reset_puc(struct hifn_softc *sc) 861104477Ssam{ 862104477Ssam /* Reset processing unit */ 863167755Ssam int reg = HIFN_0_PUCTRL; 864167755Ssam 865167755Ssam if (sc->sc_flags & HIFN_IS_7956) { 866167755Ssam reg = HIFN_0_PUCTRL2; 867167755Ssam } 868167755Ssam WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); 869167755Ssam 870104477Ssam hifn_puc_wait(sc); 871104477Ssam} 872104477Ssam 873104477Ssam/* 874104477Ssam * Set the Retry and TRDY registers; note that we set them to 875104477Ssam * zero because the 7811 locks up when forced to retry (section 876104477Ssam * 3.6 of "Specification Update SU-0014-04". Not clear if we 877104477Ssam * should do this for all Hifn parts, but it doesn't seem to hurt. 878104477Ssam */ 879104477Ssamstatic void 880104477Ssamhifn_set_retry(struct hifn_softc *sc) 881104477Ssam{ 882104477Ssam /* NB: RETRY only responds to 8-bit reads/writes */ 883104477Ssam pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 884216519Stijl pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 1); 885104477Ssam} 886104477Ssam 887104477Ssam/* 888104477Ssam * Resets the board. Values in the regesters are left as is 889104477Ssam * from the reset (i.e. initial values are assigned elsewhere). 890104477Ssam */ 891104477Ssamstatic void 892104477Ssamhifn_reset_board(struct hifn_softc *sc, int full) 893104477Ssam{ 894104477Ssam u_int32_t reg; 895104477Ssam 896104477Ssam /* 897104477Ssam * Set polling in the DMA configuration register to zero. 0x7 avoids 898104477Ssam * resetting the board and zeros out the other fields. 899104477Ssam */ 900104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 901104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 902104477Ssam 903104477Ssam /* 904104477Ssam * Now that polling has been disabled, we have to wait 1 ms 905104477Ssam * before resetting the board. 906104477Ssam */ 907104477Ssam DELAY(1000); 908104477Ssam 909104477Ssam /* Reset the DMA unit */ 910104477Ssam if (full) { 911104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 912104477Ssam DELAY(1000); 913104477Ssam } else { 914104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 915104477Ssam HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 916104477Ssam hifn_reset_puc(sc); 917104477Ssam } 918104477Ssam 919104477Ssam KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 920104477Ssam bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 921104477Ssam 922104477Ssam /* Bring dma unit out of reset */ 923104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 924104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 925104477Ssam 926104477Ssam hifn_puc_wait(sc); 927104477Ssam hifn_set_retry(sc); 928104477Ssam 929104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 930104477Ssam for (reg = 0; reg < 1000; reg++) { 931104477Ssam if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 932104477Ssam HIFN_MIPSRST_CRAMINIT) 933104477Ssam break; 934104477Ssam DELAY(1000); 935104477Ssam } 936104477Ssam if (reg == 1000) 937104477Ssam printf(": cram init timeout\n"); 938167755Ssam } else { 939167755Ssam /* set up DMA configuration register #2 */ 940167755Ssam /* turn off all PK and BAR0 swaps */ 941167755Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, 942167755Ssam (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| 943167755Ssam (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| 944167755Ssam (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| 945167755Ssam (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); 946104477Ssam } 947167755Ssam 948104477Ssam} 949104477Ssam 950104477Ssamstatic u_int32_t 951104477Ssamhifn_next_signature(u_int32_t a, u_int cnt) 952104477Ssam{ 953104477Ssam int i; 954104477Ssam u_int32_t v; 955104477Ssam 956104477Ssam for (i = 0; i < cnt; i++) { 957104477Ssam 958104477Ssam /* get the parity */ 959104477Ssam v = a & 0x80080125; 960104477Ssam v ^= v >> 16; 961104477Ssam v ^= v >> 8; 962104477Ssam v ^= v >> 4; 963104477Ssam v ^= v >> 2; 964104477Ssam v ^= v >> 1; 965104477Ssam 966104477Ssam a = (v & 1) ^ (a << 1); 967104477Ssam } 968104477Ssam 969104477Ssam return a; 970104477Ssam} 971104477Ssam 972104477Ssamstruct pci2id { 973104477Ssam u_short pci_vendor; 974104477Ssam u_short pci_prod; 975104477Ssam char card_id[13]; 976104477Ssam}; 977104477Ssamstatic struct pci2id pci2id[] = { 978104477Ssam { 979104477Ssam PCI_VENDOR_HIFN, 980104477Ssam PCI_PRODUCT_HIFN_7951, 981104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 982104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 983104477Ssam }, { 984120915Ssam PCI_VENDOR_HIFN, 985120915Ssam PCI_PRODUCT_HIFN_7955, 986120915Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 987120915Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 988120915Ssam }, { 989120915Ssam PCI_VENDOR_HIFN, 990120915Ssam PCI_PRODUCT_HIFN_7956, 991120915Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 992120915Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 993120915Ssam }, { 994104477Ssam PCI_VENDOR_NETSEC, 995104477Ssam PCI_PRODUCT_NETSEC_7751, 996104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 997104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 998104477Ssam }, { 999104477Ssam PCI_VENDOR_INVERTEX, 1000104477Ssam PCI_PRODUCT_INVERTEX_AEON, 1001104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1002104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1003104477Ssam }, { 1004104477Ssam PCI_VENDOR_HIFN, 1005104477Ssam PCI_PRODUCT_HIFN_7811, 1006104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1007104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1008104477Ssam }, { 1009104477Ssam /* 1010104477Ssam * Other vendors share this PCI ID as well, such as 1011104477Ssam * http://www.powercrypt.com, and obviously they also 1012104477Ssam * use the same key. 1013104477Ssam */ 1014104477Ssam PCI_VENDOR_HIFN, 1015104477Ssam PCI_PRODUCT_HIFN_7751, 1016104477Ssam { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1017104477Ssam 0x00, 0x00, 0x00, 0x00, 0x00 } 1018104477Ssam }, 1019104477Ssam}; 1020104477Ssam 1021104477Ssam/* 1022104477Ssam * Checks to see if crypto is already enabled. If crypto isn't enable, 1023104477Ssam * "hifn_enable_crypto" is called to enable it. The check is important, 1024104477Ssam * as enabling crypto twice will lock the board. 1025104477Ssam */ 1026104477Ssamstatic int 1027104477Ssamhifn_enable_crypto(struct hifn_softc *sc) 1028104477Ssam{ 1029104477Ssam u_int32_t dmacfg, ramcfg, encl, addr, i; 1030104477Ssam char *offtbl = NULL; 1031104477Ssam 1032298307Spfg for (i = 0; i < nitems(pci2id); i++) { 1033104477Ssam if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 1034104477Ssam pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 1035104477Ssam offtbl = pci2id[i].card_id; 1036104477Ssam break; 1037104477Ssam } 1038104477Ssam } 1039104477Ssam if (offtbl == NULL) { 1040104477Ssam device_printf(sc->sc_dev, "Unknown card!\n"); 1041104477Ssam return (1); 1042104477Ssam } 1043104477Ssam 1044104477Ssam ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1045104477Ssam dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 1046104477Ssam 1047104477Ssam /* 1048104477Ssam * The RAM config register's encrypt level bit needs to be set before 1049104477Ssam * every read performed on the encryption level register. 1050104477Ssam */ 1051104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 1052104477Ssam 1053104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 1054104477Ssam 1055104477Ssam /* 1056104477Ssam * Make sure we don't re-unlock. Two unlocks kills chip until the 1057104477Ssam * next reboot. 1058104477Ssam */ 1059104477Ssam if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 1060104477Ssam#ifdef HIFN_DEBUG 1061104477Ssam if (hifn_debug) 1062104477Ssam device_printf(sc->sc_dev, 1063104477Ssam "Strong crypto already enabled!\n"); 1064104477Ssam#endif 1065104477Ssam goto report; 1066104477Ssam } 1067104477Ssam 1068104477Ssam if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 1069104477Ssam#ifdef HIFN_DEBUG 1070104477Ssam if (hifn_debug) 1071104477Ssam device_printf(sc->sc_dev, 1072104477Ssam "Unknown encryption level 0x%x\n", encl); 1073104477Ssam#endif 1074104477Ssam return 1; 1075104477Ssam } 1076104477Ssam 1077104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 1078104477Ssam HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 1079104477Ssam DELAY(1000); 1080104477Ssam addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 1081104477Ssam DELAY(1000); 1082104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 1083104477Ssam DELAY(1000); 1084104477Ssam 1085104477Ssam for (i = 0; i <= 12; i++) { 1086104477Ssam addr = hifn_next_signature(addr, offtbl[i] + 0x101); 1087104477Ssam WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 1088104477Ssam 1089104477Ssam DELAY(1000); 1090104477Ssam } 1091104477Ssam 1092104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 1093104477Ssam encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 1094104477Ssam 1095104477Ssam#ifdef HIFN_DEBUG 1096104477Ssam if (hifn_debug) { 1097104477Ssam if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 1098104477Ssam device_printf(sc->sc_dev, "Engine is permanently " 1099104477Ssam "locked until next system reset!\n"); 1100104477Ssam else 1101104477Ssam device_printf(sc->sc_dev, "Engine enabled " 1102104477Ssam "successfully!\n"); 1103104477Ssam } 1104104477Ssam#endif 1105104477Ssam 1106104477Ssamreport: 1107104477Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 1108104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 1109104477Ssam 1110104477Ssam switch (encl) { 1111104477Ssam case HIFN_PUSTAT_ENA_1: 1112104477Ssam case HIFN_PUSTAT_ENA_2: 1113104477Ssam break; 1114104477Ssam case HIFN_PUSTAT_ENA_0: 1115104477Ssam default: 1116104477Ssam device_printf(sc->sc_dev, "disabled"); 1117104477Ssam break; 1118104477Ssam } 1119104477Ssam 1120104477Ssam return 0; 1121104477Ssam} 1122104477Ssam 1123104477Ssam/* 1124104477Ssam * Give initial values to the registers listed in the "Register Space" 1125104477Ssam * section of the HIFN Software Development reference manual. 1126104477Ssam */ 1127104477Ssamstatic void 1128104477Ssamhifn_init_pci_registers(struct hifn_softc *sc) 1129104477Ssam{ 1130104477Ssam /* write fixed values needed by the Initialization registers */ 1131104477Ssam WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 1132104477Ssam WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 1133104477Ssam WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 1134104477Ssam 1135104477Ssam /* write all 4 ring address registers */ 1136104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 1137104477Ssam offsetof(struct hifn_dma, cmdr[0])); 1138104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 1139104477Ssam offsetof(struct hifn_dma, srcr[0])); 1140104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 1141104477Ssam offsetof(struct hifn_dma, dstr[0])); 1142104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 1143104477Ssam offsetof(struct hifn_dma, resr[0])); 1144104477Ssam 1145104477Ssam DELAY(2000); 1146104477Ssam 1147104477Ssam /* write status register */ 1148104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1149104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1150104477Ssam HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1151104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1152104477Ssam HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1153104477Ssam HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1154104477Ssam HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1155104477Ssam HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1156104477Ssam HIFN_DMACSR_S_WAIT | 1157104477Ssam HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1158104477Ssam HIFN_DMACSR_C_WAIT | 1159104477Ssam HIFN_DMACSR_ENGINE | 1160104477Ssam ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1161104477Ssam HIFN_DMACSR_PUBDONE : 0) | 1162104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1163104477Ssam HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1164104477Ssam 1165104477Ssam sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1166104477Ssam sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1167104477Ssam HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1168104477Ssam HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1169104477Ssam ((sc->sc_flags & HIFN_IS_7811) ? 1170104477Ssam HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1171104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1172104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1173104477Ssam 1174104477Ssam 1175120915Ssam if (sc->sc_flags & HIFN_IS_7956) { 1176140480Ssam u_int32_t pll; 1177140480Ssam 1178120915Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1179120915Ssam HIFN_PUCNFG_TCALLPHASES | 1180120915Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); 1181140480Ssam 1182140480Ssam /* turn off the clocks and insure bypass is set */ 1183140480Ssam pll = READ_REG_1(sc, HIFN_1_PLL); 1184140480Ssam pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) 1185167755Ssam | HIFN_PLL_BP | HIFN_PLL_MBSET; 1186140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1187140480Ssam DELAY(10*1000); /* 10ms */ 1188167755Ssam 1189140480Ssam /* change configuration */ 1190140480Ssam pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; 1191140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1192140480Ssam DELAY(10*1000); /* 10ms */ 1193167755Ssam 1194140480Ssam /* disable bypass */ 1195140480Ssam pll &= ~HIFN_PLL_BP; 1196140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1197140480Ssam /* enable clocks with new configuration */ 1198140480Ssam pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; 1199140480Ssam WRITE_REG_1(sc, HIFN_1_PLL, pll); 1200120915Ssam } else { 1201120915Ssam WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1202120915Ssam HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1203120915Ssam HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1204120915Ssam (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1205120915Ssam } 1206120915Ssam 1207104477Ssam WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1208104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1209104477Ssam HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1210104477Ssam ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1211104477Ssam ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1212104477Ssam} 1213104477Ssam 1214104477Ssam/* 1215104477Ssam * The maximum number of sessions supported by the card 1216104477Ssam * is dependent on the amount of context ram, which 1217104477Ssam * encryption algorithms are enabled, and how compression 1218104477Ssam * is configured. This should be configured before this 1219104477Ssam * routine is called. 1220104477Ssam */ 1221104477Ssamstatic void 1222104477Ssamhifn_sessions(struct hifn_softc *sc) 1223104477Ssam{ 1224104477Ssam u_int32_t pucnfg; 1225104477Ssam int ctxsize; 1226104477Ssam 1227104477Ssam pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1228104477Ssam 1229104477Ssam if (pucnfg & HIFN_PUCNFG_COMPSING) { 1230104477Ssam if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1231104477Ssam ctxsize = 128; 1232104477Ssam else 1233104477Ssam ctxsize = 512; 1234120915Ssam /* 1235120915Ssam * 7955/7956 has internal context memory of 32K 1236120915Ssam */ 1237120915Ssam if (sc->sc_flags & HIFN_IS_7956) 1238120915Ssam sc->sc_maxses = 32768 / ctxsize; 1239120915Ssam else 1240120915Ssam sc->sc_maxses = 1 + 1241120915Ssam ((sc->sc_ramsize - 32768) / ctxsize); 1242104477Ssam } else 1243104477Ssam sc->sc_maxses = sc->sc_ramsize / 16384; 1244104477Ssam 1245104477Ssam if (sc->sc_maxses > 2048) 1246104477Ssam sc->sc_maxses = 2048; 1247104477Ssam} 1248104477Ssam 1249104477Ssam/* 1250104477Ssam * Determine ram type (sram or dram). Board should be just out of a reset 1251104477Ssam * state when this is called. 1252104477Ssam */ 1253104477Ssamstatic int 1254104477Ssamhifn_ramtype(struct hifn_softc *sc) 1255104477Ssam{ 1256104477Ssam u_int8_t data[8], dataexpect[8]; 1257104477Ssam int i; 1258104477Ssam 1259104477Ssam for (i = 0; i < sizeof(data); i++) 1260104477Ssam data[i] = dataexpect[i] = 0x55; 1261104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1262104477Ssam return (-1); 1263104477Ssam if (hifn_readramaddr(sc, 0, data)) 1264104477Ssam return (-1); 1265104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1266104477Ssam sc->sc_drammodel = 1; 1267104477Ssam return (0); 1268104477Ssam } 1269104477Ssam 1270104477Ssam for (i = 0; i < sizeof(data); i++) 1271104477Ssam data[i] = dataexpect[i] = 0xaa; 1272104477Ssam if (hifn_writeramaddr(sc, 0, data)) 1273104477Ssam return (-1); 1274104477Ssam if (hifn_readramaddr(sc, 0, data)) 1275104477Ssam return (-1); 1276104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1277104477Ssam sc->sc_drammodel = 1; 1278104477Ssam return (0); 1279104477Ssam } 1280104477Ssam 1281104477Ssam return (0); 1282104477Ssam} 1283104477Ssam 1284104477Ssam#define HIFN_SRAM_MAX (32 << 20) 1285104477Ssam#define HIFN_SRAM_STEP_SIZE 16384 1286104477Ssam#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1287104477Ssam 1288104477Ssamstatic int 1289104477Ssamhifn_sramsize(struct hifn_softc *sc) 1290104477Ssam{ 1291104477Ssam u_int32_t a; 1292104477Ssam u_int8_t data[8]; 1293104477Ssam u_int8_t dataexpect[sizeof(data)]; 1294104477Ssam int32_t i; 1295104477Ssam 1296104477Ssam for (i = 0; i < sizeof(data); i++) 1297104477Ssam data[i] = dataexpect[i] = i ^ 0x5a; 1298104477Ssam 1299104477Ssam for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1300104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1301104477Ssam bcopy(&i, data, sizeof(i)); 1302104477Ssam hifn_writeramaddr(sc, a, data); 1303104477Ssam } 1304104477Ssam 1305104477Ssam for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1306104477Ssam a = i * HIFN_SRAM_STEP_SIZE; 1307104477Ssam bcopy(&i, dataexpect, sizeof(i)); 1308104477Ssam if (hifn_readramaddr(sc, a, data) < 0) 1309104477Ssam return (0); 1310104477Ssam if (bcmp(data, dataexpect, sizeof(data)) != 0) 1311104477Ssam return (0); 1312104477Ssam sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1313104477Ssam } 1314104477Ssam 1315104477Ssam return (0); 1316104477Ssam} 1317104477Ssam 1318104477Ssam/* 1319104477Ssam * XXX For dram boards, one should really try all of the 1320104477Ssam * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1321104477Ssam * is already set up correctly. 1322104477Ssam */ 1323104477Ssamstatic int 1324104477Ssamhifn_dramsize(struct hifn_softc *sc) 1325104477Ssam{ 1326104477Ssam u_int32_t cnfg; 1327104477Ssam 1328120915Ssam if (sc->sc_flags & HIFN_IS_7956) { 1329120915Ssam /* 1330120915Ssam * 7955/7956 have a fixed internal ram of only 32K. 1331120915Ssam */ 1332120915Ssam sc->sc_ramsize = 32768; 1333120915Ssam } else { 1334120915Ssam cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1335120915Ssam HIFN_PUCNFG_DRAMMASK; 1336120915Ssam sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1337120915Ssam } 1338104477Ssam return (0); 1339104477Ssam} 1340104477Ssam 1341104477Ssamstatic void 1342104477Ssamhifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1343104477Ssam{ 1344104477Ssam struct hifn_dma *dma = sc->sc_dma; 1345104477Ssam 1346213091Sgonzo if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) { 1347213091Sgonzo sc->sc_cmdi = 0; 1348104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1349104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1350104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1351104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1352104477Ssam } 1353213091Sgonzo *cmdp = sc->sc_cmdi++; 1354213091Sgonzo sc->sc_cmdk = sc->sc_cmdi; 1355104477Ssam 1356213091Sgonzo if (sc->sc_srci == HIFN_D_SRC_RSIZE) { 1357213091Sgonzo sc->sc_srci = 0; 1358104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1359104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1360104477Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1361104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1362104477Ssam } 1363213091Sgonzo *srcp = sc->sc_srci++; 1364213091Sgonzo sc->sc_srck = sc->sc_srci; 1365104477Ssam 1366213091Sgonzo if (sc->sc_dsti == HIFN_D_DST_RSIZE) { 1367213091Sgonzo sc->sc_dsti = 0; 1368104477Ssam dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1369104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1370104477Ssam HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1371104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1372104477Ssam } 1373213091Sgonzo *dstp = sc->sc_dsti++; 1374213091Sgonzo sc->sc_dstk = sc->sc_dsti; 1375104477Ssam 1376213091Sgonzo if (sc->sc_resi == HIFN_D_RES_RSIZE) { 1377213091Sgonzo sc->sc_resi = 0; 1378104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1379104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1380104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1381104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1382104477Ssam } 1383213091Sgonzo *resp = sc->sc_resi++; 1384213091Sgonzo sc->sc_resk = sc->sc_resi; 1385104477Ssam} 1386104477Ssam 1387104477Ssamstatic int 1388104477Ssamhifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1389104477Ssam{ 1390104477Ssam struct hifn_dma *dma = sc->sc_dma; 1391104477Ssam hifn_base_command_t wc; 1392104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1393104477Ssam int r, cmdi, resi, srci, dsti; 1394104477Ssam 1395104477Ssam wc.masks = htole16(3 << 13); 1396104477Ssam wc.session_num = htole16(addr >> 14); 1397104477Ssam wc.total_source_count = htole16(8); 1398104477Ssam wc.total_dest_count = htole16(addr & 0x3fff); 1399104477Ssam 1400104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1401104477Ssam 1402104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1403104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1404104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1405104477Ssam 1406104477Ssam /* build write command */ 1407104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1408104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1409104477Ssam bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1410104477Ssam 1411104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1412104477Ssam + offsetof(struct hifn_dma, test_src)); 1413104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1414104477Ssam + offsetof(struct hifn_dma, test_dst)); 1415104477Ssam 1416104477Ssam dma->cmdr[cmdi].l = htole32(16 | masks); 1417104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1418104477Ssam dma->dstr[dsti].l = htole32(4 | masks); 1419104477Ssam dma->resr[resi].l = htole32(4 | masks); 1420104477Ssam 1421104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1422104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1423104477Ssam 1424104477Ssam for (r = 10000; r >= 0; r--) { 1425104477Ssam DELAY(10); 1426104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1427104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1428104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1429104477Ssam break; 1430104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1431104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1432104477Ssam } 1433104477Ssam if (r == 0) { 1434104477Ssam device_printf(sc->sc_dev, "writeramaddr -- " 1435104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1436104477Ssam r = -1; 1437104477Ssam return (-1); 1438104477Ssam } else 1439104477Ssam r = 0; 1440104477Ssam 1441104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1442104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1443104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1444104477Ssam 1445104477Ssam return (r); 1446104477Ssam} 1447104477Ssam 1448104477Ssamstatic int 1449104477Ssamhifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1450104477Ssam{ 1451104477Ssam struct hifn_dma *dma = sc->sc_dma; 1452104477Ssam hifn_base_command_t rc; 1453104477Ssam const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1454104477Ssam int r, cmdi, srci, dsti, resi; 1455104477Ssam 1456104477Ssam rc.masks = htole16(2 << 13); 1457104477Ssam rc.session_num = htole16(addr >> 14); 1458104477Ssam rc.total_source_count = htole16(addr & 0x3fff); 1459104477Ssam rc.total_dest_count = htole16(8); 1460104477Ssam 1461104477Ssam hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1462104477Ssam 1463104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1464104477Ssam HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1465104477Ssam HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1466104477Ssam 1467104477Ssam bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1468104477Ssam *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1469104477Ssam 1470104477Ssam dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1471104477Ssam offsetof(struct hifn_dma, test_src)); 1472104477Ssam dma->test_src = 0; 1473104477Ssam dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1474104477Ssam offsetof(struct hifn_dma, test_dst)); 1475104477Ssam dma->test_dst = 0; 1476104477Ssam dma->cmdr[cmdi].l = htole32(8 | masks); 1477104477Ssam dma->srcr[srci].l = htole32(8 | masks); 1478104477Ssam dma->dstr[dsti].l = htole32(8 | masks); 1479104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1480104477Ssam 1481104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1482104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1483104477Ssam 1484104477Ssam for (r = 10000; r >= 0; r--) { 1485104477Ssam DELAY(10); 1486104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1487104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1488104477Ssam if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1489104477Ssam break; 1490104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1491104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1492104477Ssam } 1493104477Ssam if (r == 0) { 1494104477Ssam device_printf(sc->sc_dev, "readramaddr -- " 1495104477Ssam "result[%d](addr %d) still valid\n", resi, addr); 1496104477Ssam r = -1; 1497104477Ssam } else { 1498104477Ssam r = 0; 1499104477Ssam bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1500104477Ssam } 1501104477Ssam 1502104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1503104477Ssam HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1504104477Ssam HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1505104477Ssam 1506104477Ssam return (r); 1507104477Ssam} 1508104477Ssam 1509104477Ssam/* 1510104477Ssam * Initialize the descriptor rings. 1511104477Ssam */ 1512104477Ssamstatic void 1513104477Ssamhifn_init_dma(struct hifn_softc *sc) 1514104477Ssam{ 1515104477Ssam struct hifn_dma *dma = sc->sc_dma; 1516104477Ssam int i; 1517104477Ssam 1518104477Ssam hifn_set_retry(sc); 1519104477Ssam 1520104477Ssam /* initialize static pointer values */ 1521104477Ssam for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1522104477Ssam dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1523104477Ssam offsetof(struct hifn_dma, command_bufs[i][0])); 1524104477Ssam for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1525104477Ssam dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1526104477Ssam offsetof(struct hifn_dma, result_bufs[i][0])); 1527104477Ssam 1528104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].p = 1529104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1530104477Ssam dma->srcr[HIFN_D_SRC_RSIZE].p = 1531104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1532104477Ssam dma->dstr[HIFN_D_DST_RSIZE].p = 1533104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1534104477Ssam dma->resr[HIFN_D_RES_RSIZE].p = 1535104477Ssam htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1536104477Ssam 1537213091Sgonzo sc->sc_cmdu = sc->sc_srcu = sc->sc_dstu = sc->sc_resu = 0; 1538213091Sgonzo sc->sc_cmdi = sc->sc_srci = sc->sc_dsti = sc->sc_resi = 0; 1539213091Sgonzo sc->sc_cmdk = sc->sc_srck = sc->sc_dstk = sc->sc_resk = 0; 1540104477Ssam} 1541104477Ssam 1542104477Ssam/* 1543104477Ssam * Writes out the raw command buffer space. Returns the 1544104477Ssam * command buffer size. 1545104477Ssam */ 1546104477Ssamstatic u_int 1547104477Ssamhifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1548104477Ssam{ 1549104477Ssam u_int8_t *buf_pos; 1550104477Ssam hifn_base_command_t *base_cmd; 1551104477Ssam hifn_mac_command_t *mac_cmd; 1552104477Ssam hifn_crypt_command_t *cry_cmd; 1553120915Ssam int using_mac, using_crypt, len, ivlen; 1554104477Ssam u_int32_t dlen, slen; 1555104477Ssam 1556104477Ssam buf_pos = buf; 1557104477Ssam using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1558104477Ssam using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1559104477Ssam 1560104477Ssam base_cmd = (hifn_base_command_t *)buf_pos; 1561104477Ssam base_cmd->masks = htole16(cmd->base_masks); 1562104477Ssam slen = cmd->src_mapsize; 1563104477Ssam if (cmd->sloplen) 1564104477Ssam dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1565104477Ssam else 1566104477Ssam dlen = cmd->dst_mapsize; 1567104477Ssam base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1568104477Ssam base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1569104477Ssam dlen >>= 16; 1570104477Ssam slen >>= 16; 1571136526Ssam base_cmd->session_num = htole16( 1572104477Ssam ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1573104477Ssam ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1574104477Ssam buf_pos += sizeof(hifn_base_command_t); 1575104477Ssam 1576104477Ssam if (using_mac) { 1577104477Ssam mac_cmd = (hifn_mac_command_t *)buf_pos; 1578104477Ssam dlen = cmd->maccrd->crd_len; 1579104477Ssam mac_cmd->source_count = htole16(dlen & 0xffff); 1580104477Ssam dlen >>= 16; 1581104477Ssam mac_cmd->masks = htole16(cmd->mac_masks | 1582104477Ssam ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1583104477Ssam mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1584104477Ssam mac_cmd->reserved = 0; 1585104477Ssam buf_pos += sizeof(hifn_mac_command_t); 1586104477Ssam } 1587104477Ssam 1588104477Ssam if (using_crypt) { 1589104477Ssam cry_cmd = (hifn_crypt_command_t *)buf_pos; 1590104477Ssam dlen = cmd->enccrd->crd_len; 1591104477Ssam cry_cmd->source_count = htole16(dlen & 0xffff); 1592104477Ssam dlen >>= 16; 1593104477Ssam cry_cmd->masks = htole16(cmd->cry_masks | 1594104477Ssam ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1595104477Ssam cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1596104477Ssam cry_cmd->reserved = 0; 1597104477Ssam buf_pos += sizeof(hifn_crypt_command_t); 1598104477Ssam } 1599104477Ssam 1600104477Ssam if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1601104477Ssam bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1602104477Ssam buf_pos += HIFN_MAC_KEY_LENGTH; 1603104477Ssam } 1604104477Ssam 1605104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1606104477Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1607104477Ssam case HIFN_CRYPT_CMD_ALG_3DES: 1608104477Ssam bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1609104477Ssam buf_pos += HIFN_3DES_KEY_LENGTH; 1610104477Ssam break; 1611104477Ssam case HIFN_CRYPT_CMD_ALG_DES: 1612104477Ssam bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1613120915Ssam buf_pos += HIFN_DES_KEY_LENGTH; 1614104477Ssam break; 1615104477Ssam case HIFN_CRYPT_CMD_ALG_RC4: 1616104477Ssam len = 256; 1617104477Ssam do { 1618104477Ssam int clen; 1619104477Ssam 1620104477Ssam clen = MIN(cmd->cklen, len); 1621104477Ssam bcopy(cmd->ck, buf_pos, clen); 1622104477Ssam len -= clen; 1623104477Ssam buf_pos += clen; 1624104477Ssam } while (len > 0); 1625104477Ssam bzero(buf_pos, 4); 1626104477Ssam buf_pos += 4; 1627104477Ssam break; 1628120915Ssam case HIFN_CRYPT_CMD_ALG_AES: 1629120915Ssam /* 1630120915Ssam * AES keys are variable 128, 192 and 1631120915Ssam * 256 bits (16, 24 and 32 bytes). 1632120915Ssam */ 1633120915Ssam bcopy(cmd->ck, buf_pos, cmd->cklen); 1634120915Ssam buf_pos += cmd->cklen; 1635120915Ssam break; 1636104477Ssam } 1637104477Ssam } 1638104477Ssam 1639104477Ssam if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1640120915Ssam switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1641120915Ssam case HIFN_CRYPT_CMD_ALG_AES: 1642120915Ssam ivlen = HIFN_AES_IV_LENGTH; 1643120915Ssam break; 1644120915Ssam default: 1645120915Ssam ivlen = HIFN_IV_LENGTH; 1646120915Ssam break; 1647120915Ssam } 1648120915Ssam bcopy(cmd->iv, buf_pos, ivlen); 1649120915Ssam buf_pos += ivlen; 1650104477Ssam } 1651104477Ssam 1652104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1653104477Ssam bzero(buf_pos, 8); 1654104477Ssam buf_pos += 8; 1655104477Ssam } 1656104477Ssam 1657104477Ssam return (buf_pos - buf); 1658104477Ssam} 1659104477Ssam 1660104477Ssamstatic int 1661104477Ssamhifn_dmamap_aligned(struct hifn_operand *op) 1662104477Ssam{ 1663104477Ssam int i; 1664104477Ssam 1665104477Ssam for (i = 0; i < op->nsegs; i++) { 1666104477Ssam if (op->segs[i].ds_addr & 3) 1667104477Ssam return (0); 1668104477Ssam if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1669104477Ssam return (0); 1670104477Ssam } 1671104477Ssam return (1); 1672104477Ssam} 1673104477Ssam 1674167755Ssamstatic __inline int 1675167755Ssamhifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) 1676167755Ssam{ 1677167755Ssam struct hifn_dma *dma = sc->sc_dma; 1678167755Ssam 1679167755Ssam if (++idx == HIFN_D_DST_RSIZE) { 1680167755Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1681167755Ssam HIFN_D_MASKDONEIRQ); 1682167755Ssam HIFN_DSTR_SYNC(sc, idx, 1683167755Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1684167755Ssam idx = 0; 1685167755Ssam } 1686167755Ssam return (idx); 1687167755Ssam} 1688167755Ssam 1689104477Ssamstatic int 1690104477Ssamhifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1691104477Ssam{ 1692104477Ssam struct hifn_dma *dma = sc->sc_dma; 1693104477Ssam struct hifn_operand *dst = &cmd->dst; 1694104477Ssam u_int32_t p, l; 1695104477Ssam int idx, used = 0, i; 1696104477Ssam 1697213091Sgonzo idx = sc->sc_dsti; 1698104477Ssam for (i = 0; i < dst->nsegs - 1; i++) { 1699104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1700104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1701104477Ssam HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1702104477Ssam HIFN_DSTR_SYNC(sc, idx, 1703104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1704104477Ssam used++; 1705104477Ssam 1706167755Ssam idx = hifn_dmamap_dstwrap(sc, idx); 1707104477Ssam } 1708104477Ssam 1709104477Ssam if (cmd->sloplen == 0) { 1710104477Ssam p = dst->segs[i].ds_addr; 1711104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1712104477Ssam dst->segs[i].ds_len; 1713104477Ssam } else { 1714104477Ssam p = sc->sc_dma_physaddr + 1715104477Ssam offsetof(struct hifn_dma, slop[cmd->slopidx]); 1716104477Ssam l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1717104477Ssam sizeof(u_int32_t); 1718104477Ssam 1719104477Ssam if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1720104477Ssam dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1721104477Ssam dma->dstr[idx].l = htole32(HIFN_D_VALID | 1722104477Ssam HIFN_D_MASKDONEIRQ | 1723104477Ssam (dst->segs[i].ds_len - cmd->sloplen)); 1724104477Ssam HIFN_DSTR_SYNC(sc, idx, 1725104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1726104477Ssam used++; 1727104477Ssam 1728167755Ssam idx = hifn_dmamap_dstwrap(sc, idx); 1729104477Ssam } 1730104477Ssam } 1731104477Ssam dma->dstr[idx].p = htole32(p); 1732104477Ssam dma->dstr[idx].l = htole32(l); 1733104477Ssam HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1734104477Ssam used++; 1735104477Ssam 1736167755Ssam idx = hifn_dmamap_dstwrap(sc, idx); 1737104477Ssam 1738213091Sgonzo sc->sc_dsti = idx; 1739213091Sgonzo sc->sc_dstu += used; 1740104477Ssam return (idx); 1741104477Ssam} 1742104477Ssam 1743167755Ssamstatic __inline int 1744167755Ssamhifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) 1745167755Ssam{ 1746167755Ssam struct hifn_dma *dma = sc->sc_dma; 1747167755Ssam 1748167755Ssam if (++idx == HIFN_D_SRC_RSIZE) { 1749167755Ssam dma->srcr[idx].l = htole32(HIFN_D_VALID | 1750167755Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1751167755Ssam HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1752167755Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1753167755Ssam idx = 0; 1754167755Ssam } 1755167755Ssam return (idx); 1756167755Ssam} 1757167755Ssam 1758104477Ssamstatic int 1759104477Ssamhifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1760104477Ssam{ 1761104477Ssam struct hifn_dma *dma = sc->sc_dma; 1762104477Ssam struct hifn_operand *src = &cmd->src; 1763104477Ssam int idx, i; 1764104477Ssam u_int32_t last = 0; 1765104477Ssam 1766213091Sgonzo idx = sc->sc_srci; 1767104477Ssam for (i = 0; i < src->nsegs; i++) { 1768104477Ssam if (i == src->nsegs - 1) 1769104477Ssam last = HIFN_D_LAST; 1770104477Ssam 1771104477Ssam dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1772104477Ssam dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1773104477Ssam HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1774104477Ssam HIFN_SRCR_SYNC(sc, idx, 1775104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1776104477Ssam 1777167755Ssam idx = hifn_dmamap_srcwrap(sc, idx); 1778104477Ssam } 1779213091Sgonzo sc->sc_srci = idx; 1780213091Sgonzo sc->sc_srcu += src->nsegs; 1781104477Ssam return (idx); 1782104477Ssam} 1783104477Ssam 1784104477Ssamstatic void 1785104477Ssamhifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1786104477Ssam{ 1787104477Ssam struct hifn_operand *op = arg; 1788104477Ssam 1789104477Ssam KASSERT(nsegs <= MAX_SCATTER, 1790104477Ssam ("hifn_op_cb: too many DMA segments (%u > %u) " 1791104477Ssam "returned when mapping operand", nsegs, MAX_SCATTER)); 1792104477Ssam op->mapsize = mapsize; 1793104477Ssam op->nsegs = nsegs; 1794104477Ssam bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1795104477Ssam} 1796104477Ssam 1797104477Ssamstatic int 1798104477Ssamhifn_crypto( 1799104477Ssam struct hifn_softc *sc, 1800104477Ssam struct hifn_command *cmd, 1801104477Ssam struct cryptop *crp, 1802104477Ssam int hint) 1803104477Ssam{ 1804104477Ssam struct hifn_dma *dma = sc->sc_dma; 1805167755Ssam u_int32_t cmdlen, csr; 1806104477Ssam int cmdi, resi, err = 0; 1807104477Ssam 1808104477Ssam /* 1809104477Ssam * need 1 cmd, and 1 res 1810104477Ssam * 1811104477Ssam * NB: check this first since it's easy. 1812104477Ssam */ 1813115748Ssam HIFN_LOCK(sc); 1814213091Sgonzo if ((sc->sc_cmdu + 1) > HIFN_D_CMD_RSIZE || 1815213091Sgonzo (sc->sc_resu + 1) > HIFN_D_RES_RSIZE) { 1816104477Ssam#ifdef HIFN_DEBUG 1817104477Ssam if (hifn_debug) { 1818104477Ssam device_printf(sc->sc_dev, 1819104477Ssam "cmd/result exhaustion, cmdu %u resu %u\n", 1820213091Sgonzo sc->sc_cmdu, sc->sc_resu); 1821104477Ssam } 1822104477Ssam#endif 1823104477Ssam hifnstats.hst_nomem_cr++; 1824115748Ssam HIFN_UNLOCK(sc); 1825104477Ssam return (ERESTART); 1826104477Ssam } 1827104477Ssam 1828104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1829104477Ssam hifnstats.hst_nomem_map++; 1830115748Ssam HIFN_UNLOCK(sc); 1831104477Ssam return (ENOMEM); 1832104477Ssam } 1833104477Ssam 1834104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1835104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1836104477Ssam cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1837104477Ssam hifnstats.hst_nomem_load++; 1838104477Ssam err = ENOMEM; 1839104477Ssam goto err_srcmap1; 1840104477Ssam } 1841104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1842104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1843104477Ssam cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1844104477Ssam hifnstats.hst_nomem_load++; 1845104477Ssam err = ENOMEM; 1846104477Ssam goto err_srcmap1; 1847104477Ssam } 1848104477Ssam } else { 1849104477Ssam err = EINVAL; 1850104477Ssam goto err_srcmap1; 1851104477Ssam } 1852104477Ssam 1853104477Ssam if (hifn_dmamap_aligned(&cmd->src)) { 1854104477Ssam cmd->sloplen = cmd->src_mapsize & 3; 1855104477Ssam cmd->dst = cmd->src; 1856104477Ssam } else { 1857104477Ssam if (crp->crp_flags & CRYPTO_F_IOV) { 1858104477Ssam err = EINVAL; 1859104477Ssam goto err_srcmap; 1860104477Ssam } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1861104477Ssam int totlen, len; 1862104477Ssam struct mbuf *m, *m0, *mlast; 1863104477Ssam 1864104477Ssam KASSERT(cmd->dst_m == cmd->src_m, 1865104477Ssam ("hifn_crypto: dst_m initialized improperly")); 1866104477Ssam hifnstats.hst_unaligned++; 1867104477Ssam /* 1868104477Ssam * Source is not aligned on a longword boundary. 1869104477Ssam * Copy the data to insure alignment. If we fail 1870104477Ssam * to allocate mbufs or clusters while doing this 1871104477Ssam * we return ERESTART so the operation is requeued 1872104477Ssam * at the crypto later, but only if there are 1873104477Ssam * ops already posted to the hardware; otherwise we 1874104477Ssam * have no guarantee that we'll be re-entered. 1875104477Ssam */ 1876104477Ssam totlen = cmd->src_mapsize; 1877104477Ssam if (cmd->src_m->m_flags & M_PKTHDR) { 1878104477Ssam len = MHLEN; 1879243857Sglebius MGETHDR(m0, M_NOWAIT, MT_DATA); 1880243857Sglebius if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_NOWAIT)) { 1881108466Ssam m_free(m0); 1882108466Ssam m0 = NULL; 1883108466Ssam } 1884104477Ssam } else { 1885104477Ssam len = MLEN; 1886243857Sglebius MGET(m0, M_NOWAIT, MT_DATA); 1887104477Ssam } 1888104477Ssam if (m0 == NULL) { 1889104477Ssam hifnstats.hst_nomem_mbuf++; 1890213091Sgonzo err = sc->sc_cmdu ? ERESTART : ENOMEM; 1891104477Ssam goto err_srcmap; 1892104477Ssam } 1893104477Ssam if (totlen >= MINCLSIZE) { 1894276750Srwatson if (!(MCLGET(m0, M_NOWAIT))) { 1895104477Ssam hifnstats.hst_nomem_mcl++; 1896213091Sgonzo err = sc->sc_cmdu ? ERESTART : ENOMEM; 1897104477Ssam m_freem(m0); 1898104477Ssam goto err_srcmap; 1899104477Ssam } 1900104477Ssam len = MCLBYTES; 1901104477Ssam } 1902104477Ssam totlen -= len; 1903104477Ssam m0->m_pkthdr.len = m0->m_len = len; 1904104477Ssam mlast = m0; 1905104477Ssam 1906104477Ssam while (totlen > 0) { 1907243857Sglebius MGET(m, M_NOWAIT, MT_DATA); 1908104477Ssam if (m == NULL) { 1909104477Ssam hifnstats.hst_nomem_mbuf++; 1910213091Sgonzo err = sc->sc_cmdu ? ERESTART : ENOMEM; 1911104477Ssam m_freem(m0); 1912104477Ssam goto err_srcmap; 1913104477Ssam } 1914104477Ssam len = MLEN; 1915104477Ssam if (totlen >= MINCLSIZE) { 1916276750Srwatson if (!(MCLGET(m, M_NOWAIT))) { 1917104477Ssam hifnstats.hst_nomem_mcl++; 1918213091Sgonzo err = sc->sc_cmdu ? ERESTART : ENOMEM; 1919104477Ssam mlast->m_next = m; 1920104477Ssam m_freem(m0); 1921104477Ssam goto err_srcmap; 1922104477Ssam } 1923104477Ssam len = MCLBYTES; 1924104477Ssam } 1925104477Ssam 1926104477Ssam m->m_len = len; 1927104477Ssam m0->m_pkthdr.len += len; 1928104477Ssam totlen -= len; 1929104477Ssam 1930104477Ssam mlast->m_next = m; 1931104477Ssam mlast = m; 1932104477Ssam } 1933104477Ssam cmd->dst_m = m0; 1934104477Ssam } 1935104477Ssam } 1936104477Ssam 1937104477Ssam if (cmd->dst_map == NULL) { 1938104477Ssam if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1939104477Ssam hifnstats.hst_nomem_map++; 1940104477Ssam err = ENOMEM; 1941104477Ssam goto err_srcmap; 1942104477Ssam } 1943104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 1944104477Ssam if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1945104477Ssam cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1946104477Ssam hifnstats.hst_nomem_map++; 1947104477Ssam err = ENOMEM; 1948104477Ssam goto err_dstmap1; 1949104477Ssam } 1950104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 1951104477Ssam if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1952104477Ssam cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1953104477Ssam hifnstats.hst_nomem_load++; 1954104477Ssam err = ENOMEM; 1955104477Ssam goto err_dstmap1; 1956104477Ssam } 1957104477Ssam } 1958104477Ssam } 1959104477Ssam 1960104477Ssam#ifdef HIFN_DEBUG 1961104477Ssam if (hifn_debug) { 1962104477Ssam device_printf(sc->sc_dev, 1963104477Ssam "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1964104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 1965104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER), 1966213091Sgonzo sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu, 1967104477Ssam cmd->src_nsegs, cmd->dst_nsegs); 1968104477Ssam } 1969104477Ssam#endif 1970104477Ssam 1971104477Ssam if (cmd->src_map == cmd->dst_map) { 1972104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1973104477Ssam BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1974104477Ssam } else { 1975104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 1976104477Ssam BUS_DMASYNC_PREWRITE); 1977104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 1978104477Ssam BUS_DMASYNC_PREREAD); 1979104477Ssam } 1980104477Ssam 1981104477Ssam /* 1982104477Ssam * need N src, and N dst 1983104477Ssam */ 1984213091Sgonzo if ((sc->sc_srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 1985213091Sgonzo (sc->sc_dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 1986104477Ssam#ifdef HIFN_DEBUG 1987104477Ssam if (hifn_debug) { 1988104477Ssam device_printf(sc->sc_dev, 1989104477Ssam "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 1990213091Sgonzo sc->sc_srcu, cmd->src_nsegs, 1991213091Sgonzo sc->sc_dstu, cmd->dst_nsegs); 1992104477Ssam } 1993104477Ssam#endif 1994104477Ssam hifnstats.hst_nomem_sd++; 1995104477Ssam err = ERESTART; 1996104477Ssam goto err_dstmap; 1997104477Ssam } 1998104477Ssam 1999213091Sgonzo if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) { 2000213091Sgonzo sc->sc_cmdi = 0; 2001104477Ssam dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 2002104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 2003104477Ssam HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 2004104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2005104477Ssam } 2006213091Sgonzo cmdi = sc->sc_cmdi++; 2007104477Ssam cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 2008104477Ssam HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 2009104477Ssam 2010104477Ssam /* .p for command/result already set */ 2011104477Ssam dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 2012104477Ssam HIFN_D_MASKDONEIRQ); 2013104477Ssam HIFN_CMDR_SYNC(sc, cmdi, 2014104477Ssam BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2015213091Sgonzo sc->sc_cmdu++; 2016104477Ssam 2017104477Ssam /* 2018104477Ssam * We don't worry about missing an interrupt (which a "command wait" 2019104477Ssam * interrupt salvages us from), unless there is more than one command 2020104477Ssam * in the queue. 2021104477Ssam */ 2022213091Sgonzo if (sc->sc_cmdu > 1) { 2023104477Ssam sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 2024104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2025104477Ssam } 2026104477Ssam 2027104477Ssam hifnstats.hst_ipackets++; 2028104477Ssam hifnstats.hst_ibytes += cmd->src_mapsize; 2029104477Ssam 2030104477Ssam hifn_dmamap_load_src(sc, cmd); 2031104477Ssam 2032104477Ssam /* 2033104477Ssam * Unlike other descriptors, we don't mask done interrupt from 2034104477Ssam * result descriptor. 2035104477Ssam */ 2036104477Ssam#ifdef HIFN_DEBUG 2037104477Ssam if (hifn_debug) 2038104477Ssam printf("load res\n"); 2039104477Ssam#endif 2040213091Sgonzo if (sc->sc_resi == HIFN_D_RES_RSIZE) { 2041213091Sgonzo sc->sc_resi = 0; 2042104477Ssam dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 2043104477Ssam HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 2044104477Ssam HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 2045104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2046104477Ssam } 2047213091Sgonzo resi = sc->sc_resi++; 2048213091Sgonzo KASSERT(sc->sc_hifn_commands[resi] == NULL, 2049104477Ssam ("hifn_crypto: command slot %u busy", resi)); 2050213091Sgonzo sc->sc_hifn_commands[resi] = cmd; 2051104477Ssam HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 2052104477Ssam if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 2053104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 2054104477Ssam HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 2055104477Ssam sc->sc_curbatch++; 2056104477Ssam if (sc->sc_curbatch > hifnstats.hst_maxbatch) 2057104477Ssam hifnstats.hst_maxbatch = sc->sc_curbatch; 2058104477Ssam hifnstats.hst_totbatch++; 2059104477Ssam } else { 2060104477Ssam dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 2061104477Ssam HIFN_D_VALID | HIFN_D_LAST); 2062104477Ssam sc->sc_curbatch = 0; 2063104477Ssam } 2064104477Ssam HIFN_RESR_SYNC(sc, resi, 2065104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2066213091Sgonzo sc->sc_resu++; 2067104477Ssam 2068104477Ssam if (cmd->sloplen) 2069104477Ssam cmd->slopidx = resi; 2070104477Ssam 2071104477Ssam hifn_dmamap_load_dst(sc, cmd); 2072104477Ssam 2073167755Ssam csr = 0; 2074167755Ssam if (sc->sc_c_busy == 0) { 2075167755Ssam csr |= HIFN_DMACSR_C_CTRL_ENA; 2076167755Ssam sc->sc_c_busy = 1; 2077167755Ssam } 2078167755Ssam if (sc->sc_s_busy == 0) { 2079167755Ssam csr |= HIFN_DMACSR_S_CTRL_ENA; 2080167755Ssam sc->sc_s_busy = 1; 2081167755Ssam } 2082167755Ssam if (sc->sc_r_busy == 0) { 2083167755Ssam csr |= HIFN_DMACSR_R_CTRL_ENA; 2084167755Ssam sc->sc_r_busy = 1; 2085167755Ssam } 2086104477Ssam if (sc->sc_d_busy == 0) { 2087167755Ssam csr |= HIFN_DMACSR_D_CTRL_ENA; 2088104477Ssam sc->sc_d_busy = 1; 2089104477Ssam } 2090167755Ssam if (csr) 2091167755Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); 2092104477Ssam 2093104477Ssam#ifdef HIFN_DEBUG 2094104477Ssam if (hifn_debug) { 2095104477Ssam device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 2096104477Ssam READ_REG_1(sc, HIFN_1_DMA_CSR), 2097104477Ssam READ_REG_1(sc, HIFN_1_DMA_IER)); 2098104477Ssam } 2099104477Ssam#endif 2100104477Ssam 2101104477Ssam sc->sc_active = 5; 2102115748Ssam HIFN_UNLOCK(sc); 2103104477Ssam KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 2104104477Ssam return (err); /* success */ 2105104477Ssam 2106104477Ssamerr_dstmap: 2107104477Ssam if (cmd->src_map != cmd->dst_map) 2108104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2109104477Ssamerr_dstmap1: 2110104477Ssam if (cmd->src_map != cmd->dst_map) 2111104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2112104477Ssamerr_srcmap: 2113104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2114104477Ssam if (cmd->src_m != cmd->dst_m) 2115104477Ssam m_freem(cmd->dst_m); 2116104477Ssam } 2117104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2118104477Ssamerr_srcmap1: 2119104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2120115748Ssam HIFN_UNLOCK(sc); 2121104477Ssam return (err); 2122104477Ssam} 2123104477Ssam 2124104477Ssamstatic void 2125104477Ssamhifn_tick(void* vsc) 2126104477Ssam{ 2127104477Ssam struct hifn_softc *sc = vsc; 2128104477Ssam 2129104477Ssam HIFN_LOCK(sc); 2130104477Ssam if (sc->sc_active == 0) { 2131104477Ssam u_int32_t r = 0; 2132104477Ssam 2133213091Sgonzo if (sc->sc_cmdu == 0 && sc->sc_c_busy) { 2134104477Ssam sc->sc_c_busy = 0; 2135104477Ssam r |= HIFN_DMACSR_C_CTRL_DIS; 2136104477Ssam } 2137213091Sgonzo if (sc->sc_srcu == 0 && sc->sc_s_busy) { 2138104477Ssam sc->sc_s_busy = 0; 2139104477Ssam r |= HIFN_DMACSR_S_CTRL_DIS; 2140104477Ssam } 2141213091Sgonzo if (sc->sc_dstu == 0 && sc->sc_d_busy) { 2142104477Ssam sc->sc_d_busy = 0; 2143104477Ssam r |= HIFN_DMACSR_D_CTRL_DIS; 2144104477Ssam } 2145213091Sgonzo if (sc->sc_resu == 0 && sc->sc_r_busy) { 2146104477Ssam sc->sc_r_busy = 0; 2147104477Ssam r |= HIFN_DMACSR_R_CTRL_DIS; 2148104477Ssam } 2149104477Ssam if (r) 2150104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 2151104477Ssam } else 2152104477Ssam sc->sc_active--; 2153104477Ssam HIFN_UNLOCK(sc); 2154104477Ssam callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 2155104477Ssam} 2156104477Ssam 2157104477Ssamstatic void 2158104477Ssamhifn_intr(void *arg) 2159104477Ssam{ 2160104477Ssam struct hifn_softc *sc = arg; 2161104477Ssam struct hifn_dma *dma; 2162104477Ssam u_int32_t dmacsr, restart; 2163104477Ssam int i, u; 2164104477Ssam 2165115748Ssam dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 2166115748Ssam 2167115748Ssam /* Nothing in the DMA unit interrupted */ 2168115748Ssam if ((dmacsr & sc->sc_dmaier) == 0) 2169115748Ssam return; 2170115748Ssam 2171104477Ssam HIFN_LOCK(sc); 2172115748Ssam 2173104477Ssam dma = sc->sc_dma; 2174104477Ssam 2175104477Ssam#ifdef HIFN_DEBUG 2176104477Ssam if (hifn_debug) { 2177104477Ssam device_printf(sc->sc_dev, 2178104477Ssam "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 2179104477Ssam dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 2180213091Sgonzo sc->sc_cmdi, sc->sc_srci, sc->sc_dsti, sc->sc_resi, 2181213091Sgonzo sc->sc_cmdk, sc->sc_srck, sc->sc_dstk, sc->sc_resk, 2182213091Sgonzo sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu); 2183104477Ssam } 2184104477Ssam#endif 2185104477Ssam 2186104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 2187104477Ssam 2188104477Ssam if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 2189104477Ssam (dmacsr & HIFN_DMACSR_PUBDONE)) 2190104477Ssam WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 2191104477Ssam READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 2192104477Ssam 2193104477Ssam restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 2194104477Ssam if (restart) 2195104477Ssam device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 2196104477Ssam 2197104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2198104477Ssam if (dmacsr & HIFN_DMACSR_ILLR) 2199104477Ssam device_printf(sc->sc_dev, "illegal read\n"); 2200104477Ssam if (dmacsr & HIFN_DMACSR_ILLW) 2201104477Ssam device_printf(sc->sc_dev, "illegal write\n"); 2202104477Ssam } 2203104477Ssam 2204104477Ssam restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 2205104477Ssam HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 2206104477Ssam if (restart) { 2207104477Ssam device_printf(sc->sc_dev, "abort, resetting.\n"); 2208104477Ssam hifnstats.hst_abort++; 2209104477Ssam hifn_abort(sc); 2210104477Ssam HIFN_UNLOCK(sc); 2211104477Ssam return; 2212104477Ssam } 2213104477Ssam 2214213091Sgonzo if ((dmacsr & HIFN_DMACSR_C_WAIT) && (sc->sc_cmdu == 0)) { 2215104477Ssam /* 2216104477Ssam * If no slots to process and we receive a "waiting on 2217104477Ssam * command" interrupt, we disable the "waiting on command" 2218104477Ssam * (by clearing it). 2219104477Ssam */ 2220104477Ssam sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2221104477Ssam WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2222104477Ssam } 2223104477Ssam 2224104477Ssam /* clear the rings */ 2225213091Sgonzo i = sc->sc_resk; u = sc->sc_resu; 2226104477Ssam while (u != 0) { 2227104477Ssam HIFN_RESR_SYNC(sc, i, 2228104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2229104477Ssam if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2230104477Ssam HIFN_RESR_SYNC(sc, i, 2231104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2232104477Ssam break; 2233104477Ssam } 2234104477Ssam 2235104477Ssam if (i != HIFN_D_RES_RSIZE) { 2236104477Ssam struct hifn_command *cmd; 2237104477Ssam u_int8_t *macbuf = NULL; 2238104477Ssam 2239104477Ssam HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2240213091Sgonzo cmd = sc->sc_hifn_commands[i]; 2241104477Ssam KASSERT(cmd != NULL, 2242104477Ssam ("hifn_intr: null command slot %u", i)); 2243213091Sgonzo sc->sc_hifn_commands[i] = NULL; 2244104477Ssam 2245104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2246104477Ssam macbuf = dma->result_bufs[i]; 2247104477Ssam macbuf += 12; 2248104477Ssam } 2249104477Ssam 2250104477Ssam hifn_callback(sc, cmd, macbuf); 2251104477Ssam hifnstats.hst_opackets++; 2252104477Ssam u--; 2253104477Ssam } 2254104477Ssam 2255104477Ssam if (++i == (HIFN_D_RES_RSIZE + 1)) 2256104477Ssam i = 0; 2257104477Ssam } 2258213091Sgonzo sc->sc_resk = i; sc->sc_resu = u; 2259104477Ssam 2260213091Sgonzo i = sc->sc_srck; u = sc->sc_srcu; 2261104477Ssam while (u != 0) { 2262104477Ssam if (i == HIFN_D_SRC_RSIZE) 2263104477Ssam i = 0; 2264104477Ssam HIFN_SRCR_SYNC(sc, i, 2265104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2266104477Ssam if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2267104477Ssam HIFN_SRCR_SYNC(sc, i, 2268104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2269104477Ssam break; 2270104477Ssam } 2271104477Ssam i++, u--; 2272104477Ssam } 2273213091Sgonzo sc->sc_srck = i; sc->sc_srcu = u; 2274104477Ssam 2275213091Sgonzo i = sc->sc_cmdk; u = sc->sc_cmdu; 2276104477Ssam while (u != 0) { 2277104477Ssam HIFN_CMDR_SYNC(sc, i, 2278104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2279104477Ssam if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2280104477Ssam HIFN_CMDR_SYNC(sc, i, 2281104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2282104477Ssam break; 2283104477Ssam } 2284104477Ssam if (i != HIFN_D_CMD_RSIZE) { 2285104477Ssam u--; 2286104477Ssam HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2287104477Ssam } 2288104477Ssam if (++i == (HIFN_D_CMD_RSIZE + 1)) 2289104477Ssam i = 0; 2290104477Ssam } 2291213091Sgonzo sc->sc_cmdk = i; sc->sc_cmdu = u; 2292104477Ssam 2293115748Ssam HIFN_UNLOCK(sc); 2294115748Ssam 2295104477Ssam if (sc->sc_needwakeup) { /* XXX check high watermark */ 2296104477Ssam int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2297104477Ssam#ifdef HIFN_DEBUG 2298104477Ssam if (hifn_debug) 2299104477Ssam device_printf(sc->sc_dev, 2300104477Ssam "wakeup crypto (%x) u %d/%d/%d/%d\n", 2301104477Ssam sc->sc_needwakeup, 2302213091Sgonzo sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu); 2303104477Ssam#endif 2304104477Ssam sc->sc_needwakeup &= ~wakeup; 2305104477Ssam crypto_unblock(sc->sc_cid, wakeup); 2306104477Ssam } 2307104477Ssam} 2308104477Ssam 2309104477Ssam/* 2310104477Ssam * Allocate a new 'session' and return an encoded session id. 'sidp' 2311104477Ssam * contains our registration id, and should contain an encoded session 2312104477Ssam * id on successful allocation. 2313104477Ssam */ 2314104477Ssamstatic int 2315167755Ssamhifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) 2316104477Ssam{ 2317167755Ssam struct hifn_softc *sc = device_get_softc(dev); 2318104477Ssam struct cryptoini *c; 2319136526Ssam int mac = 0, cry = 0, sesn; 2320136532Ssam struct hifn_session *ses = NULL; 2321104477Ssam 2322104477Ssam KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2323104477Ssam if (sidp == NULL || cri == NULL || sc == NULL) 2324104477Ssam return (EINVAL); 2325104477Ssam 2326167755Ssam HIFN_LOCK(sc); 2327136526Ssam if (sc->sc_sessions == NULL) { 2328136526Ssam ses = sc->sc_sessions = (struct hifn_session *)malloc( 2329136526Ssam sizeof(*ses), M_DEVBUF, M_NOWAIT); 2330167755Ssam if (ses == NULL) { 2331167755Ssam HIFN_UNLOCK(sc); 2332136526Ssam return (ENOMEM); 2333167755Ssam } 2334136526Ssam sesn = 0; 2335136526Ssam sc->sc_nsessions = 1; 2336136526Ssam } else { 2337136526Ssam for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 2338136526Ssam if (!sc->sc_sessions[sesn].hs_used) { 2339136526Ssam ses = &sc->sc_sessions[sesn]; 2340136526Ssam break; 2341136526Ssam } 2342136526Ssam } 2343104477Ssam 2344136526Ssam if (ses == NULL) { 2345136526Ssam sesn = sc->sc_nsessions; 2346136526Ssam ses = (struct hifn_session *)malloc((sesn + 1) * 2347136526Ssam sizeof(*ses), M_DEVBUF, M_NOWAIT); 2348167755Ssam if (ses == NULL) { 2349167755Ssam HIFN_UNLOCK(sc); 2350136526Ssam return (ENOMEM); 2351167755Ssam } 2352136526Ssam bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); 2353136526Ssam bzero(sc->sc_sessions, sesn * sizeof(*ses)); 2354136526Ssam free(sc->sc_sessions, M_DEVBUF); 2355136526Ssam sc->sc_sessions = ses; 2356136526Ssam ses = &sc->sc_sessions[sesn]; 2357136526Ssam sc->sc_nsessions++; 2358136526Ssam } 2359136526Ssam } 2360167755Ssam HIFN_UNLOCK(sc); 2361167755Ssam 2362136526Ssam bzero(ses, sizeof(*ses)); 2363136526Ssam ses->hs_used = 1; 2364136526Ssam 2365104477Ssam for (c = cri; c != NULL; c = c->cri_next) { 2366104477Ssam switch (c->cri_alg) { 2367104477Ssam case CRYPTO_MD5: 2368104477Ssam case CRYPTO_SHA1: 2369104477Ssam case CRYPTO_MD5_HMAC: 2370104477Ssam case CRYPTO_SHA1_HMAC: 2371104477Ssam if (mac) 2372104477Ssam return (EINVAL); 2373104477Ssam mac = 1; 2374158705Spjd ses->hs_mlen = c->cri_mlen; 2375158705Spjd if (ses->hs_mlen == 0) { 2376158705Spjd switch (c->cri_alg) { 2377158705Spjd case CRYPTO_MD5: 2378158705Spjd case CRYPTO_MD5_HMAC: 2379158705Spjd ses->hs_mlen = 16; 2380158705Spjd break; 2381158705Spjd case CRYPTO_SHA1: 2382158705Spjd case CRYPTO_SHA1_HMAC: 2383158705Spjd ses->hs_mlen = 20; 2384158705Spjd break; 2385158705Spjd } 2386158705Spjd } 2387104477Ssam break; 2388104477Ssam case CRYPTO_DES_CBC: 2389104477Ssam case CRYPTO_3DES_CBC: 2390120915Ssam case CRYPTO_AES_CBC: 2391104477Ssam /* XXX this may read fewer, does it matter? */ 2392136526Ssam read_random(ses->hs_iv, 2393120915Ssam c->cri_alg == CRYPTO_AES_CBC ? 2394120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2395104477Ssam /*FALLTHROUGH*/ 2396104477Ssam case CRYPTO_ARC4: 2397104477Ssam if (cry) 2398104477Ssam return (EINVAL); 2399104477Ssam cry = 1; 2400104477Ssam break; 2401104477Ssam default: 2402104477Ssam return (EINVAL); 2403104477Ssam } 2404104477Ssam } 2405104477Ssam if (mac == 0 && cry == 0) 2406104477Ssam return (EINVAL); 2407104477Ssam 2408136526Ssam *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); 2409104477Ssam 2410104477Ssam return (0); 2411104477Ssam} 2412104477Ssam 2413104477Ssam/* 2414104477Ssam * Deallocate a session. 2415104477Ssam * XXX this routine should run a zero'd mac/encrypt key into context ram. 2416104477Ssam * XXX to blow away any keys already stored there. 2417104477Ssam */ 2418104477Ssamstatic int 2419167755Ssamhifn_freesession(device_t dev, u_int64_t tid) 2420104477Ssam{ 2421167755Ssam struct hifn_softc *sc = device_get_softc(dev); 2422167755Ssam int session, error; 2423116924Ssam u_int32_t sid = CRYPTO_SESID2LID(tid); 2424104477Ssam 2425104477Ssam KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2426104477Ssam if (sc == NULL) 2427104477Ssam return (EINVAL); 2428104477Ssam 2429167755Ssam HIFN_LOCK(sc); 2430104477Ssam session = HIFN_SESSION(sid); 2431167755Ssam if (session < sc->sc_nsessions) { 2432167755Ssam bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); 2433167755Ssam error = 0; 2434167755Ssam } else 2435167755Ssam error = EINVAL; 2436167755Ssam HIFN_UNLOCK(sc); 2437104477Ssam 2438167755Ssam return (error); 2439104477Ssam} 2440104477Ssam 2441104477Ssamstatic int 2442167755Ssamhifn_process(device_t dev, struct cryptop *crp, int hint) 2443104477Ssam{ 2444167755Ssam struct hifn_softc *sc = device_get_softc(dev); 2445104477Ssam struct hifn_command *cmd = NULL; 2446120915Ssam int session, err, ivlen; 2447104477Ssam struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2448104477Ssam 2449104477Ssam if (crp == NULL || crp->crp_callback == NULL) { 2450104477Ssam hifnstats.hst_invalid++; 2451104477Ssam return (EINVAL); 2452104477Ssam } 2453104477Ssam session = HIFN_SESSION(crp->crp_sid); 2454104477Ssam 2455136526Ssam if (sc == NULL || session >= sc->sc_nsessions) { 2456104477Ssam err = EINVAL; 2457104477Ssam goto errout; 2458104477Ssam } 2459104477Ssam 2460104477Ssam cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2461104477Ssam if (cmd == NULL) { 2462104477Ssam hifnstats.hst_nomem++; 2463104477Ssam err = ENOMEM; 2464104477Ssam goto errout; 2465104477Ssam } 2466104477Ssam 2467104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2468104477Ssam cmd->src_m = (struct mbuf *)crp->crp_buf; 2469104477Ssam cmd->dst_m = (struct mbuf *)crp->crp_buf; 2470104477Ssam } else if (crp->crp_flags & CRYPTO_F_IOV) { 2471104477Ssam cmd->src_io = (struct uio *)crp->crp_buf; 2472104477Ssam cmd->dst_io = (struct uio *)crp->crp_buf; 2473104477Ssam } else { 2474104477Ssam err = EINVAL; 2475104477Ssam goto errout; /* XXX we don't handle contiguous buffers! */ 2476104477Ssam } 2477104477Ssam 2478104477Ssam crd1 = crp->crp_desc; 2479104477Ssam if (crd1 == NULL) { 2480104477Ssam err = EINVAL; 2481104477Ssam goto errout; 2482104477Ssam } 2483104477Ssam crd2 = crd1->crd_next; 2484104477Ssam 2485104477Ssam if (crd2 == NULL) { 2486104477Ssam if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2487104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2488104477Ssam crd1->crd_alg == CRYPTO_SHA1 || 2489104477Ssam crd1->crd_alg == CRYPTO_MD5) { 2490104477Ssam maccrd = crd1; 2491104477Ssam enccrd = NULL; 2492104477Ssam } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2493104477Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2494120915Ssam crd1->crd_alg == CRYPTO_AES_CBC || 2495104477Ssam crd1->crd_alg == CRYPTO_ARC4) { 2496104477Ssam if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2497104477Ssam cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2498104477Ssam maccrd = NULL; 2499104477Ssam enccrd = crd1; 2500104477Ssam } else { 2501104477Ssam err = EINVAL; 2502104477Ssam goto errout; 2503104477Ssam } 2504104477Ssam } else { 2505104477Ssam if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2506104477Ssam crd1->crd_alg == CRYPTO_SHA1_HMAC || 2507104477Ssam crd1->crd_alg == CRYPTO_MD5 || 2508104477Ssam crd1->crd_alg == CRYPTO_SHA1) && 2509104477Ssam (crd2->crd_alg == CRYPTO_DES_CBC || 2510104477Ssam crd2->crd_alg == CRYPTO_3DES_CBC || 2511120915Ssam crd2->crd_alg == CRYPTO_AES_CBC || 2512104477Ssam crd2->crd_alg == CRYPTO_ARC4) && 2513104477Ssam ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2514104477Ssam cmd->base_masks = HIFN_BASE_CMD_DECODE; 2515104477Ssam maccrd = crd1; 2516104477Ssam enccrd = crd2; 2517104477Ssam } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2518104477Ssam crd1->crd_alg == CRYPTO_ARC4 || 2519120915Ssam crd1->crd_alg == CRYPTO_3DES_CBC || 2520120915Ssam crd1->crd_alg == CRYPTO_AES_CBC) && 2521104477Ssam (crd2->crd_alg == CRYPTO_MD5_HMAC || 2522104477Ssam crd2->crd_alg == CRYPTO_SHA1_HMAC || 2523104477Ssam crd2->crd_alg == CRYPTO_MD5 || 2524104477Ssam crd2->crd_alg == CRYPTO_SHA1) && 2525104477Ssam (crd1->crd_flags & CRD_F_ENCRYPT)) { 2526104477Ssam enccrd = crd1; 2527104477Ssam maccrd = crd2; 2528104477Ssam } else { 2529104477Ssam /* 2530104477Ssam * We cannot order the 7751 as requested 2531104477Ssam */ 2532104477Ssam err = EINVAL; 2533104477Ssam goto errout; 2534104477Ssam } 2535104477Ssam } 2536104477Ssam 2537104477Ssam if (enccrd) { 2538104477Ssam cmd->enccrd = enccrd; 2539104477Ssam cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2540104477Ssam switch (enccrd->crd_alg) { 2541104477Ssam case CRYPTO_ARC4: 2542104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2543104477Ssam break; 2544104477Ssam case CRYPTO_DES_CBC: 2545104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2546104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2547104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2548104477Ssam break; 2549104477Ssam case CRYPTO_3DES_CBC: 2550104477Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2551104477Ssam HIFN_CRYPT_CMD_MODE_CBC | 2552104477Ssam HIFN_CRYPT_CMD_NEW_IV; 2553104477Ssam break; 2554120915Ssam case CRYPTO_AES_CBC: 2555120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | 2556120915Ssam HIFN_CRYPT_CMD_MODE_CBC | 2557120915Ssam HIFN_CRYPT_CMD_NEW_IV; 2558120915Ssam break; 2559104477Ssam default: 2560104477Ssam err = EINVAL; 2561104477Ssam goto errout; 2562104477Ssam } 2563104477Ssam if (enccrd->crd_alg != CRYPTO_ARC4) { 2564120915Ssam ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? 2565120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2566104477Ssam if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2567104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2568120915Ssam bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2569104477Ssam else 2570104477Ssam bcopy(sc->sc_sessions[session].hs_iv, 2571120915Ssam cmd->iv, ivlen); 2572104477Ssam 2573104477Ssam if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2574104477Ssam == 0) { 2575159242Spjd crypto_copyback(crp->crp_flags, 2576159242Spjd crp->crp_buf, enccrd->crd_inject, 2577159242Spjd ivlen, cmd->iv); 2578104477Ssam } 2579104477Ssam } else { 2580104477Ssam if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2581120915Ssam bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2582159242Spjd else { 2583159242Spjd crypto_copydata(crp->crp_flags, 2584159242Spjd crp->crp_buf, enccrd->crd_inject, 2585159242Spjd ivlen, cmd->iv); 2586159242Spjd } 2587104477Ssam } 2588104477Ssam } 2589104477Ssam 2590125330Sphk if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 2591125330Sphk cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2592104477Ssam cmd->ck = enccrd->crd_key; 2593104477Ssam cmd->cklen = enccrd->crd_klen >> 3; 2594136526Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2595104477Ssam 2596120915Ssam /* 2597120915Ssam * Need to specify the size for the AES key in the masks. 2598120915Ssam */ 2599120915Ssam if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == 2600120915Ssam HIFN_CRYPT_CMD_ALG_AES) { 2601120915Ssam switch (cmd->cklen) { 2602120915Ssam case 16: 2603120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; 2604120915Ssam break; 2605120915Ssam case 24: 2606120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; 2607120915Ssam break; 2608120915Ssam case 32: 2609120915Ssam cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; 2610120915Ssam break; 2611120915Ssam default: 2612120915Ssam err = EINVAL; 2613120915Ssam goto errout; 2614120915Ssam } 2615120915Ssam } 2616104477Ssam } 2617104477Ssam 2618104477Ssam if (maccrd) { 2619104477Ssam cmd->maccrd = maccrd; 2620104477Ssam cmd->base_masks |= HIFN_BASE_CMD_MAC; 2621104477Ssam 2622104477Ssam switch (maccrd->crd_alg) { 2623104477Ssam case CRYPTO_MD5: 2624104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2625104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2626104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2627104477Ssam break; 2628104477Ssam case CRYPTO_MD5_HMAC: 2629104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2630104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2631104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2632104477Ssam break; 2633104477Ssam case CRYPTO_SHA1: 2634104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2635104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2636104477Ssam HIFN_MAC_CMD_POS_IPSEC; 2637104477Ssam break; 2638104477Ssam case CRYPTO_SHA1_HMAC: 2639104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2640104477Ssam HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2641104477Ssam HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2642104477Ssam break; 2643104477Ssam } 2644104477Ssam 2645136526Ssam if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2646136526Ssam maccrd->crd_alg == CRYPTO_MD5_HMAC) { 2647104477Ssam cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2648104477Ssam bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2649104477Ssam bzero(cmd->mac + (maccrd->crd_klen >> 3), 2650104477Ssam HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2651104477Ssam } 2652104477Ssam } 2653104477Ssam 2654104477Ssam cmd->crp = crp; 2655104477Ssam cmd->session_num = session; 2656104477Ssam cmd->softc = sc; 2657104477Ssam 2658104477Ssam err = hifn_crypto(sc, cmd, crp, hint); 2659104477Ssam if (!err) { 2660104477Ssam return 0; 2661104477Ssam } else if (err == ERESTART) { 2662104477Ssam /* 2663104477Ssam * There weren't enough resources to dispatch the request 2664104477Ssam * to the part. Notify the caller so they'll requeue this 2665104477Ssam * request and resubmit it again soon. 2666104477Ssam */ 2667104477Ssam#ifdef HIFN_DEBUG 2668104477Ssam if (hifn_debug) 2669104477Ssam device_printf(sc->sc_dev, "requeue request\n"); 2670104477Ssam#endif 2671104477Ssam free(cmd, M_DEVBUF); 2672104477Ssam sc->sc_needwakeup |= CRYPTO_SYMQ; 2673104477Ssam return (err); 2674104477Ssam } 2675104477Ssam 2676104477Ssamerrout: 2677104477Ssam if (cmd != NULL) 2678104477Ssam free(cmd, M_DEVBUF); 2679104477Ssam if (err == EINVAL) 2680104477Ssam hifnstats.hst_invalid++; 2681104477Ssam else 2682104477Ssam hifnstats.hst_nomem++; 2683104477Ssam crp->crp_etype = err; 2684104477Ssam crypto_done(crp); 2685104477Ssam return (err); 2686104477Ssam} 2687104477Ssam 2688104477Ssamstatic void 2689104477Ssamhifn_abort(struct hifn_softc *sc) 2690104477Ssam{ 2691104477Ssam struct hifn_dma *dma = sc->sc_dma; 2692104477Ssam struct hifn_command *cmd; 2693104477Ssam struct cryptop *crp; 2694104477Ssam int i, u; 2695104477Ssam 2696213091Sgonzo i = sc->sc_resk; u = sc->sc_resu; 2697104477Ssam while (u != 0) { 2698213091Sgonzo cmd = sc->sc_hifn_commands[i]; 2699104477Ssam KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2700213091Sgonzo sc->sc_hifn_commands[i] = NULL; 2701104477Ssam crp = cmd->crp; 2702104477Ssam 2703104477Ssam if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2704104477Ssam /* Salvage what we can. */ 2705104477Ssam u_int8_t *macbuf; 2706104477Ssam 2707104477Ssam if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2708104477Ssam macbuf = dma->result_bufs[i]; 2709104477Ssam macbuf += 12; 2710104477Ssam } else 2711104477Ssam macbuf = NULL; 2712104477Ssam hifnstats.hst_opackets++; 2713104477Ssam hifn_callback(sc, cmd, macbuf); 2714104477Ssam } else { 2715104477Ssam if (cmd->src_map == cmd->dst_map) { 2716104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2717104477Ssam BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2718104477Ssam } else { 2719104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2720104477Ssam BUS_DMASYNC_POSTWRITE); 2721104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2722104477Ssam BUS_DMASYNC_POSTREAD); 2723104477Ssam } 2724104477Ssam 2725104477Ssam if (cmd->src_m != cmd->dst_m) { 2726104477Ssam m_freem(cmd->src_m); 2727104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2728104477Ssam } 2729104477Ssam 2730104477Ssam /* non-shared buffers cannot be restarted */ 2731104477Ssam if (cmd->src_map != cmd->dst_map) { 2732104477Ssam /* 2733104477Ssam * XXX should be EAGAIN, delayed until 2734104477Ssam * after the reset. 2735104477Ssam */ 2736104477Ssam crp->crp_etype = ENOMEM; 2737104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2738104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2739104477Ssam } else 2740104477Ssam crp->crp_etype = ENOMEM; 2741104477Ssam 2742104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2743104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2744104477Ssam 2745104477Ssam free(cmd, M_DEVBUF); 2746104477Ssam if (crp->crp_etype != EAGAIN) 2747104477Ssam crypto_done(crp); 2748104477Ssam } 2749104477Ssam 2750104477Ssam if (++i == HIFN_D_RES_RSIZE) 2751104477Ssam i = 0; 2752104477Ssam u--; 2753104477Ssam } 2754213091Sgonzo sc->sc_resk = i; sc->sc_resu = u; 2755104477Ssam 2756104477Ssam hifn_reset_board(sc, 1); 2757104477Ssam hifn_init_dma(sc); 2758104477Ssam hifn_init_pci_registers(sc); 2759104477Ssam} 2760104477Ssam 2761104477Ssamstatic void 2762104477Ssamhifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2763104477Ssam{ 2764104477Ssam struct hifn_dma *dma = sc->sc_dma; 2765104477Ssam struct cryptop *crp = cmd->crp; 2766104477Ssam struct cryptodesc *crd; 2767104477Ssam struct mbuf *m; 2768120915Ssam int totlen, i, u, ivlen; 2769104477Ssam 2770104477Ssam if (cmd->src_map == cmd->dst_map) { 2771104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2772104477Ssam BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2773104477Ssam } else { 2774104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2775104477Ssam BUS_DMASYNC_POSTWRITE); 2776104477Ssam bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2777104477Ssam BUS_DMASYNC_POSTREAD); 2778104477Ssam } 2779104477Ssam 2780104477Ssam if (crp->crp_flags & CRYPTO_F_IMBUF) { 2781104477Ssam if (cmd->src_m != cmd->dst_m) { 2782104477Ssam crp->crp_buf = (caddr_t)cmd->dst_m; 2783104477Ssam totlen = cmd->src_mapsize; 2784104477Ssam for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2785104477Ssam if (totlen < m->m_len) { 2786104477Ssam m->m_len = totlen; 2787104477Ssam totlen = 0; 2788104477Ssam } else 2789104477Ssam totlen -= m->m_len; 2790104477Ssam } 2791104477Ssam cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2792104477Ssam m_freem(cmd->src_m); 2793104477Ssam } 2794104477Ssam } 2795104477Ssam 2796104477Ssam if (cmd->sloplen != 0) { 2797159242Spjd crypto_copyback(crp->crp_flags, crp->crp_buf, 2798159242Spjd cmd->src_mapsize - cmd->sloplen, cmd->sloplen, 2799159242Spjd (caddr_t)&dma->slop[cmd->slopidx]); 2800104477Ssam } 2801104477Ssam 2802213091Sgonzo i = sc->sc_dstk; u = sc->sc_dstu; 2803104477Ssam while (u != 0) { 2804104477Ssam if (i == HIFN_D_DST_RSIZE) 2805104477Ssam i = 0; 2806104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2807104477Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2808104477Ssam if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2809104477Ssam bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2810104477Ssam BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2811104477Ssam break; 2812104477Ssam } 2813104477Ssam i++, u--; 2814104477Ssam } 2815213091Sgonzo sc->sc_dstk = i; sc->sc_dstu = u; 2816104477Ssam 2817104477Ssam hifnstats.hst_obytes += cmd->dst_mapsize; 2818104477Ssam 2819104477Ssam if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2820104477Ssam HIFN_BASE_CMD_CRYPT) { 2821104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2822104477Ssam if (crd->crd_alg != CRYPTO_DES_CBC && 2823120915Ssam crd->crd_alg != CRYPTO_3DES_CBC && 2824120915Ssam crd->crd_alg != CRYPTO_AES_CBC) 2825104477Ssam continue; 2826120915Ssam ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? 2827120915Ssam HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2828159242Spjd crypto_copydata(crp->crp_flags, crp->crp_buf, 2829159242Spjd crd->crd_skip + crd->crd_len - ivlen, ivlen, 2830159242Spjd cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2831104477Ssam break; 2832104477Ssam } 2833104477Ssam } 2834104477Ssam 2835104477Ssam if (macbuf != NULL) { 2836104477Ssam for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2837105275Ssam int len; 2838104477Ssam 2839158705Spjd if (crd->crd_alg != CRYPTO_MD5 && 2840158705Spjd crd->crd_alg != CRYPTO_SHA1 && 2841158705Spjd crd->crd_alg != CRYPTO_MD5_HMAC && 2842158705Spjd crd->crd_alg != CRYPTO_SHA1_HMAC) { 2843104477Ssam continue; 2844158705Spjd } 2845158705Spjd len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; 2846159242Spjd crypto_copyback(crp->crp_flags, crp->crp_buf, 2847159242Spjd crd->crd_inject, len, macbuf); 2848104477Ssam break; 2849104477Ssam } 2850104477Ssam } 2851104477Ssam 2852104477Ssam if (cmd->src_map != cmd->dst_map) { 2853104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2854104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2855104477Ssam } 2856104477Ssam bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2857104477Ssam bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2858104477Ssam free(cmd, M_DEVBUF); 2859104477Ssam crypto_done(crp); 2860104477Ssam} 2861104477Ssam 2862104477Ssam/* 2863104477Ssam * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2864104477Ssam * and Group 1 registers; avoid conditions that could create 2865104477Ssam * burst writes by doing a read in between the writes. 2866104477Ssam * 2867104477Ssam * NB: The read we interpose is always to the same register; 2868104477Ssam * we do this because reading from an arbitrary (e.g. last) 2869104477Ssam * register may not always work. 2870104477Ssam */ 2871104477Ssamstatic void 2872104477Ssamhifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2873104477Ssam{ 2874104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2875104477Ssam if (sc->sc_bar0_lastreg == reg - 4) 2876104477Ssam bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2877104477Ssam sc->sc_bar0_lastreg = reg; 2878104477Ssam } 2879104477Ssam bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2880104477Ssam} 2881104477Ssam 2882104477Ssamstatic void 2883104477Ssamhifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2884104477Ssam{ 2885104477Ssam if (sc->sc_flags & HIFN_IS_7811) { 2886104477Ssam if (sc->sc_bar1_lastreg == reg - 4) 2887104477Ssam bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2888104477Ssam sc->sc_bar1_lastreg = reg; 2889104477Ssam } 2890104477Ssam bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2891104477Ssam} 2892167755Ssam 2893167755Ssam#ifdef HIFN_VULCANDEV 2894167755Ssam/* 2895167755Ssam * this code provides support for mapping the PK engine's register 2896167755Ssam * into a userspace program. 2897167755Ssam * 2898167755Ssam */ 2899167755Ssamstatic int 2900201223Srnolandvulcanpk_mmap(struct cdev *dev, vm_ooffset_t offset, 2901201223Srnoland vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr) 2902167755Ssam{ 2903167755Ssam struct hifn_softc *sc; 2904167755Ssam vm_paddr_t pd; 2905167755Ssam void *b; 2906167755Ssam 2907167755Ssam sc = dev->si_drv1; 2908167755Ssam 2909167755Ssam pd = rman_get_start(sc->sc_bar1res); 2910167755Ssam b = rman_get_virtual(sc->sc_bar1res); 2911167755Ssam 2912167755Ssam#if 0 2913201223Srnoland printf("vpk mmap: %p(%016llx) offset=%lld\n", b, 2914201223Srnoland (unsigned long long)pd, offset); 2915167755Ssam hexdump(b, HIFN_1_PUB_MEMEND, "vpk", 0); 2916167755Ssam#endif 2917167755Ssam 2918167755Ssam if (offset == 0) { 2919167755Ssam *paddr = pd; 2920167755Ssam return (0); 2921167755Ssam } 2922167755Ssam return (-1); 2923167755Ssam} 2924167755Ssam 2925167755Ssamstatic struct cdevsw vulcanpk_cdevsw = { 2926167755Ssam .d_version = D_VERSION, 2927167755Ssam .d_mmap = vulcanpk_mmap, 2928167755Ssam .d_name = "vulcanpk", 2929167755Ssam}; 2930167755Ssam#endif /* HIFN_VULCANDEV */ 2931