1248782Sadrian/*- 2248782Sadrian * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org> 3248782Sadrian * All rights reserved. 4248782Sadrian * 5248782Sadrian * Redistribution and use in source and binary forms, with or without 6248782Sadrian * modification, are permitted provided that the following conditions 7248782Sadrian * are met: 8248782Sadrian * 1. Redistributions of source code must retain the above copyright 9248782Sadrian * notice, this list of conditions and the following disclaimer. 10248782Sadrian * 2. Redistributions in binary form must reproduce the above copyright 11248782Sadrian * notice, this list of conditions and the following disclaimer in the 12248782Sadrian * documentation and/or other materials provided with the distribution. 13248782Sadrian * 14248782Sadrian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15248782Sadrian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16248782Sadrian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17248782Sadrian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18248782Sadrian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19248782Sadrian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20248782Sadrian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21248782Sadrian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22248782Sadrian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23248782Sadrian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24248782Sadrian * SUCH DAMAGE. 25248782Sadrian */ 26248782Sadrian 27248782Sadrian#include <sys/cdefs.h> 28248782Sadrian__FBSDID("$FreeBSD$"); 29248782Sadrian 30248782Sadrian#include "opt_ddb.h" 31248782Sadrian 32248782Sadrian#include <sys/param.h> 33248782Sadrian#include <sys/conf.h> 34248782Sadrian#include <sys/kernel.h> 35248782Sadrian#include <sys/systm.h> 36248782Sadrian#include <sys/bus.h> 37248782Sadrian#include <sys/cons.h> 38248782Sadrian#include <sys/kdb.h> 39248782Sadrian#include <sys/reboot.h> 40248782Sadrian 41248782Sadrian#include <vm/vm.h> 42248782Sadrian#include <vm/vm_page.h> 43248782Sadrian 44248782Sadrian#include <net/ethernet.h> 45248782Sadrian 46248782Sadrian#include <machine/clock.h> 47248782Sadrian#include <machine/cpu.h> 48248782Sadrian#include <machine/cpuregs.h> 49248782Sadrian#include <machine/hwfunc.h> 50248782Sadrian#include <machine/md_var.h> 51248782Sadrian#include <machine/trap.h> 52248782Sadrian#include <machine/vmparam.h> 53248782Sadrian 54248782Sadrian#include <mips/atheros/ar71xxreg.h> 55248782Sadrian#include <mips/atheros/ar933xreg.h> 56248782Sadrian 57248782Sadrian#include <mips/atheros/ar71xx_cpudef.h> 58248782Sadrian#include <mips/atheros/ar71xx_setup.h> 59248782Sadrian 60248782Sadrian#include <mips/atheros/ar71xx_chip.h> 61248782Sadrian#include <mips/atheros/ar933x_chip.h> 62248782Sadrian 63248782Sadrianstatic void 64248782Sadrianar933x_chip_detect_mem_size(void) 65248782Sadrian{ 66248782Sadrian} 67248782Sadrian 68248782Sadrianstatic void 69248782Sadrianar933x_chip_detect_sys_frequency(void) 70248782Sadrian{ 71248782Sadrian uint32_t clock_ctrl; 72248782Sadrian uint32_t cpu_config; 73248782Sadrian uint32_t freq; 74248782Sadrian uint32_t t; 75248782Sadrian 76248782Sadrian t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP); 77248782Sadrian if (t & AR933X_BOOTSTRAP_REF_CLK_40) 78248782Sadrian u_ar71xx_refclk = (40 * 1000 * 1000); 79248782Sadrian else 80248782Sadrian u_ar71xx_refclk = (25 * 1000 * 1000); 81248782Sadrian 82248782Sadrian clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG); 83248782Sadrian if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { 84248782Sadrian u_ar71xx_cpu_freq = u_ar71xx_refclk; 85248782Sadrian u_ar71xx_ahb_freq = u_ar71xx_refclk; 86248782Sadrian u_ar71xx_ddr_freq = u_ar71xx_refclk; 87248782Sadrian } else { 88248782Sadrian cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG); 89248782Sadrian 90248782Sadrian t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & 91248782Sadrian AR933X_PLL_CPU_CONFIG_REFDIV_MASK; 92248782Sadrian freq = u_ar71xx_refclk / t; 93248782Sadrian 94248782Sadrian t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & 95248782Sadrian AR933X_PLL_CPU_CONFIG_NINT_MASK; 96248782Sadrian freq *= t; 97248782Sadrian 98248782Sadrian t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & 99248782Sadrian AR933X_PLL_CPU_CONFIG_OUTDIV_MASK; 100248782Sadrian if (t == 0) 101248782Sadrian t = 1; 102248782Sadrian 103248782Sadrian freq >>= t; 104248782Sadrian 105248782Sadrian t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & 106248782Sadrian AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; 107248782Sadrian u_ar71xx_cpu_freq = freq / t; 108248782Sadrian 109248782Sadrian t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & 110248782Sadrian AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; 111248782Sadrian u_ar71xx_ddr_freq = freq / t; 112248782Sadrian 113248782Sadrian t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & 114248782Sadrian AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; 115248782Sadrian u_ar71xx_ahb_freq = freq / t; 116248782Sadrian } 117253508Sadrian 118256490Sadrian /* 119256490Sadrian * On the AR933x, the UART frequency is the reference clock, 120255764Sadrian * not the AHB bus clock. 121255764Sadrian */ 122255764Sadrian u_ar71xx_uart_freq = u_ar71xx_refclk; 123255764Sadrian 124255764Sadrian /* 125256490Sadrian * XXX TODO: check whether the mdio frequency is always the 126256490Sadrian * refclock frequency, or whether it's variable like on the 127256490Sadrian * AR934x. 128256490Sadrian */ 129256490Sadrian u_ar71xx_mdio_freq = u_ar71xx_refclk; 130256490Sadrian 131256490Sadrian /* 132255764Sadrian * XXX check what the watchdog frequency should be? 133255764Sadrian */ 134253508Sadrian u_ar71xx_wdt_freq = u_ar71xx_ahb_freq; 135248782Sadrian} 136248782Sadrian 137248782Sadrianstatic void 138248782Sadrianar933x_chip_device_stop(uint32_t mask) 139248782Sadrian{ 140248809Sadrian uint32_t reg; 141248782Sadrian 142248782Sadrian reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE); 143248809Sadrian ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg | mask); 144248782Sadrian} 145248782Sadrian 146248782Sadrianstatic void 147248782Sadrianar933x_chip_device_start(uint32_t mask) 148248782Sadrian{ 149248809Sadrian uint32_t reg; 150248782Sadrian 151248782Sadrian reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE); 152248809Sadrian ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg & ~mask); 153248782Sadrian} 154248782Sadrian 155248782Sadrianstatic int 156248782Sadrianar933x_chip_device_stopped(uint32_t mask) 157248782Sadrian{ 158248782Sadrian uint32_t reg; 159248782Sadrian 160248782Sadrian reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE); 161248782Sadrian return ((reg & mask) == mask); 162248782Sadrian} 163248782Sadrian 164248782Sadrianstatic void 165248782Sadrianar933x_chip_set_mii_speed(uint32_t unit, uint32_t speed) 166248782Sadrian{ 167248782Sadrian 168248782Sadrian /* XXX TODO */ 169248782Sadrian return; 170248782Sadrian} 171248782Sadrian 172248782Sadrian/* 173248782Sadrian * XXX TODO !! 174248782Sadrian */ 175248782Sadrianstatic void 176248782Sadrianar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll) 177248782Sadrian{ 178248782Sadrian 179248782Sadrian switch (unit) { 180248782Sadrian case 0: 181248782Sadrian /* XXX TODO */ 182248782Sadrian break; 183248782Sadrian case 1: 184248782Sadrian /* XXX TODO */ 185248782Sadrian break; 186248782Sadrian default: 187248782Sadrian printf("%s: invalid PLL set for arge unit: %d\n", 188248782Sadrian __func__, unit); 189248782Sadrian return; 190248782Sadrian } 191248782Sadrian} 192248782Sadrian 193248782Sadrianstatic void 194285121Sadrianar933x_chip_ddr_flush(ar71xx_flush_ddr_id_t id) 195248782Sadrian{ 196248782Sadrian 197285121Sadrian switch (id) { 198285121Sadrian case AR71XX_CPU_DDR_FLUSH_GE0: 199248782Sadrian ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0); 200248782Sadrian break; 201285121Sadrian case AR71XX_CPU_DDR_FLUSH_GE1: 202248782Sadrian ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1); 203248782Sadrian break; 204285121Sadrian case AR71XX_CPU_DDR_FLUSH_USB: 205285121Sadrian ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_USB); 206285121Sadrian break; 207285121Sadrian case AR71XX_CPU_DDR_FLUSH_WMAC: 208285121Sadrian ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC); 209285121Sadrian break; 210248782Sadrian default: 211285121Sadrian printf("%s: invalid DDR flush id (%d)\n", __func__, id); 212285121Sadrian break; 213248782Sadrian } 214248782Sadrian} 215248782Sadrian 216248782Sadrian 217248782Sadrianstatic uint32_t 218248782Sadrianar933x_chip_get_eth_pll(unsigned int mac, int speed) 219248782Sadrian{ 220249123Sadrian uint32_t pll; 221248782Sadrian 222249123Sadrian switch (speed) { 223249123Sadrian case 10: 224249123Sadrian pll = AR933X_PLL_VAL_10; 225249123Sadrian break; 226249123Sadrian case 100: 227249123Sadrian pll = AR933X_PLL_VAL_100; 228249123Sadrian break; 229249123Sadrian case 1000: 230249123Sadrian pll = AR933X_PLL_VAL_1000; 231249123Sadrian break; 232249123Sadrian default: 233249123Sadrian printf("%s%d: invalid speed %d\n", __func__, mac, speed); 234249123Sadrian pll = 0; 235249123Sadrian } 236249123Sadrian return (pll); 237248782Sadrian} 238248782Sadrian 239248782Sadrianstatic void 240248782Sadrianar933x_chip_init_usb_peripheral(void) 241248782Sadrian{ 242249126Sadrian ar71xx_device_stop(AR933X_RESET_USBSUS_OVERRIDE); 243249126Sadrian DELAY(100); 244248782Sadrian 245249126Sadrian ar71xx_device_start(AR933X_RESET_USB_HOST); 246249126Sadrian DELAY(100); 247248782Sadrian 248249126Sadrian ar71xx_device_start(AR933X_RESET_USB_PHY); 249249126Sadrian DELAY(100); 250248782Sadrian} 251248782Sadrian 252256490Sadrianstatic void 253256490Sadrianar933x_configure_gmac(uint32_t gmac_cfg) 254256490Sadrian{ 255256490Sadrian uint32_t reg; 256256490Sadrian 257256490Sadrian reg = ATH_READ_REG(AR933X_GMAC_REG_ETH_CFG); 258256490Sadrian 259256490Sadrian /* 260256490Sadrian * The relevant bits here include: 261256490Sadrian * 262256490Sadrian * + AR933X_ETH_CFG_SW_PHY_SWAP 263256490Sadrian * + AR933X_ETH_CFG_SW_PHY_ADDR_SWAP 264256490Sadrian * 265256490Sadrian * There are other things; look at what openwrt exposes so 266256490Sadrian * it can be correctly exposed. 267256490Sadrian * 268256490Sadrian * TODO: what about ethernet switch support? How's that work? 269256490Sadrian */ 270256490Sadrian if (bootverbose) 271256490Sadrian printf("%s: GMAC config was 0x%08x\n", __func__, reg); 272256490Sadrian reg &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP); 273256490Sadrian reg |= gmac_cfg; 274256490Sadrian if (bootverbose) 275256490Sadrian printf("%s: GMAC setting is 0x%08x; register is now 0x%08x\n", 276256490Sadrian __func__, 277256490Sadrian gmac_cfg, 278256490Sadrian reg); 279256490Sadrian ATH_WRITE_REG(AR933X_GMAC_REG_ETH_CFG, reg); 280256490Sadrian} 281256490Sadrian 282256490Sadrianstatic void 283256490Sadrianar933x_chip_init_gmac(void) 284256490Sadrian{ 285256490Sadrian int val; 286256490Sadrian uint32_t gmac_cfg = 0; 287256490Sadrian 288256490Sadrian /* 289256490Sadrian * These two bits need a bit better explanation. 290256490Sadrian * 291256490Sadrian * The default configuration in the hardware is to map both 292256490Sadrian * ports to the internal switch. 293256490Sadrian * 294256490Sadrian * Here, GE0 == arge0, GE1 == arge1. 295256490Sadrian * 296256490Sadrian * The internal switch has: 297256490Sadrian * + 5 MAC ports, MAC0->MAC4. 298256490Sadrian * + 5 PHY ports, PHY0->PHY4, 299256490Sadrian * + MAC0 connects to GE1; 300256490Sadrian * + GE0 connects to PHY4; 301256490Sadrian * + The other mappings are MAC1->PHY0, MAC2->PHY1 .. MAC4->PHY3. 302256490Sadrian * 303256490Sadrian * The GE1 port is linked in via 1000MBit/full, supplying what is 304256490Sadrian * normally the 'WAN' switch ports. 305256490Sadrian * 306256490Sadrian * The switch is connected the MDIO bus on GE1. It looks like 307256490Sadrian * a normal AR7240 on-board switch. 308256490Sadrian * 309256490Sadrian * The GE0 port is connected via MII to PHY4, and can operate in 310256490Sadrian * 10/100mbit, full/half duplex. Ie, you can speak to PHY4 on 311256490Sadrian * the MDIO bus and everything will simply 'work'. 312256490Sadrian * 313256490Sadrian * So far so good. This looks just like an AR7240 SoC. 314256490Sadrian * 315256490Sadrian * However, some configurations will just expose one or two 316256490Sadrian * physical ports. In this case, some configuration bits can 317256490Sadrian * be set to tweak this. 318256490Sadrian * 319256490Sadrian * + CFG_SW_PHY_ADDR_SWAP swaps PHY port 0 with PHY port 4. 320256490Sadrian * Ie, GE0's PHY shows up as PHY 0. So if there's only 321256490Sadrian * one physical port, there's no need to involve the 322256490Sadrian * switch framework - it can just show up as a default, 323256490Sadrian * normal single PHY. 324256490Sadrian * 325256490Sadrian * + CFG_SW_PHY_SWAP swaps the internal switch connection 326256490Sadrian * between PHY0 and PHY4. Ie, PHY4 connects to MAc1, 327256490Sadrian * PHY0 connects to GE0. 328256490Sadrian */ 329256490Sadrian if ((resource_int_value("ar933x_gmac", 0, "override_phy", &val) == 0) 330256490Sadrian && (val == 0)) 331256490Sadrian return; 332256490Sadrian if ((resource_int_value("ar933x_gmac", 0, "swap_phy", &val) == 0) 333256490Sadrian && (val == 1)) 334256490Sadrian gmac_cfg |= AR933X_ETH_CFG_SW_PHY_SWAP; 335256490Sadrian if ((resource_int_value("ar933x_gmac", 0, "swap_phy_addr", &val) == 0) 336256490Sadrian && (val == 1)) 337256490Sadrian gmac_cfg |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP; 338256490Sadrian ar933x_configure_gmac(gmac_cfg); 339256490Sadrian} 340256490Sadrian 341248782Sadrianstruct ar71xx_cpu_def ar933x_chip_def = { 342248782Sadrian &ar933x_chip_detect_mem_size, 343248782Sadrian &ar933x_chip_detect_sys_frequency, 344248782Sadrian &ar933x_chip_device_stop, 345248782Sadrian &ar933x_chip_device_start, 346248782Sadrian &ar933x_chip_device_stopped, 347248782Sadrian &ar933x_chip_set_pll_ge, 348248782Sadrian &ar933x_chip_set_mii_speed, 349248782Sadrian &ar71xx_chip_set_mii_if, 350248782Sadrian &ar933x_chip_get_eth_pll, 351285121Sadrian &ar933x_chip_ddr_flush, 352256490Sadrian &ar933x_chip_init_usb_peripheral, 353256490Sadrian NULL, 354256490Sadrian NULL, 355256490Sadrian &ar933x_chip_init_gmac, 356248782Sadrian}; 357