/freebsd-10.2-release/contrib/llvm/lib/Target/R600/ |
H A D | SIRegisterInfo.cpp | 29 Reserved.set(AMDGPU::EXEC); 30 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR); 44 case AMDGPU::GPRF32RegClassID: 45 return &AMDGPU::VReg_32RegClass; 54 case MVT::i32: return &AMDGPU::VReg_32RegClass; 66 &AMDGPU::VReg_32RegClass, 67 &AMDGPU::SReg_32RegClass, 68 &AMDGPU::VReg_64RegClass, 69 &AMDGPU::SReg_64RegClass, 70 &AMDGPU [all...] |
H A D | R600RegisterInfo.cpp | 33 Reserved.set(AMDGPU::ZERO); 34 Reserved.set(AMDGPU::HALF); 35 Reserved.set(AMDGPU::ONE); 36 Reserved.set(AMDGPU::ONE_INT); 37 Reserved.set(AMDGPU::NEG_HALF); 38 Reserved.set(AMDGPU::NEG_ONE); 39 Reserved.set(AMDGPU::PV_X); 40 Reserved.set(AMDGPU::ALU_LITERAL_X); 41 Reserved.set(AMDGPU::ALU_CONST); 42 Reserved.set(AMDGPU [all...] |
H A D | AMDGPURegisterInfo.cpp | 1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===// 30 const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister; 51 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4, 52 AMDGPU::sub5, AMDGPU::sub6, AMDGPU [all...] |
H A D | SIInstrInfo.cpp | 47 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); 50 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 51 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU [all...] |
H A D | SILowerControlFlow.cpp | 51 #include "AMDGPU.h" 115 case AMDGPU::DS_ADD_U32_RTN: 116 case AMDGPU::DS_SUB_U32_RTN: 117 case AMDGPU::DS_WRITE_B32: 118 case AMDGPU::DS_WRITE_B8: 119 case AMDGPU::DS_WRITE_B16: 120 case AMDGPU::DS_READ_B32: 121 case AMDGPU::DS_READ_I8: 122 case AMDGPU::DS_READ_U8: 123 case AMDGPU [all...] |
H A D | R600InstrInfo.cpp | 16 #include "AMDGPU.h" 55 if (AMDGPU::R600_Reg128RegClass.contains(DestReg) && 56 AMDGPU::R600_Reg128RegClass.contains(SrcReg)) { 58 } else if(AMDGPU::R600_Reg64RegClass.contains(DestReg) && 59 AMDGPU::R600_Reg64RegClass.contains(SrcReg)) { 66 buildDefaultInstruction(MBB, MI, AMDGPU::MOV, 73 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV, 75 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0)) 93 return AMDGPU::SETE_INT; 101 case AMDGPU [all...] |
H A D | R600ExpandSpecialInstrs.cpp | 17 #include "AMDGPU.h" 73 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); 77 DstOp.getReg(), AMDGPU::OQAP); 78 DstOp.setReg(AMDGPU::OQAP); 80 AMDGPU::OpName::pred_sel); 82 AMDGPU::OpName::pred_sel); 91 case AMDGPU::PRED_X: { 99 AMDGPU::ZERO); // src1 102 TII->setImmOperand(PredSet, AMDGPU::OpName::update_exec_mask, 1); 104 TII->setImmOperand(PredSet, AMDGPU [all...] |
H A D | R600EmitClauseMarkers.cpp | 17 #include "AMDGPU.h" 39 case AMDGPU::INTERP_PAIR_XY: 40 case AMDGPU::INTERP_PAIR_ZW: 41 case AMDGPU::INTERP_VEC_LOAD: 42 case AMDGPU::DOT_4: 44 case AMDGPU::KILL: 64 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X) 76 case AMDGPU::PRED_X: 77 case AMDGPU::INTERP_PAIR_XY: 78 case AMDGPU [all...] |
H A D | R600ClauseMergePass.cpp | 17 #include "AMDGPU.h" 34 case AMDGPU::CF_ALU: 35 case AMDGPU::CF_ALU_PUSH_BEFORE: 75 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm(); 81 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::Enabled)).getImm(); 86 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); 105 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); 113 if (RootCFAlu->getOpcode() == AMDGPU [all...] |
H A D | R600ControlFlowFinalizer.cpp | 17 #include "AMDGPU.h" 58 case AMDGPU::KILL: 59 case AMDGPU::RETURN: 71 Opcode = isEg ? AMDGPU::CF_TC_EG : AMDGPU::CF_TC_R600; 74 Opcode = isEg ? AMDGPU::CF_VC_EG : AMDGPU::CF_VC_R600; 77 Opcode = isEg ? AMDGPU::CF_CALL_FS_EG : AMDGPU::CF_CALL_FS_R600; 80 Opcode = isEg ? AMDGPU [all...] |
H A D | R600MachineScheduler.cpp | 163 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X) 183 if (MI->getOpcode() != AMDGPU::COPY) 226 case AMDGPU::PRED_X: 228 case AMDGPU::INTERP_PAIR_XY: 229 case AMDGPU::INTERP_PAIR_ZW: 230 case AMDGPU::INTERP_VEC_LOAD: 231 case AMDGPU::DOT_4: 233 case AMDGPU::COPY: 248 MI->getOpcode() == AMDGPU::GROUP_BARRIER) { 259 case AMDGPU [all...] |
H A D | AMDGPUInstrInfo.cpp | 96 case AMDGPU::BRANCH_COND_i32: 97 case AMDGPU::BRANCH_COND_f32: 98 case AMDGPU::BRANCH: 128 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::addr); 133 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::chan); 137 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst); 142 if (OffsetReg == AMDGPU [all...] |
H A D | AMDGPUAsmPrinter.cpp | 1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===// 21 #include "AMDGPU.h" 64 const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config", 88 OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm", 119 if (MI.getOpcode() == AMDGPU::KILLGT) 196 if (reg == AMDGPU::VCC) { 203 case AMDGPU::SCC: 204 case AMDGPU::EXEC: 205 case AMDGPU::M0: 209 if (AMDGPU [all...] |
H A D | R600ISelLowering.cpp | 32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass); 33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass); 34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass); 35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass); 36 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass); 37 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass); 140 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst); 147 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode()))); 155 case AMDGPU::CLAMP_R600: { 157 AMDGPU [all...] |
H A D | SIISelLowering.cpp | 16 #include "AMDGPU.h" 34 addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass); 35 addRegisterClass(MVT::i64, &AMDGPU::VSrc_64RegClass); 37 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); 38 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); 40 addRegisterClass(MVT::i32, &AMDGPU::VSrc_32RegClass); 41 addRegisterClass(MVT::f32, &AMDGPU::VSrc_32RegClass); 43 addRegisterClass(MVT::f64, &AMDGPU::VSrc_64RegClass); 44 addRegisterClass(MVT::v2i32, &AMDGPU::VSrc_64RegClass); 45 addRegisterClass(MVT::v2f32, &AMDGPU [all...] |
H A D | R600Packetizer.cpp | 19 #include "AMDGPU.h" 88 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write); 91 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); 97 Result[Dst] = AMDGPU::PS; 100 if (BI->getOpcode() == AMDGPU::DOT4_r600 || 101 BI->getOpcode() == AMDGPU::DOT4_eg) { 102 Result[Dst] = AMDGPU::PV_X; 105 if (Dst == AMDGPU::OQAP) { 111 PVReg = AMDGPU::PV_X; 114 PVReg = AMDGPU [all...] |
H A D | AMDGPUISelDAGToDAG.cpp | 11 /// \brief Defines an instruction selector for the AMDGPU target. 36 /// AMDGPU specific code to select AMDGPU machine instructions for 39 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can 92 /// \brief This pass converts a legalized DAG into a AMDGPU-specific 127 case AMDGPU::REG_SEQUENCE: { 229 case 1: RegClassID = UseVReg ? AMDGPU::VReg_32RegClassID : 230 AMDGPU::SReg_32RegClassID; 232 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID : 233 AMDGPU [all...] |
H A D | SIFixSGPRCopies.cpp | 69 #include "AMDGPU.h" 147 case AMDGPU::COPY: 168 if (Def->getOpcode() != AMDGPU::COPY) { 187 DstRC == &AMDGPU::M0RegRegClass) 207 if (MI.getOpcode() == AMDGPU::COPY && isVGPRToSGPRCopy(MI, TRI, MRI)) { 216 case AMDGPU::PHI: { 229 if (TRI->getCommonSubClass(RC, &AMDGPU::VReg_32RegClass)) { 230 MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass); 248 case AMDGPU::REG_SEQUENCE: {
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H A D | AMDILCFGStructurizer.cpp | 13 #include "AMDGPU.h" 259 /// because the AMDGPU instruction is not recognized as terminator fix this 439 if (I->getOpcode() == AMDGPU::PRED_X) { 533 case AMDGPU::JUMP_COND: 534 case AMDGPU::JUMP: return AMDGPU::IF_PREDICATE_SET; 535 case AMDGPU::BRANCH_COND_i32: 536 case AMDGPU::BRANCH_COND_f32: return AMDGPU::IF_LOGICALNZ_f32; 544 case AMDGPU [all...] |
H A D | AMDGPUInstrInfo.h | 1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===// 29 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT 30 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT 31 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE 32 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE 203 namespace AMDGPU { namespace in namespace:llvm 205 } // End namespace AMDGPU
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H A D | SIInsertWaits.cpp | 19 #include "AMDGPU.h" 132 (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore())); 170 if (MI.getOpcode() == AMDGPU::EXP) 221 ExpInstrTypesSeen |= MI.getOpcode() == AMDGPU::EXP ? 1 : 2; 249 if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM) 298 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT)) 320 if (MI.getOpcode() == AMDGPU::S_SENDMSG)
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H A D | R600OptimizeVectorRegisters.cpp | 32 #include "AMDGPU.h" 66 assert (MI->getOpcode() == AMDGPU::REG_SEQUENCE); 135 case AMDGPU::R600_ExportSwz: 136 case AMDGPU::EG_ExportSwz: 189 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 194 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG), 211 Pos = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg) 328 if (MI->getOpcode() != AMDGPU::REG_SEQUENCE) {
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/freebsd-10.2-release/contrib/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | R600MCCodeEmitter.cpp | 92 if (MI.getOpcode() == AMDGPU::RETURN || 93 MI.getOpcode() == AMDGPU::FETCH_CLAUSE || 94 MI.getOpcode() == AMDGPU::ALU_CLAUSE || 95 MI.getOpcode() == AMDGPU::BUNDLE || 96 MI.getOpcode() == AMDGPU::KILL) { 101 if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) { 134 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
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H A D | SIMCCodeEmitter.cpp | 78 return (AMDGPU::SSrc_32RegClassID == RegClass) || 79 (AMDGPU::SSrc_64RegClassID == RegClass) || 80 (AMDGPU::VSrc_32RegClassID == RegClass) || 81 (AMDGPU::VSrc_64RegClassID == RegClass);
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/freebsd-10.2-release/contrib/llvm/lib/Target/R600/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===// 28 case AMDGPU::VCC: 31 case AMDGPU::SCC: 34 case AMDGPU::EXEC: 37 case AMDGPU::M0: 90 case AMDGPU::PRED_SEL_OFF:
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