Lines Matching refs:AMDGPU
16 #include "AMDGPU.h"
34 addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
35 addRegisterClass(MVT::i64, &AMDGPU::VSrc_64RegClass);
37 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
38 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
40 addRegisterClass(MVT::i32, &AMDGPU::VSrc_32RegClass);
41 addRegisterClass(MVT::f32, &AMDGPU::VSrc_32RegClass);
43 addRegisterClass(MVT::f64, &AMDGPU::VSrc_64RegClass);
44 addRegisterClass(MVT::v2i32, &AMDGPU::VSrc_64RegClass);
45 addRegisterClass(MVT::v2f32, &AMDGPU::VSrc_64RegClass);
47 addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass);
48 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
49 addRegisterClass(MVT::i128, &AMDGPU::SReg_128RegClass);
51 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
52 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
54 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
55 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
173 MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
249 CCInfo.AllocateReg(AMDGPU::VGPR0);
250 CCInfo.AllocateReg(AMDGPU::VGPR1);
255 CCInfo.AllocateReg(AMDGPU::SGPR0);
256 CCInfo.AllocateReg(AMDGPU::SGPR1);
257 MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
294 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
295 &AMDGPU::SReg_64RegClass);
296 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
343 case AMDGPU::BRANCH: return BB;
344 case AMDGPU::SI_ADDR64_RSRC: {
349 unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
350 unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
351 unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
352 unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
353 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
355 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
357 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
359 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
361 .addImm(AMDGPU::sub0)
363 .addImm(AMDGPU::sub1);
364 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
366 .addImm(AMDGPU::sub0_sub1)
368 .addImm(AMDGPU::sub2_sub3);
372 case AMDGPU::V_SUB_F64: {
375 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64),
387 case AMDGPU::SI_RegisterStorePseudo: {
391 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
393 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
493 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
494 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 0), VT);
496 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
497 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 1), VT);
499 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
500 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 2), VT);
502 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
503 AMDGPU::VGPR0, VT);
505 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
506 AMDGPU::VGPR1, VT);
508 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
509 AMDGPU::VGPR2, VT);
895 return AMDGPU::VSrc_32RegClassID == RegClass ||
896 AMDGPU::VSrc_64RegClassID == RegClass;
901 return AMDGPU::SSrc_32RegClassID == RegClass ||
902 AMDGPU::SSrc_64RegClassID == RegClass;
999 case AMDGPU::COPY_TO_REGCLASS:
1006 if (OpClassID == AMDGPU::VSrc_32RegClassID ||
1007 OpClassID == AMDGPU::VSrc_64RegClassID) {
1011 case AMDGPU::EXTRACT_SUBREG: {
1017 case AMDGPU::REG_SEQUENCE:
1043 if (RegClass == AMDGPU::VSrc_32RegClassID)
1044 RegClass = AMDGPU::VReg_32RegClassID;
1045 else if (RegClass == AMDGPU::VSrc_64RegClassID)
1046 RegClass = AMDGPU::VReg_64RegClassID;
1100 int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
1227 case AMDGPU::sub0: return 0;
1228 case AMDGPU::sub1: return 1;
1229 case AMDGPU::sub2: return 2;
1230 case AMDGPU::sub3: return 3;
1287 SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
1296 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1307 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1308 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1309 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1345 case 1: RC = &AMDGPU::VReg_32RegClass; break;
1346 case 2: RC = &AMDGPU::VReg_64RegClass; break;
1347 case 3: RC = &AMDGPU::VReg_96RegClass; break;
1364 case AMDGPU::S_LOAD_DWORD_IMM:
1365 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1367 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1369 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1372 case AMDGPU::S_LOAD_DWORDX4_IMM:
1373 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1375 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1377 if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
1382 SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,