1249259Sdim//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief R600 implementation of the TargetRegisterInfo class. 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdim#include "R600RegisterInfo.h" 16249259Sdim#include "AMDGPUTargetMachine.h" 17249259Sdim#include "R600Defines.h" 18249259Sdim#include "R600InstrInfo.h" 19249259Sdim#include "R600MachineFunctionInfo.h" 20249259Sdim 21249259Sdimusing namespace llvm; 22249259Sdim 23263508SdimR600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm) 24263508Sdim: AMDGPURegisterInfo(tm), 25263508Sdim TM(tm) 26263508Sdim { RCW.RegWeight = 0; RCW.WeightLimit = 0;} 27249259Sdim 28249259SdimBitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 29249259Sdim BitVector Reserved(getNumRegs()); 30249259Sdim 31263508Sdim const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo()); 32263508Sdim 33249259Sdim Reserved.set(AMDGPU::ZERO); 34249259Sdim Reserved.set(AMDGPU::HALF); 35249259Sdim Reserved.set(AMDGPU::ONE); 36249259Sdim Reserved.set(AMDGPU::ONE_INT); 37249259Sdim Reserved.set(AMDGPU::NEG_HALF); 38249259Sdim Reserved.set(AMDGPU::NEG_ONE); 39249259Sdim Reserved.set(AMDGPU::PV_X); 40249259Sdim Reserved.set(AMDGPU::ALU_LITERAL_X); 41249259Sdim Reserved.set(AMDGPU::ALU_CONST); 42249259Sdim Reserved.set(AMDGPU::PREDICATE_BIT); 43249259Sdim Reserved.set(AMDGPU::PRED_SEL_OFF); 44249259Sdim Reserved.set(AMDGPU::PRED_SEL_ZERO); 45249259Sdim Reserved.set(AMDGPU::PRED_SEL_ONE); 46263508Sdim Reserved.set(AMDGPU::INDIRECT_BASE_ADDR); 47249259Sdim 48249259Sdim for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(), 49249259Sdim E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) { 50249259Sdim Reserved.set(*I); 51249259Sdim } 52249259Sdim 53263508Sdim TII->reserveIndirectRegisters(Reserved, MF); 54249259Sdim 55249259Sdim return Reserved; 56249259Sdim} 57249259Sdim 58249259Sdimconst TargetRegisterClass * 59249259SdimR600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const { 60249259Sdim switch (rc->getID()) { 61249259Sdim case AMDGPU::GPRF32RegClassID: 62249259Sdim case AMDGPU::GPRI32RegClassID: 63249259Sdim return &AMDGPU::R600_Reg32RegClass; 64249259Sdim default: return rc; 65249259Sdim } 66249259Sdim} 67249259Sdim 68249259Sdimunsigned R600RegisterInfo::getHWRegChan(unsigned reg) const { 69249259Sdim return this->getEncodingValue(reg) >> HW_CHAN_SHIFT; 70249259Sdim} 71249259Sdim 72263508Sdimunsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const { 73263508Sdim return GET_REG_INDEX(getEncodingValue(Reg)); 74263508Sdim} 75263508Sdim 76249259Sdimconst TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( 77249259Sdim MVT VT) const { 78249259Sdim switch(VT.SimpleTy) { 79249259Sdim default: 80249259Sdim case MVT::i32: return &AMDGPU::R600_TReg32RegClass; 81249259Sdim } 82249259Sdim} 83249259Sdim 84263508Sdimconst RegClassWeight &R600RegisterInfo::getRegClassWeight( 85263508Sdim const TargetRegisterClass *RC) const { 86263508Sdim return RCW; 87263508Sdim} 88263508Sdim 89263508Sdimbool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const { 90263508Sdim assert(!TargetRegisterInfo::isVirtualRegister(Reg)); 91263508Sdim 92263508Sdim switch (Reg) { 93263508Sdim case AMDGPU::OQAP: 94263508Sdim case AMDGPU::OQBP: 95263508Sdim case AMDGPU::AR_X: 96263508Sdim return false; 97263508Sdim default: 98263508Sdim return true; 99249259Sdim } 100249259Sdim} 101