Lines Matching refs:AMDGPU
163 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
183 if (MI->getOpcode() != AMDGPU::COPY)
226 case AMDGPU::PRED_X:
228 case AMDGPU::INTERP_PAIR_XY:
229 case AMDGPU::INTERP_PAIR_ZW:
230 case AMDGPU::INTERP_VEC_LOAD:
231 case AMDGPU::DOT_4:
233 case AMDGPU::COPY:
248 MI->getOpcode() == AMDGPU::GROUP_BARRIER) {
259 case AMDGPU::sub0:
261 case AMDGPU::sub1:
263 case AMDGPU::sub2:
265 case AMDGPU::sub3:
273 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) ||
274 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass))
276 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass))
278 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass))
280 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass))
282 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass))
304 case AMDGPU::PRED_X:
305 case AMDGPU::COPY:
306 case AMDGPU::CONST_COPY:
307 case AMDGPU::INTERP_PAIR_XY:
308 case AMDGPU::INTERP_PAIR_ZW:
309 case AMDGPU::INTERP_VEC_LOAD:
310 case AMDGPU::DOT_4:
357 int DstIndex = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
374 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass);
377 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass);
380 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass);
383 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_WRegClass);