Lines Matching refs:AMDGPU
29 Reserved.set(AMDGPU::EXEC);
30 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
44 case AMDGPU::GPRF32RegClassID:
45 return &AMDGPU::VReg_32RegClass;
54 case MVT::i32: return &AMDGPU::VReg_32RegClass;
66 &AMDGPU::VReg_32RegClass,
67 &AMDGPU::SReg_32RegClass,
68 &AMDGPU::VReg_64RegClass,
69 &AMDGPU::SReg_64RegClass,
70 &AMDGPU::SReg_128RegClass,
71 &AMDGPU::SReg_256RegClass
91 return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
92 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
93 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
94 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
95 getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
96 getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
103 } else if (SRC == &AMDGPU::SCCRegRegClass) {
104 return &AMDGPU::VCCRegRegClass;
105 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
106 return &AMDGPU::VReg_32RegClass;
107 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
108 return &AMDGPU::VReg_64RegClass;
109 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
110 return &AMDGPU::VReg_128RegClass;
111 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
112 return &AMDGPU::VReg_256RegClass;
113 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
114 return &AMDGPU::VReg_512RegClass;
121 if (SubIdx == AMDGPU::NoSubRegister)
127 return &AMDGPU::SGPR_32RegClass;
129 return &AMDGPU::VGPR_32RegClass;