Target/R600/R600ExpandSpecialInstrs.cpp

17 #include "AMDGPU.h"
73         int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
77                                                DstOp.getReg(), AMDGPU::OQAP);
78         DstOp.setReg(AMDGPU::OQAP);
80                                            AMDGPU::OpName::pred_sel);
82                                            AMDGPU::OpName::pred_sel);
91       case AMDGPU::PRED_X: {
99                                             AMDGPU::ZERO);             // src1
102           TII->setImmOperand(PredSet, AMDGPU::OpName::update_exec_mask, 1);
104           TII->setImmOperand(PredSet, AMDGPU::OpName::update_pred, 1);
110       case AMDGPU::INTERP_PAIR_XY: {
112         unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
121             DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
123           BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY,
139       case AMDGPU::INTERP_PAIR_ZW: {
141         unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
148             DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
152           BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_ZW,
168       case AMDGPU::INTERP_VEC_LOAD: {
171         unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
176           BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_LOAD_P0,
188       case AMDGPU::DOT_4: {
198               AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
213               TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
216               TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
263                             TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg();
265                            TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg();
270           int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1);
298           DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
307         case AMDGPU::CUBE_r600_pseudo:
308           Opcode = AMDGPU::CUBE_r600_real;
310         case AMDGPU::CUBE_eg_pseudo:
311           Opcode = AMDGPU::CUBE_eg_real;