Lines Matching refs:AMDGPU
32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
37 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
140 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
147 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
155 case AMDGPU::CLAMP_R600: {
157 AMDGPU::MOV,
164 case AMDGPU::FABS_R600: {
166 AMDGPU::MOV,
173 case AMDGPU::FNEG_R600: {
175 AMDGPU::MOV,
182 case AMDGPU::MASK_WRITE: {
190 case AMDGPU::MOV_IMM_F32:
195 case AMDGPU::MOV_IMM_I32:
199 case AMDGPU::CONST_COPY: {
200 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
201 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
202 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
207 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
208 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
209 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
210 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
219 case AMDGPU::TXD: {
220 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
221 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
257 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
276 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
295 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
320 case AMDGPU::TXD_SHADOW: {
321 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
322 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
359 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
378 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
397 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
422 case AMDGPU::BRANCH:
423 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
427 case AMDGPU::BRANCH_COND_f32: {
429 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
430 AMDGPU::PREDICATE_BIT)
435 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
437 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
441 case AMDGPU::BRANCH_COND_i32: {
443 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
444 AMDGPU::PREDICATE_BIT)
449 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
451 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
455 case AMDGPU::EG_ExportSwz:
456 case AMDGPU::R600_ExportSwz: {
463 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
464 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
473 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
476 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
489 case AMDGPU::RETURN: {
526 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
560 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
576 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
584 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
585 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
594 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
598 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
611 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
615 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
736 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
737 AMDGPU::T1_X, VT);
739 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
740 AMDGPU::T1_Y, VT);
742 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
743 AMDGPU::T1_Z, VT);
745 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
746 AMDGPU::T0_X, VT);
748 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
749 AMDGPU::T0_Y, VT);
751 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
752 AMDGPU::T0_Z, VT);
1364 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
1721 case AMDGPU::FNEG_R600:
1727 case AMDGPU::FABS_R600:
1733 case AMDGPU::CONST_COPY: {
1735 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
1746 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
1747 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
1748 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2),
1749 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
1750 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
1751 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
1752 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
1753 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
1754 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
1755 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
1756 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
1770 if (Reg->getReg() == AMDGPU::ALU_CONST) {
1785 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
1788 case AMDGPU::MOV_IMM_I32:
1789 case AMDGPU::MOV_IMM_F32: {
1790 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
1794 if (Src.getMachineOpcode() == AMDGPU::MOV_IMM_F32) {
1798 ImmReg = AMDGPU::ZERO;
1800 ImmReg = AMDGPU::HALF;
1802 ImmReg = AMDGPU::ONE;
1810 ImmReg = AMDGPU::ZERO;
1812 ImmReg = AMDGPU::ONE_INT;
1821 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
1854 if (Opcode == AMDGPU::DOT_4) {
1856 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
1857 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
1858 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
1859 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
1860 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
1861 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
1862 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
1863 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
1866 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X),
1867 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y),
1868 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Z),
1869 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_W),
1870 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_X),
1871 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Y),
1872 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Z),
1873 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_W)
1876 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_X),
1877 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Y),
1878 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Z),
1879 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_W),
1880 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_X),
1881 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Y),
1882 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Z),
1883 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_W)
1891 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
1899 } else if (Opcode == AMDGPU::REG_SEQUENCE) {
1905 } else if (Opcode == AMDGPU::CLAMP_R600) {
1911 AMDGPU::OpName::clamp);
1925 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
1926 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
1927 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2)
1930 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg),
1931 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg),
1932 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_neg)
1935 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs),
1936 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs),
1946 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
1948 int ImmIdx = TII->getOperandIdx(Opcode, AMDGPU::OpName::literal);