Lines Matching refs:AMDGPU
11 /// \brief Defines an instruction selector for the AMDGPU target.
36 /// AMDGPU specific code to select AMDGPU machine instructions for
39 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
92 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
127 case AMDGPU::REG_SEQUENCE: {
229 case 1: RegClassID = UseVReg ? AMDGPU::VReg_32RegClassID :
230 AMDGPU::SReg_32RegClassID;
232 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
233 AMDGPU::SReg_64RegClassID;
235 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
236 AMDGPU::SReg_128RegClassID;
238 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
239 AMDGPU::SReg_256RegClassID;
241 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
242 AMDGPU::SReg_512RegClassID;
252 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
253 case 4: RegClassID = AMDGPU::R600_Reg128RegClassID; break;
261 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS,
287 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
297 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
298 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
299 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
301 RC = CurDAG->getTargetConstant(AMDGPU::VSrc_64RegClassID, MVT::i32);
302 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
303 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
325 return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, SDLoc(N),
342 return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, SDLoc(N),
441 return "AMDGPU DAG->DAG Pattern Instruction Selection";
488 AMDGPU::ZERO, MVT::i32);
504 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);