Lines Matching refs:AMDGPU
47 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
50 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
51 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
52 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
53 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
57 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
58 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
62 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
66 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
70 AMDGPU::sub0, AMDGPU::sub1, 0
76 if (AMDGPU::M0 == DestReg) {
81 if (!I->definesRegister(AMDGPU::M0))
85 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
96 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
97 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
98 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
102 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
103 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
104 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
108 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
109 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
110 Opcode = AMDGPU::S_MOV_B32;
113 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
114 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
115 Opcode = AMDGPU::S_MOV_B32;
118 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
119 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
120 Opcode = AMDGPU::S_MOV_B32;
123 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
124 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
125 AMDGPU::SReg_32RegClass.contains(SrcReg));
126 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
130 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
131 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
132 AMDGPU::SReg_64RegClass.contains(SrcReg));
133 Opcode = AMDGPU::V_MOV_B32_e32;
136 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
137 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
138 Opcode = AMDGPU::V_MOV_B32_e32;
141 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
142 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
143 AMDGPU::SReg_128RegClass.contains(SrcReg));
144 Opcode = AMDGPU::V_MOV_B32_e32;
147 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
148 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
149 AMDGPU::SReg_256RegClass.contains(SrcReg));
150 Opcode = AMDGPU::V_MOV_B32_e32;
153 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
154 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
155 AMDGPU::SReg_512RegClass.contains(SrcReg));
156 Opcode = AMDGPU::V_MOV_B32_e32;
178 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
182 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
209 (MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
210 AMDGPU::OpName::abs)).getImm() ||
211 MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
212 AMDGPU::OpName::neg)).getImm()))
232 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
239 case AMDGPU::S_MOV_B32:
240 case AMDGPU::S_MOV_B64:
241 case AMDGPU::V_MOV_B32_e32:
242 case AMDGPU::V_MOV_B32_e64:
249 return RC != &AMDGPU::EXECRegRegClass;
305 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
306 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
307 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
312 unsigned SGPRUsed = AMDGPU::NoRegister;
319 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
323 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
325 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
326 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
372 default: return AMDGPU::INSTRUCTION_LIST_END;
373 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
374 case AMDGPU::COPY: return AMDGPU::COPY;
375 case AMDGPU::PHI: return AMDGPU::PHI;
376 case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;
377 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
378 case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
379 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
380 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
381 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
382 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
383 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
384 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
385 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
390 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
407 case AMDGPU::COPY:
408 case AMDGPU::REG_SEQUENCE:
421 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
423 Opcode = AMDGPU::COPY;
425 Opcode = AMDGPU::S_MOV_B32;
437 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
438 AMDGPU::OpName::src0);
439 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
440 AMDGPU::OpName::src1);
441 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
442 AMDGPU::OpName::src2);
451 bool ReadsVCC = MI->readsRegister(AMDGPU::VCC, &RI);
480 unsigned SGPRReg = AMDGPU::NoRegister;
491 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
493 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
512 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
547 get(AMDGPU::COPY), DstReg)
561 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END)
575 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
604 case AMDGPU::COPY:
605 case AMDGPU::PHI:
606 case AMDGPU::REG_SEQUENCE:
642 return &AMDGPU::VReg_32RegClass;
651 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
654 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
669 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
672 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
691 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
694 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
697 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
700 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
703 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
706 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));