Lines Matching refs:AMDGPU
33 Reserved.set(AMDGPU::ZERO);
34 Reserved.set(AMDGPU::HALF);
35 Reserved.set(AMDGPU::ONE);
36 Reserved.set(AMDGPU::ONE_INT);
37 Reserved.set(AMDGPU::NEG_HALF);
38 Reserved.set(AMDGPU::NEG_ONE);
39 Reserved.set(AMDGPU::PV_X);
40 Reserved.set(AMDGPU::ALU_LITERAL_X);
41 Reserved.set(AMDGPU::ALU_CONST);
42 Reserved.set(AMDGPU::PREDICATE_BIT);
43 Reserved.set(AMDGPU::PRED_SEL_OFF);
44 Reserved.set(AMDGPU::PRED_SEL_ZERO);
45 Reserved.set(AMDGPU::PRED_SEL_ONE);
46 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
48 for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
49 E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
61 case AMDGPU::GPRF32RegClassID:
62 case AMDGPU::GPRI32RegClassID:
63 return &AMDGPU::R600_Reg32RegClass;
80 case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
93 case AMDGPU::OQAP:
94 case AMDGPU::OQBP:
95 case AMDGPU::AR_X: