Lines Matching refs:AMDGPU
51 #include "AMDGPU.h"
115 case AMDGPU::DS_ADD_U32_RTN:
116 case AMDGPU::DS_SUB_U32_RTN:
117 case AMDGPU::DS_WRITE_B32:
118 case AMDGPU::DS_WRITE_B8:
119 case AMDGPU::DS_WRITE_B16:
120 case AMDGPU::DS_READ_B32:
121 case AMDGPU::DS_READ_I8:
122 case AMDGPU::DS_READ_U8:
123 case AMDGPU::DS_READ_I16:
124 case AMDGPU::DS_READ_U16:
155 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
157 .addReg(AMDGPU::EXEC);
174 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
176 .addReg(AMDGPU::EXEC);
179 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
185 .addReg(AMDGPU::VGPR0)
186 .addReg(AMDGPU::VGPR0)
187 .addReg(AMDGPU::VGPR0)
188 .addReg(AMDGPU::VGPR0);
191 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
200 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
203 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
204 .addReg(AMDGPU::EXEC)
219 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
222 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
223 .addReg(AMDGPU::EXEC)
238 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
239 .addReg(AMDGPU::EXEC)
253 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
268 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
280 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
281 .addReg(AMDGPU::EXEC)
284 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
286 .addReg(AMDGPU::EXEC);
297 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
298 .addReg(AMDGPU::EXEC)
325 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
341 if (AMDGPU::SReg_32RegClass.contains(Idx)) {
342 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
349 assert(AMDGPU::SReg_64RegClass.contains(Save));
350 assert(AMDGPU::VReg_32RegClass.contains(Idx));
353 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save)
354 .addReg(AMDGPU::EXEC);
357 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32_e32), AMDGPU::VCC)
361 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
362 .addReg(AMDGPU::VCC);
365 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
366 .addReg(AMDGPU::M0)
370 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
371 .addReg(AMDGPU::VCC);
377 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
378 .addReg(AMDGPU::EXEC)
379 .addReg(AMDGPU::VCC);
382 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
384 .addReg(AMDGPU::EXEC);
387 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
401 unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0);
406 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
408 .addReg(AMDGPU::M0, RegState::Implicit)
422 unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0);
427 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
430 .addReg(AMDGPU::M0, RegState::Implicit)
462 case AMDGPU::SI_IF:
467 case AMDGPU::SI_ELSE:
471 case AMDGPU::SI_BREAK:
475 case AMDGPU::SI_IF_BREAK:
479 case AMDGPU::SI_ELSE_BREAK:
483 case AMDGPU::SI_LOOP:
488 case AMDGPU::SI_END_CF:
496 case AMDGPU::SI_KILL:
504 case AMDGPU::S_BRANCH:
508 case AMDGPU::SI_INDIRECT_SRC:
512 case AMDGPU::SI_INDIRECT_DST_V1:
513 case AMDGPU::SI_INDIRECT_DST_V2:
514 case AMDGPU::SI_INDIRECT_DST_V4:
515 case AMDGPU::SI_INDIRECT_DST_V8:
516 case AMDGPU::SI_INDIRECT_DST_V16:
520 case AMDGPU::V_INTERP_P1_F32:
521 case AMDGPU::V_INTERP_P2_F32:
522 case AMDGPU::V_INTERP_MOV_F32:
534 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_MOV_B32),
535 AMDGPU::M0).addImm(0xffffffff);
540 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
541 AMDGPU::EXEC).addReg(AMDGPU::EXEC);