Lines Matching refs:AMDGPU
16 #include "AMDGPU.h"
55 if (AMDGPU::R600_Reg128RegClass.contains(DestReg) &&
56 AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
58 } else if(AMDGPU::R600_Reg64RegClass.contains(DestReg) &&
59 AMDGPU::R600_Reg64RegClass.contains(SrcReg)) {
66 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
73 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
75 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
93 return AMDGPU::SETE_INT;
101 case AMDGPU::MOV:
102 case AMDGPU::MOV_IMM_F32:
103 case AMDGPU::MOV_IMM_I32:
114 case AMDGPU::RETURN:
126 case AMDGPU::CUBE_r600_pseudo:
127 case AMDGPU::CUBE_r600_real:
128 case AMDGPU::CUBE_eg_pseudo:
129 case AMDGPU::CUBE_eg_real:
157 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1;
161 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1;
170 case AMDGPU::PRED_X:
171 case AMDGPU::INTERP_PAIR_XY:
172 case AMDGPU::INTERP_PAIR_ZW:
173 case AMDGPU::INTERP_VEC_LOAD:
174 case AMDGPU::COPY:
175 case AMDGPU::DOT_4:
185 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
193 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
225 case AMDGPU::KILLGT:
226 case AMDGPU::GROUP_BARRIER:
234 return MI->findRegisterUseOperandIdx(AMDGPU::AR_X) != -1;
238 return MI->findRegisterDefOperandIdx(AMDGPU::AR_X) != -1;
251 if (AMDGPU::R600_LDS_SRC_REGRegClass.contains(I->getReg()))
259 AMDGPU::OpName::src0,
260 AMDGPU::OpName::src1,
261 AMDGPU::OpName::src2
271 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
272 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
273 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
274 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
275 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
276 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
277 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
278 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
279 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
280 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
281 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
297 if (MI->getOpcode() == AMDGPU::DOT_4) {
299 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
300 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
301 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
302 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
303 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
304 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
305 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
306 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
313 if (Reg == AMDGPU::ALU_CONST) {
325 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
326 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
327 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
336 if (Reg == AMDGPU::ALU_CONST) {
342 if (Reg == AMDGPU::ALU_LITERAL_X) {
344 getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal)).getImm();
365 if (Reg == AMDGPU::OQAP) {
457 if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
563 AMDGPU::OpName::bank_swizzle);
637 if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
641 if (Src.first->getReg() == AMDGPU::ALU_CONST)
643 if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
644 AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
663 case AMDGPU::PRED_X:
685 return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
689 return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
690 Opcode == AMDGPU::BRANCH_COND_f32;
711 // AMDGPU::BRANCH* instructions are only available after isel and are not
720 while (I != MBB.begin() && llvm::prior(I)->getOpcode() == AMDGPU::JUMP) {
732 if (LastOpc == AMDGPU::JUMP) {
735 } else if (LastOpc == AMDGPU::JUMP_COND) {
743 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
754 if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
763 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
776 case AMDGPU::GPRI32RegClassID: return AMDGPU::BRANCH_COND_i32;
777 case AMDGPU::GPRF32RegClassID: return AMDGPU::BRANCH_COND_f32;
785 if (It->getOpcode() == AMDGPU::CF_ALU ||
786 It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
802 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
810 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
812 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
816 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
817 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
825 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
827 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
828 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
832 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
833 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
853 case AMDGPU::JUMP_COND: {
860 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
861 CfAlu->setDesc(get(AMDGPU::CF_ALU));
864 case AMDGPU::JUMP:
878 case AMDGPU::JUMP_COND: {
885 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
886 CfAlu->setDesc(get(AMDGPU::CF_ALU));
889 case AMDGPU::JUMP:
905 case AMDGPU::PRED_SEL_ONE:
906 case AMDGPU::PRED_SEL_ZERO:
907 case AMDGPU::PREDICATE_BIT:
919 if (MI->getOpcode() == AMDGPU::KILLGT) {
921 } else if (MI->getOpcode() == AMDGPU::CF_ALU) {
994 case AMDGPU::PRED_SEL_ZERO:
995 MO2.setReg(AMDGPU::PRED_SEL_ONE);
997 case AMDGPU::PRED_SEL_ONE:
998 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
1025 if (MI->getOpcode() == AMDGPU::CF_ALU) {
1030 if (MI->getOpcode() == AMDGPU::DOT_4) {
1031 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_X))
1033 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Y))
1035 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Z))
1037 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_W))
1040 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1048 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1079 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1082 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1096 return &AMDGPU::R600_TReg32_XRegClass;
1103 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
1104 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1105 AMDGPU::AR_X, OffsetReg);
1106 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1108 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1110 .addReg(AMDGPU::AR_X,
1112 setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1);
1120 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
1121 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1122 AMDGPU::AR_X,
1124 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1125 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1128 .addReg(AMDGPU::AR_X,
1130 setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1);
1173 .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
1194 OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
1195 OPERAND_CASE(AMDGPU::OpName::update_pred)
1196 OPERAND_CASE(AMDGPU::OpName::write)
1197 OPERAND_CASE(AMDGPU::OpName::omod)
1198 OPERAND_CASE(AMDGPU::OpName::dst_rel)
1199 OPERAND_CASE(AMDGPU::OpName::clamp)
1200 OPERAND_CASE(AMDGPU::OpName::src0)
1201 OPERAND_CASE(AMDGPU::OpName::src0_neg)
1202 OPERAND_CASE(AMDGPU::OpName::src0_rel)
1203 OPERAND_CASE(AMDGPU::OpName::src0_abs)
1204 OPERAND_CASE(AMDGPU::OpName::src0_sel)
1205 OPERAND_CASE(AMDGPU::OpName::src1)
1206 OPERAND_CASE(AMDGPU::OpName::src1_neg)
1207 OPERAND_CASE(AMDGPU::OpName::src1_rel)
1208 OPERAND_CASE(AMDGPU::OpName::src1_abs)
1209 OPERAND_CASE(AMDGPU::OpName::src1_sel)
1210 OPERAND_CASE(AMDGPU::OpName::pred_sel)
1221 assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
1225 Opcode = AMDGPU::DOT4_r600;
1227 Opcode = AMDGPU::DOT4_eg;
1230 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1232 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1236 AMDGPU::OpName::update_exec_mask,
1237 AMDGPU::OpName::update_pred,
1238 AMDGPU::OpName::write,
1239 AMDGPU::OpName::omod,
1240 AMDGPU::OpName::dst_rel,
1241 AMDGPU::OpName::clamp,
1242 AMDGPU::OpName::src0_neg,
1243 AMDGPU::OpName::src0_rel,
1244 AMDGPU::OpName::src0_abs,
1245 AMDGPU::OpName::src0_sel,
1246 AMDGPU::OpName::src1_neg,
1247 AMDGPU::OpName::src1_rel,
1248 AMDGPU::OpName::src1_abs,
1249 AMDGPU::OpName::src1_sel,
1253 getSlotedOps(AMDGPU::OpName::pred_sel, Slot)));
1254 MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel))
1271 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
1272 AMDGPU::ALU_LITERAL_X);
1273 setImmOperand(MovImm, AMDGPU::OpName::literal, Imm);
1280 return buildDefaultInstruction(*MBB, I, AMDGPU::MOV, DstReg, SrcReg);
1288 return AMDGPU::getNamedOperandIdx(Opcode, Op);
1319 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp);
1322 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write);
1326 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last);
1330 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break;
1331 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break;
1332 case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break;
1341 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break;
1342 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break;