Searched refs:uint32_t (Results 376 - 400 of 3101) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddm_services.h56 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
62 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
63 uint32_t value, const char *func_name);
71 static inline uint32_t dm_read_index_reg(
74 uint32_t index)
82 uint32_t index,
83 uint32_t value)
88 static inline uint32_t get_reg_field_value_ex(
89 uint32_t reg_valu
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddpp.h66 uint32_t raw;
164 uint32_t is_enabled;
165 uint32_t igam_lut_mode;
166 uint32_t igam_input_format;
167 uint32_t dgam_lut_mode;
168 uint32_t rgam_lut_mode;
170 uint32_t gamut_remap_mode;
171 uint32_t gamut_remap_c11_c12;
172 uint32_t gamut_remap_c13_c14;
173 uint32_t gamut_remap_c21_c2
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H A Ddchubbub.h50 uint32_t wm_set;
51 uint32_t data_urgent;
52 uint32_t pte_meta_urgent;
53 uint32_t sr_enter;
54 uint32_t sr_exit;
55 uint32_t dram_clk_change;
56 uint32_t usr_retrain;
57 uint32_t fclk_pstate_change;
58 uint32_t sr_enter_exit_Z8;
59 uint32_t sr_enter_Z
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/linux-master/fs/jffs2/
H A Dnodelist.h88 uint32_t flash_offset;
91 uint32_t __totlen; /* This may die; use ref_totlen(c, jeb, ) below */
174 uint32_t ino;
179 uint32_t pino_nlink; /* Directories store parent inode
216 uint32_t ofs; /* The offset to which the data of this node belongs */
217 uint32_t size;
218 uint32_t frags; /* Number of fragments which currently refer
232 uint32_t version;
233 uint32_t data_crc;
234 uint32_t partial_cr
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mode.h152 uint32_t mask_clk_reg;
153 uint32_t mask_data_reg;
154 uint32_t a_clk_reg;
155 uint32_t a_data_reg;
156 uint32_t en_clk_reg;
157 uint32_t en_data_reg;
158 uint32_t y_clk_reg;
159 uint32_t y_data_reg;
160 uint32_t mask_clk_mask;
161 uint32_t mask_data_mas
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H A Dvcn_sw_ring.c28 u64 seq, uint32_t flags)
45 struct amdgpu_ib *ib, uint32_t flags)
47 uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
56 void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
57 uint32_t val, uint32_t mask)
66 uint32_t vmid, uint64_t pd_addr)
69 uint32_t data0, data1, mask;
80 void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
81 uint32_t va
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H A Damdgpu_amdkfd_gfx_v10.c44 static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
45 uint32_t queue, uint32_t vmid)
57 static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
58 uint32_t queue_id)
60 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
61 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
67 uint32_t pipe_id, uint32_t queue_i
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H A Damdgpu_amdkfd_gfx_v9.c50 static void kgd_gfx_v9_lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
51 uint32_t queue, uint32_t vmid, uint32_t inst)
57 static void kgd_gfx_v9_unlock_srbm(struct amdgpu_device *adev, uint32_t inst)
63 void kgd_gfx_v9_acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
64 uint32_t queue_id, uint32_t inst)
66 uint32_t me
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H A Damdgpu_amdkfd_gfx_v11.c42 static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
43 uint32_t queue, uint32_t vmid)
55 static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
56 uint32_t queue_id)
58 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
59 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
65 uint32_t pipe_id, uint32_t queue_i
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H A Damdgpu_virt.h65 uint32_t *cpu_addr;
200 uint32_t checksum;
204 uint32_t driver_cert;
206 uint32_t os_info;
208 uint32_t fb_usage;
210 uint32_t gfx_usage;
212 uint32_t gfx_health;
214 uint32_t compute_usage;
216 uint32_t compute_health;
218 uint32_t vce_enc_usag
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/linux-master/include/linux/
H A Dfsi.h18 uint32_t addr;
19 uint32_t size;
22 extern int fsi_device_read(struct fsi_device *dev, uint32_t addr,
24 extern int fsi_device_write(struct fsi_device *dev, uint32_t addr,
63 uint32_t addr, uint32_t size);
65 uint32_t addr, uint32_t size);
66 extern int fsi_slave_read(struct fsi_slave *slave, uint32_t addr,
68 extern int fsi_slave_write(struct fsi_slave *slave, uint32_t add
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/linux-master/tools/testing/selftests/powerpc/cache_shape/
H A Dcache_shape.c31 static void print_size(const char *label, uint32_t val)
36 static void print_geo(const char *label, uint32_t val)
64 print_size("L1I ", (uint32_t)p->a_un.a_val);
70 print_geo("L1I ", (uint32_t)p->a_un.a_val);
76 print_size("L1D ", (uint32_t)p->a_un.a_val);
82 print_geo("L1D ", (uint32_t)p->a_un.a_val);
88 print_size("L2 ", (uint32_t)p->a_un.a_val);
94 print_geo("L2 ", (uint32_t)p->a_un.a_val);
100 print_size("L3 ", (uint32_t)p->a_un.a_val);
106 print_geo("L3 ", (uint32_t)
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/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_priv.h215 const uint32_t *ih_ring_entry, uint32_t *patched_ihre,
218 const uint32_t *ih_ring_entry);
222 uint32_t gfx_target_version;
232 uint32_t no_atomic_fw_version;
242 uint32_t range_start;
243 uint32_t range_end;
245 uint32_t *cpu_ptr;
250 uint32_t first_vmid_kfd;
251 uint32_t last_vmid_kf
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H A Dkfd_device_queue_manager.h49 uint32_t cmd:3;
50 uint32_t:1; member in struct:SQ_CMD_BITS::__anon318
51 uint32_t mode:3;
52 uint32_t check_vmid:1;
53 uint32_t trap_id:3;
54 uint32_t:5; member in struct:SQ_CMD_BITS::__anon318
55 uint32_t wave_id:4;
56 uint32_t simd_id:2;
57 uint32_t:2; member in struct:SQ_CMD_BITS::__anon318
58 uint32_t queue_i
59 uint32_t:1; member in struct:SQ_CMD_BITS::__anon318
72 uint32_t:5; member in struct:GRBM_GFX_INDEX_BITS::__anon319
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/
H A Dreg_helper.h383 { uint32_t val = REG_UPDATE(reg, f1, v1); \
387 { uint32_t val = REG_UPDATE(reg, f1, v1); \
391 uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
392 uint8_t shift, uint32_t mask, uint32_t *field_value);
394 uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
395 uint8_t shift1, uint32_t mask1, uint32_t *field_value
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/linux-master/sound/soc/sof/
H A Dipc4-topology.h104 * Use LARGE_CONFIG_SET to setup attenuation on output pins. Data is just uint32_t.
135 uint32_t priority;
136 uint32_t lp_mode;
137 uint32_t mem_usage;
138 uint32_t core_id;
192 uint32_t node_id;
193 uint32_t dma_buffer_size;
194 uint32_t config_length;
195 uint32_t config_data[];
208 uint32_t copier_feature_mas
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/linux-master/drivers/scsi/csiostor/
H A Dcsio_wr.h158 uint32_t reserved6;
209 uint32_t eqid;
235 uint32_t len; /* Buffer size */
245 uint32_t nsge; /* Number of SG elements */
246 uint32_t tmo; /* Driver timeout */
247 uint32_t datadir; /* Data direction */
328 uint32_t size1;
330 uint32_t size2;
343 uint32_t totlen; /* Total length */
350 typedef void (*iq_handler_t)(struct csio_hw *, void *, uint32_t,
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.h35 uint32_t numFractionalBits;
76 uint32_t MmHubPadding[7]; // SMU internal use
121 uint32_t FClk;
122 uint32_t MemClk;
123 uint32_t Voltage;
131 uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
132 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
133 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
134 uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
135 uint32_t VClock
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/linux-master/include/linux/soc/qcom/
H A Dapr.h45 uint32_t opcode;
46 uint32_t status;
64 uint32_t token;
65 uint32_t opcode;
80 uint32_t version:4;
81 uint32_t hdr_size:4;
82 uint32_t pkt_size:24;
83 uint32_t dest_domain:8;
84 uint32_t src_domain:8;
85 uint32_t reserve
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/linux-master/drivers/scsi/aic7xxx/aicasm/
H A Daicasm_insformat.h50 uint32_t immediate : 8,
57 uint32_t parity : 1,
69 uint32_t shift_control : 8,
76 uint32_t parity : 1,
88 uint32_t immediate : 8,
94 uint32_t parity : 1,
105 uint32_t opcode_ext : 8,
112 uint32_t parity : 1,
124 uint32_t opcode_ext : 8,
130 uint32_t parit
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/linux-master/drivers/gpu/drm/amd/display/dc/basics/
H A Dconversion.c82 uint32_t buffer_size)
88 uint32_t i;
91 uint32_t reg_value =
132 uint32_t buffer_size)
138 static uint32_t find_gcd(uint32_t a, uint32_t b)
140 uint32_t remainder;
150 void reduce_fraction(uint32_t num, uint32_t de
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/linux-master/arch/csky/abiv1/
H A Dalignment.c13 static inline uint32_t get_ptreg(struct pt_regs *regs, uint32_t rx)
15 return rx == 15 ? regs->lr : *((uint32_t *)&(regs->a0) - 2 + rx);
18 static inline void put_ptreg(struct pt_regs *regs, uint32_t rx, uint32_t val)
23 *((uint32_t *)&(regs->a0) - 2 + rx) = val;
32 static int ldb_asm(uint32_t addr, uint32_t *valp)
34 uint32_t val;
65 static int stb_asm(uint32_t add
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/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_0.h376 uint32_t Spare[8];
377 uint32_t MmHubPadding[8]; // SMU internal use
387 uint32_t eccPadding;
416 uint32_t a; // store in IEEE float format in this variable
417 uint32_t b; // store in IEEE float format in this variable
418 uint32_t c; // store in IEEE float format in this variable
422 uint32_t m; // store in IEEE float format in this variable
423 uint32_t b; // store in IEEE float format in this variable
427 uint32_t a; // store in IEEE float format in this variable
428 uint32_t
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/linux-master/drivers/scsi/lpfc/
H A Dlpfc_sli4.h179 uint32_t entry_count; /* Number of entries to support on the queue */
180 uint32_t entry_size; /* Size of each queue entry. */
181 uint32_t entry_cnt_per_pg;
182 uint32_t notify_interval; /* Queue Notification Interval
198 uint32_t max_proc_limit; /* Queue Processing Limit
213 uint32_t queue_claimed; /* indicates queue is being processed */
214 uint32_t queue_id; /* Queue ID assigned by the hardware */
215 uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */
216 uint32_t host_index; /* The host's index for putting or getting */
217 uint32_t hba_inde
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hpo_dp_stream_encoder.h87 uint32_t DP_STREAM_MAPPER_CONTROL0;\
88 uint32_t DP_STREAM_MAPPER_CONTROL1;\
89 uint32_t DP_STREAM_MAPPER_CONTROL2;\
90 uint32_t DP_STREAM_MAPPER_CONTROL3;\
91 uint32_t DP_STREAM_ENC_CLOCK_CONTROL;\
92 uint32_t DP_STREAM_ENC_INPUT_MUX_CONTROL;\
93 uint32_t DP_STREAM_ENC_AUDIO_CONTROL;\
94 uint32_t DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0;\
95 uint32_t DP_SYM32_ENC_CONTROL;\
96 uint32_t DP_SYM32_ENC_VID_PIXEL_FORMA
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